1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2015-2018 Broadcom */ 3 4 #include <linux/delay.h> 5 #include <linux/mutex.h> 6 #include <linux/spinlock_types.h> 7 #include <linux/workqueue.h> 8 9 #include <drm/drm_encoder.h> 10 #include <drm/drm_gem.h> 11 #include <drm/drm_gem_shmem_helper.h> 12 #include <drm/gpu_scheduler.h> 13 14 #include "uapi/drm/v3d_drm.h" 15 16 struct clk; 17 struct platform_device; 18 struct reset_control; 19 20 #define GMP_GRANULARITY (128 * 1024) 21 22 #define V3D_MMU_PAGE_SHIFT 12 23 24 #define V3D_MAX_QUEUES (V3D_CPU + 1) 25 26 static inline char *v3d_queue_to_string(enum v3d_queue queue) 27 { 28 switch (queue) { 29 case V3D_BIN: return "bin"; 30 case V3D_RENDER: return "render"; 31 case V3D_TFU: return "tfu"; 32 case V3D_CSD: return "csd"; 33 case V3D_CACHE_CLEAN: return "cache_clean"; 34 case V3D_CPU: return "cpu"; 35 } 36 return "UNKNOWN"; 37 } 38 39 struct v3d_stats { 40 u64 start_ns; 41 u64 enabled_ns; 42 u64 jobs_completed; 43 44 /* 45 * This seqcount is used to protect the access to the GPU stats 46 * variables. It must be used as, while we are reading the stats, 47 * IRQs can happen and the stats can be updated. 48 */ 49 seqcount_t lock; 50 }; 51 52 struct v3d_queue_state { 53 struct drm_gpu_scheduler sched; 54 55 u64 fence_context; 56 u64 emit_seqno; 57 58 /* Stores the GPU stats for this queue in the global context. */ 59 struct v3d_stats stats; 60 }; 61 62 /* Performance monitor object. The perform lifetime is controlled by userspace 63 * using perfmon related ioctls. A perfmon can be attached to a submit_cl 64 * request, and when this is the case, HW perf counters will be activated just 65 * before the submit_cl is submitted to the GPU and disabled when the job is 66 * done. This way, only events related to a specific job will be counted. 67 */ 68 struct v3d_perfmon { 69 /* Tracks the number of users of the perfmon, when this counter reaches 70 * zero the perfmon is destroyed. 71 */ 72 refcount_t refcnt; 73 74 /* Protects perfmon stop, as it can be invoked from multiple places. */ 75 struct mutex lock; 76 77 /* Number of counters activated in this perfmon instance 78 * (should be less than DRM_V3D_MAX_PERF_COUNTERS). 79 */ 80 u8 ncounters; 81 82 /* Events counted by the HW perf counters. */ 83 u8 counters[DRM_V3D_MAX_PERF_COUNTERS]; 84 85 /* Storage for counter values. Counters are incremented by the 86 * HW perf counter values every time the perfmon is attached 87 * to a GPU job. This way, perfmon users don't have to 88 * retrieve the results after each job if they want to track 89 * events covering several submissions. Note that counter 90 * values can't be reset, but you can fake a reset by 91 * destroying the perfmon and creating a new one. 92 */ 93 u64 values[] __counted_by(ncounters); 94 }; 95 96 struct v3d_dev { 97 struct drm_device drm; 98 99 /* Short representation (e.g. 33, 41) of the V3D tech version 100 * and revision. 101 */ 102 int ver; 103 bool single_irq_line; 104 105 void __iomem *hub_regs; 106 void __iomem *core_regs[3]; 107 void __iomem *bridge_regs; 108 void __iomem *gca_regs; 109 struct clk *clk; 110 struct reset_control *reset; 111 112 /* Virtual and DMA addresses of the single shared page table. */ 113 volatile u32 *pt; 114 dma_addr_t pt_paddr; 115 116 /* Virtual and DMA addresses of the MMU's scratch page. When 117 * a read or write is invalid in the MMU, it will be 118 * redirected here. 119 */ 120 void *mmu_scratch; 121 dma_addr_t mmu_scratch_paddr; 122 /* virtual address bits from V3D to the MMU. */ 123 int va_width; 124 125 /* Number of V3D cores. */ 126 u32 cores; 127 128 /* Allocator managing the address space. All units are in 129 * number of pages. 130 */ 131 struct drm_mm mm; 132 spinlock_t mm_lock; 133 134 struct work_struct overflow_mem_work; 135 136 struct v3d_bin_job *bin_job; 137 struct v3d_render_job *render_job; 138 struct v3d_tfu_job *tfu_job; 139 struct v3d_csd_job *csd_job; 140 struct v3d_cpu_job *cpu_job; 141 142 struct v3d_queue_state queue[V3D_MAX_QUEUES]; 143 144 /* Spinlock used to synchronize the overflow memory 145 * management against bin job submission. 146 */ 147 spinlock_t job_lock; 148 149 /* Used to track the active perfmon if any. */ 150 struct v3d_perfmon *active_perfmon; 151 152 /* Protects bo_stats */ 153 struct mutex bo_lock; 154 155 /* Lock taken when resetting the GPU, to keep multiple 156 * processes from trying to park the scheduler threads and 157 * reset at once. 158 */ 159 struct mutex reset_lock; 160 161 /* Lock taken when creating and pushing the GPU scheduler 162 * jobs, to keep the sched-fence seqnos in order. 163 */ 164 struct mutex sched_lock; 165 166 /* Lock taken during a cache clean and when initiating an L2 167 * flush, to keep L2 flushes from interfering with the 168 * synchronous L2 cleans. 169 */ 170 struct mutex cache_clean_lock; 171 172 struct { 173 u32 num_allocated; 174 u32 pages_allocated; 175 } bo_stats; 176 }; 177 178 static inline struct v3d_dev * 179 to_v3d_dev(struct drm_device *dev) 180 { 181 return container_of(dev, struct v3d_dev, drm); 182 } 183 184 static inline bool 185 v3d_has_csd(struct v3d_dev *v3d) 186 { 187 return v3d->ver >= 41; 188 } 189 190 #define v3d_to_pdev(v3d) to_platform_device((v3d)->drm.dev) 191 192 /* The per-fd struct, which tracks the MMU mappings. */ 193 struct v3d_file_priv { 194 struct v3d_dev *v3d; 195 196 struct { 197 struct idr idr; 198 struct mutex lock; 199 } perfmon; 200 201 struct drm_sched_entity sched_entity[V3D_MAX_QUEUES]; 202 203 /* Stores the GPU stats for a specific queue for this fd. */ 204 struct v3d_stats stats[V3D_MAX_QUEUES]; 205 }; 206 207 struct v3d_bo { 208 struct drm_gem_shmem_object base; 209 210 struct drm_mm_node node; 211 212 /* List entry for the BO's position in 213 * v3d_render_job->unref_list 214 */ 215 struct list_head unref_head; 216 217 void *vaddr; 218 }; 219 220 static inline struct v3d_bo * 221 to_v3d_bo(struct drm_gem_object *bo) 222 { 223 return (struct v3d_bo *)bo; 224 } 225 226 struct v3d_fence { 227 struct dma_fence base; 228 struct drm_device *dev; 229 /* v3d seqno for signaled() test */ 230 u64 seqno; 231 enum v3d_queue queue; 232 }; 233 234 static inline struct v3d_fence * 235 to_v3d_fence(struct dma_fence *fence) 236 { 237 return (struct v3d_fence *)fence; 238 } 239 240 #define V3D_READ(offset) readl(v3d->hub_regs + offset) 241 #define V3D_WRITE(offset, val) writel(val, v3d->hub_regs + offset) 242 243 #define V3D_BRIDGE_READ(offset) readl(v3d->bridge_regs + offset) 244 #define V3D_BRIDGE_WRITE(offset, val) writel(val, v3d->bridge_regs + offset) 245 246 #define V3D_GCA_READ(offset) readl(v3d->gca_regs + offset) 247 #define V3D_GCA_WRITE(offset, val) writel(val, v3d->gca_regs + offset) 248 249 #define V3D_CORE_READ(core, offset) readl(v3d->core_regs[core] + offset) 250 #define V3D_CORE_WRITE(core, offset, val) writel(val, v3d->core_regs[core] + offset) 251 252 struct v3d_job { 253 struct drm_sched_job base; 254 255 struct kref refcount; 256 257 struct v3d_dev *v3d; 258 259 /* This is the array of BOs that were looked up at the start 260 * of submission. 261 */ 262 struct drm_gem_object **bo; 263 u32 bo_count; 264 265 /* v3d fence to be signaled by IRQ handler when the job is complete. */ 266 struct dma_fence *irq_fence; 267 268 /* scheduler fence for when the job is considered complete and 269 * the BO reservations can be released. 270 */ 271 struct dma_fence *done_fence; 272 273 /* Pointer to a performance monitor object if the user requested it, 274 * NULL otherwise. 275 */ 276 struct v3d_perfmon *perfmon; 277 278 /* File descriptor of the process that submitted the job that could be used 279 * for collecting stats by process of GPU usage. 280 */ 281 struct drm_file *file; 282 283 /* Callback for the freeing of the job on refcount going to 0. */ 284 void (*free)(struct kref *ref); 285 }; 286 287 struct v3d_bin_job { 288 struct v3d_job base; 289 290 /* GPU virtual addresses of the start/end of the CL job. */ 291 u32 start, end; 292 293 u32 timedout_ctca, timedout_ctra; 294 295 /* Corresponding render job, for attaching our overflow memory. */ 296 struct v3d_render_job *render; 297 298 /* Submitted tile memory allocation start/size, tile state. */ 299 u32 qma, qms, qts; 300 }; 301 302 struct v3d_render_job { 303 struct v3d_job base; 304 305 /* GPU virtual addresses of the start/end of the CL job. */ 306 u32 start, end; 307 308 u32 timedout_ctca, timedout_ctra; 309 310 /* List of overflow BOs used in the job that need to be 311 * released once the job is complete. 312 */ 313 struct list_head unref_list; 314 }; 315 316 struct v3d_tfu_job { 317 struct v3d_job base; 318 319 struct drm_v3d_submit_tfu args; 320 }; 321 322 struct v3d_csd_job { 323 struct v3d_job base; 324 325 u32 timedout_batches; 326 327 struct drm_v3d_submit_csd args; 328 }; 329 330 enum v3d_cpu_job_type { 331 V3D_CPU_JOB_TYPE_INDIRECT_CSD = 1, 332 V3D_CPU_JOB_TYPE_TIMESTAMP_QUERY, 333 V3D_CPU_JOB_TYPE_RESET_TIMESTAMP_QUERY, 334 V3D_CPU_JOB_TYPE_COPY_TIMESTAMP_QUERY, 335 V3D_CPU_JOB_TYPE_RESET_PERFORMANCE_QUERY, 336 V3D_CPU_JOB_TYPE_COPY_PERFORMANCE_QUERY, 337 }; 338 339 struct v3d_timestamp_query { 340 /* Offset of this query in the timestamp BO for its value. */ 341 u32 offset; 342 343 /* Syncobj that indicates the timestamp availability */ 344 struct drm_syncobj *syncobj; 345 }; 346 347 /* Number of perfmons required to handle all supported performance counters */ 348 #define V3D_MAX_PERFMONS DIV_ROUND_UP(V3D_PERFCNT_NUM, \ 349 DRM_V3D_MAX_PERF_COUNTERS) 350 351 struct v3d_performance_query { 352 /* Performance monitor IDs for this query */ 353 u32 kperfmon_ids[V3D_MAX_PERFMONS]; 354 355 /* Syncobj that indicates the query availability */ 356 struct drm_syncobj *syncobj; 357 }; 358 359 struct v3d_indirect_csd_info { 360 /* Indirect CSD */ 361 struct v3d_csd_job *job; 362 363 /* Clean cache job associated to the Indirect CSD job */ 364 struct v3d_job *clean_job; 365 366 /* Offset within the BO where the workgroup counts are stored */ 367 u32 offset; 368 369 /* Workgroups size */ 370 u32 wg_size; 371 372 /* Indices of the uniforms with the workgroup dispatch counts 373 * in the uniform stream. 374 */ 375 u32 wg_uniform_offsets[3]; 376 377 /* Indirect BO */ 378 struct drm_gem_object *indirect; 379 380 /* Context of the Indirect CSD job */ 381 struct ww_acquire_ctx acquire_ctx; 382 }; 383 384 struct v3d_timestamp_query_info { 385 struct v3d_timestamp_query *queries; 386 387 u32 count; 388 }; 389 390 struct v3d_performance_query_info { 391 struct v3d_performance_query *queries; 392 393 /* Number of performance queries */ 394 u32 count; 395 396 /* Number of performance monitors related to that query pool */ 397 u32 nperfmons; 398 399 /* Number of performance counters related to that query pool */ 400 u32 ncounters; 401 }; 402 403 struct v3d_copy_query_results_info { 404 /* Define if should write to buffer using 64 or 32 bits */ 405 bool do_64bit; 406 407 /* Define if it can write to buffer even if the query is not available */ 408 bool do_partial; 409 410 /* Define if it should write availability bit to buffer */ 411 bool availability_bit; 412 413 /* Offset of the copy buffer in the BO */ 414 u32 offset; 415 416 /* Stride of the copy buffer in the BO */ 417 u32 stride; 418 }; 419 420 struct v3d_cpu_job { 421 struct v3d_job base; 422 423 enum v3d_cpu_job_type job_type; 424 425 struct v3d_indirect_csd_info indirect_csd; 426 427 struct v3d_timestamp_query_info timestamp_query; 428 429 struct v3d_copy_query_results_info copy; 430 431 struct v3d_performance_query_info performance_query; 432 }; 433 434 typedef void (*v3d_cpu_job_fn)(struct v3d_cpu_job *); 435 436 struct v3d_submit_outsync { 437 struct drm_syncobj *syncobj; 438 }; 439 440 struct v3d_submit_ext { 441 u32 flags; 442 u32 wait_stage; 443 444 u32 in_sync_count; 445 u64 in_syncs; 446 447 u32 out_sync_count; 448 struct v3d_submit_outsync *out_syncs; 449 }; 450 451 /** 452 * __wait_for - magic wait macro 453 * 454 * Macro to help avoid open coding check/wait/timeout patterns. Note that it's 455 * important that we check the condition again after having timed out, since the 456 * timeout could be due to preemption or similar and we've never had a chance to 457 * check the condition before the timeout. 458 */ 459 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \ 460 const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \ 461 long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \ 462 int ret__; \ 463 might_sleep(); \ 464 for (;;) { \ 465 const bool expired__ = ktime_after(ktime_get_raw(), end__); \ 466 OP; \ 467 /* Guarantee COND check prior to timeout */ \ 468 barrier(); \ 469 if (COND) { \ 470 ret__ = 0; \ 471 break; \ 472 } \ 473 if (expired__) { \ 474 ret__ = -ETIMEDOUT; \ 475 break; \ 476 } \ 477 usleep_range(wait__, wait__ * 2); \ 478 if (wait__ < (Wmax)) \ 479 wait__ <<= 1; \ 480 } \ 481 ret__; \ 482 }) 483 484 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \ 485 (Wmax)) 486 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000) 487 488 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) 489 { 490 /* nsecs_to_jiffies64() does not guard against overflow */ 491 if ((NSEC_PER_SEC % HZ) != 0 && 492 div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ) 493 return MAX_JIFFY_OFFSET; 494 495 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); 496 } 497 498 /* v3d_bo.c */ 499 struct drm_gem_object *v3d_create_object(struct drm_device *dev, size_t size); 500 void v3d_free_object(struct drm_gem_object *gem_obj); 501 struct v3d_bo *v3d_bo_create(struct drm_device *dev, struct drm_file *file_priv, 502 size_t size); 503 void v3d_get_bo_vaddr(struct v3d_bo *bo); 504 void v3d_put_bo_vaddr(struct v3d_bo *bo); 505 int v3d_create_bo_ioctl(struct drm_device *dev, void *data, 506 struct drm_file *file_priv); 507 int v3d_mmap_bo_ioctl(struct drm_device *dev, void *data, 508 struct drm_file *file_priv); 509 int v3d_get_bo_offset_ioctl(struct drm_device *dev, void *data, 510 struct drm_file *file_priv); 511 int v3d_wait_bo_ioctl(struct drm_device *dev, void *data, 512 struct drm_file *file_priv); 513 struct drm_gem_object *v3d_prime_import_sg_table(struct drm_device *dev, 514 struct dma_buf_attachment *attach, 515 struct sg_table *sgt); 516 517 /* v3d_debugfs.c */ 518 void v3d_debugfs_init(struct drm_minor *minor); 519 520 /* v3d_drv.c */ 521 void v3d_get_stats(const struct v3d_stats *stats, u64 timestamp, 522 u64 *active_runtime, u64 *jobs_completed); 523 524 /* v3d_fence.c */ 525 extern const struct dma_fence_ops v3d_fence_ops; 526 struct dma_fence *v3d_fence_create(struct v3d_dev *v3d, enum v3d_queue queue); 527 528 /* v3d_gem.c */ 529 int v3d_gem_init(struct drm_device *dev); 530 void v3d_gem_destroy(struct drm_device *dev); 531 void v3d_reset(struct v3d_dev *v3d); 532 void v3d_invalidate_caches(struct v3d_dev *v3d); 533 void v3d_clean_caches(struct v3d_dev *v3d); 534 535 /* v3d_submit.c */ 536 void v3d_job_cleanup(struct v3d_job *job); 537 void v3d_job_put(struct v3d_job *job); 538 int v3d_submit_cl_ioctl(struct drm_device *dev, void *data, 539 struct drm_file *file_priv); 540 int v3d_submit_tfu_ioctl(struct drm_device *dev, void *data, 541 struct drm_file *file_priv); 542 int v3d_submit_csd_ioctl(struct drm_device *dev, void *data, 543 struct drm_file *file_priv); 544 int v3d_submit_cpu_ioctl(struct drm_device *dev, void *data, 545 struct drm_file *file_priv); 546 547 /* v3d_irq.c */ 548 int v3d_irq_init(struct v3d_dev *v3d); 549 void v3d_irq_enable(struct v3d_dev *v3d); 550 void v3d_irq_disable(struct v3d_dev *v3d); 551 void v3d_irq_reset(struct v3d_dev *v3d); 552 553 /* v3d_mmu.c */ 554 int v3d_mmu_set_page_table(struct v3d_dev *v3d); 555 void v3d_mmu_insert_ptes(struct v3d_bo *bo); 556 void v3d_mmu_remove_ptes(struct v3d_bo *bo); 557 558 /* v3d_sched.c */ 559 void v3d_job_update_stats(struct v3d_job *job, enum v3d_queue queue); 560 int v3d_sched_init(struct v3d_dev *v3d); 561 void v3d_sched_fini(struct v3d_dev *v3d); 562 563 /* v3d_perfmon.c */ 564 void v3d_perfmon_get(struct v3d_perfmon *perfmon); 565 void v3d_perfmon_put(struct v3d_perfmon *perfmon); 566 void v3d_perfmon_start(struct v3d_dev *v3d, struct v3d_perfmon *perfmon); 567 void v3d_perfmon_stop(struct v3d_dev *v3d, struct v3d_perfmon *perfmon, 568 bool capture); 569 struct v3d_perfmon *v3d_perfmon_find(struct v3d_file_priv *v3d_priv, int id); 570 void v3d_perfmon_open_file(struct v3d_file_priv *v3d_priv); 571 void v3d_perfmon_close_file(struct v3d_file_priv *v3d_priv); 572 int v3d_perfmon_create_ioctl(struct drm_device *dev, void *data, 573 struct drm_file *file_priv); 574 int v3d_perfmon_destroy_ioctl(struct drm_device *dev, void *data, 575 struct drm_file *file_priv); 576 int v3d_perfmon_get_values_ioctl(struct drm_device *dev, void *data, 577 struct drm_file *file_priv); 578 579 /* v3d_sysfs.c */ 580 int v3d_sysfs_init(struct device *dev); 581 void v3d_sysfs_destroy(struct device *dev); 582