1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2015-2018 Broadcom */ 3 4 #include <linux/delay.h> 5 #include <linux/mutex.h> 6 #include <linux/pm_runtime.h> 7 #include <linux/spinlock_types.h> 8 #include <linux/workqueue.h> 9 10 #include <drm/drm_device.h> 11 #include <drm/drm_exec.h> 12 #include <drm/drm_gem.h> 13 #include <drm/drm_gem_shmem_helper.h> 14 #include <drm/gpu_scheduler.h> 15 16 #include "v3d_performance_counters.h" 17 18 #include "uapi/drm/v3d_drm.h" 19 20 struct clk; 21 struct platform_device; 22 struct reset_control; 23 24 #define V3D_MMU_PAGE_SHIFT 12 25 #define V3D_PAGE_FACTOR (PAGE_SIZE >> V3D_MMU_PAGE_SHIFT) 26 27 #define V3D_MAX_QUEUES (V3D_CPU + 1) 28 29 static inline char *v3d_queue_to_string(enum v3d_queue queue) 30 { 31 switch (queue) { 32 case V3D_BIN: return "bin"; 33 case V3D_RENDER: return "render"; 34 case V3D_TFU: return "tfu"; 35 case V3D_CSD: return "csd"; 36 case V3D_CACHE_CLEAN: return "cache_clean"; 37 case V3D_CPU: return "cpu"; 38 } 39 return "UNKNOWN"; 40 } 41 42 struct v3d_stats { 43 struct kref refcount; 44 45 u64 start_ns; 46 u64 enabled_ns; 47 u64 jobs_completed; 48 49 /* 50 * This seqcount is used to protect the access to the GPU stats 51 * variables. It must be used as, while we are reading the stats, 52 * IRQs can happen and the stats can be updated. 53 * 54 * However, we use the raw seqcount helpers to interact with this lock 55 * to avoid false positives from lockdep, which is unable to detect that 56 * our readers are never from irq or softirq context, and that, for CPU 57 * job queues, even the write side never is. 58 */ 59 seqcount_t lock; 60 61 atomic_t reset_counter; 62 }; 63 64 struct v3d_queue_state { 65 struct drm_gpu_scheduler sched; 66 67 u64 fence_context; 68 u64 emit_seqno; 69 70 /* Stores the GPU stats for this queue in the global context. */ 71 struct v3d_stats *stats; 72 73 /* Currently active job for this queue */ 74 struct v3d_job *active_job; 75 spinlock_t queue_lock; 76 }; 77 78 /* Performance monitor object 79 * 80 * The performance monitor (perfmon) lifetime is controlled by userspace using 81 * perfmon related ioctls. A perfmon can be attached to a CL or CSD submission 82 * request, and when it is, HW performance counters will be activated just 83 * before the job is submitted to the GPU and disabled when the job is done. 84 * This way, only events related to a specific submission will be counted. 85 */ 86 struct v3d_perfmon { 87 /* Tracks the number of users of the perfmon, when this counter reaches 88 * zero the perfmon is destroyed. 89 */ 90 refcount_t refcnt; 91 92 /* Number of counters activated in this perfmon instance 93 * (should be less than DRM_V3D_MAX_PERF_COUNTERS). 94 */ 95 u8 ncounters; 96 97 /* Events counted by the HW perf counters. */ 98 u8 counters[DRM_V3D_MAX_PERF_COUNTERS]; 99 100 /* Storage for counter values. Counters are incremented by the 101 * HW perf counter values every time the perfmon is attached 102 * to a GPU job. This way, perfmon users don't have to 103 * retrieve the results after each job if they want to track 104 * events covering several submissions. Note that counter 105 * values can't be reset, but you can fake a reset by 106 * destroying the perfmon and creating a new one. 107 */ 108 u64 values[] __counted_by(ncounters); 109 }; 110 111 enum v3d_gen { 112 V3D_GEN_33 = 33, 113 V3D_GEN_41 = 41, 114 V3D_GEN_42 = 42, 115 V3D_GEN_71 = 71, 116 }; 117 118 enum v3d_irq { 119 V3D_CORE_IRQ, 120 V3D_HUB_IRQ, 121 V3D_MAX_IRQS, 122 }; 123 124 struct v3d_dev { 125 struct drm_device drm; 126 127 /* Short representation (e.g. 33, 41) of the V3D tech version */ 128 enum v3d_gen ver; 129 130 /* Short representation (e.g. 5, 6) of the V3D tech revision */ 131 int rev; 132 133 bool single_irq_line; 134 135 int irq[V3D_MAX_IRQS]; 136 137 struct v3d_perfmon_info perfmon_info; 138 139 void __iomem *hub_regs; 140 void __iomem *core_regs[3]; 141 void __iomem *bridge_regs; 142 void __iomem *gca_regs; 143 void __iomem *sms_regs; 144 struct clk *clk; 145 struct reset_control *reset; 146 147 /* Virtual and DMA addresses of the single shared page table. */ 148 volatile u32 *pt; 149 dma_addr_t pt_paddr; 150 151 /* Virtual and DMA addresses of the MMU's scratch page. When 152 * a read or write is invalid in the MMU, it will be 153 * redirected here. 154 */ 155 void *mmu_scratch; 156 dma_addr_t mmu_scratch_paddr; 157 /* virtual address bits from V3D to the MMU. */ 158 int va_width; 159 160 /* Number of V3D cores. */ 161 u32 cores; 162 163 /* Allocator managing the address space. All units are in 164 * number of pages. 165 */ 166 struct drm_mm mm; 167 spinlock_t mm_lock; 168 169 struct work_struct overflow_mem_work; 170 171 struct v3d_queue_state queue[V3D_MAX_QUEUES]; 172 173 /* 174 * Tracks the performance monitor state and consistency. 175 * 176 * When a non-global perfmon is attached to a job, the scheduler must 177 * not run any other job on the HW concurrently (otherwise, the 178 * counters would be polluted by unrelated work). 179 */ 180 struct { 181 /* Protects @active. */ 182 spinlock_t lock; 183 184 /* Perfmon currently programmed in HW (or NULL if none). */ 185 struct v3d_perfmon *active; 186 187 /* Finished fence of the most recently submitted job that 188 * opened a serialization window (i.e. a job with a non-global 189 * perfmon attached). 190 */ 191 struct dma_fence *fence; 192 193 /* Finished fence of the most recently submitted job on each HW 194 * queue. Used so that a new perfmon-carrying job can depend on 195 * every job currently in-flight across all queues. 196 */ 197 struct dma_fence *last_hw_fence[V3D_MAX_QUEUES]; 198 } perfmon_state; 199 200 /* Protects bo_stats */ 201 struct mutex bo_lock; 202 203 /* Lock taken when resetting the GPU, to keep multiple 204 * processes from trying to park the scheduler threads and 205 * reset at once. 206 */ 207 struct mutex reset_lock; 208 209 /* Lock taken when creating and pushing the GPU scheduler 210 * jobs, to keep the sched-fence seqnos in order. 211 */ 212 struct mutex sched_lock; 213 214 /* Lock taken during a cache clean and when initiating an L2 215 * flush, to keep L2 flushes from interfering with the 216 * synchronous L2 cleans. 217 */ 218 struct mutex cache_clean_lock; 219 220 struct { 221 u32 num_allocated; 222 u32 pages_allocated; 223 } bo_stats; 224 225 /* To support a performance analysis tool in user space, we require 226 * a single, globally configured performance monitor (perfmon) for 227 * all jobs. 228 */ 229 struct v3d_perfmon *global_perfmon; 230 231 /* Global reset counter incremented on each GPU reset. */ 232 atomic_t reset_counter; 233 }; 234 235 static inline struct v3d_dev * 236 to_v3d_dev(struct drm_device *dev) 237 { 238 return container_of(dev, struct v3d_dev, drm); 239 } 240 241 static inline bool 242 v3d_has_csd(struct v3d_dev *v3d) 243 { 244 return v3d->ver >= V3D_GEN_41; 245 } 246 247 #define v3d_to_pdev(v3d) to_platform_device((v3d)->drm.dev) 248 249 /* The per-fd struct, which tracks the MMU mappings. */ 250 struct v3d_file_priv { 251 struct v3d_dev *v3d; 252 253 struct xarray perfmons; 254 255 struct drm_sched_entity sched_entity[V3D_MAX_QUEUES]; 256 257 /* Stores the GPU stats for a specific queue for this fd. */ 258 struct v3d_stats *stats[V3D_MAX_QUEUES]; 259 }; 260 261 struct v3d_bo { 262 struct drm_gem_shmem_object base; 263 264 struct drm_mm_node node; 265 266 /* List entry for the BO's position in 267 * v3d_render_job->unref_list 268 */ 269 struct list_head unref_head; 270 271 void *vaddr; 272 }; 273 274 static inline struct v3d_bo * 275 to_v3d_bo(struct drm_gem_object *bo) 276 { 277 return (struct v3d_bo *)bo; 278 } 279 280 struct v3d_fence { 281 struct dma_fence base; 282 struct drm_device *dev; 283 /* v3d seqno for signaled() test */ 284 u64 seqno; 285 enum v3d_queue queue; 286 }; 287 288 static inline struct v3d_fence * 289 to_v3d_fence(struct dma_fence *fence) 290 { 291 return (struct v3d_fence *)fence; 292 } 293 294 #define V3D_READ(offset) readl(v3d->hub_regs + offset) 295 #define V3D_WRITE(offset, val) writel(val, v3d->hub_regs + offset) 296 297 #define V3D_BRIDGE_READ(offset) readl(v3d->bridge_regs + offset) 298 #define V3D_BRIDGE_WRITE(offset, val) writel(val, v3d->bridge_regs + offset) 299 300 #define V3D_GCA_READ(offset) readl(v3d->gca_regs + offset) 301 #define V3D_GCA_WRITE(offset, val) writel(val, v3d->gca_regs + offset) 302 303 #define V3D_SMS_IDLE 0x0 304 #define V3D_SMS_ISOLATING_FOR_RESET 0xa 305 #define V3D_SMS_RESETTING 0xb 306 #define V3D_SMS_ISOLATING_FOR_POWER_OFF 0xc 307 #define V3D_SMS_POWER_OFF_STATE 0xd 308 309 #define V3D_SMS_READ(offset) readl(v3d->sms_regs + (offset)) 310 #define V3D_SMS_WRITE(offset, val) writel(val, v3d->sms_regs + (offset)) 311 312 #define V3D_CORE_READ(core, offset) readl(v3d->core_regs[core] + offset) 313 #define V3D_CORE_WRITE(core, offset, val) writel(val, v3d->core_regs[core] + offset) 314 315 #define V3D_MAX_JOBS_PER_SUBMISSION 3 316 317 /* Per-ioctl submission context */ 318 struct v3d_submit { 319 struct v3d_dev *v3d; 320 321 struct drm_file *file_priv; 322 323 /* DRM exec context for this submission. */ 324 struct drm_exec exec; 325 326 /* Ordered array of jobs forming the submission chain. Jobs are 327 * appended via v3d_submit_add_job(), then chained and pushed to 328 * the scheduler by v3d_submit_jobs(). 329 */ 330 struct v3d_job *jobs[V3D_MAX_JOBS_PER_SUBMISSION]; 331 332 /* Number of jobs currently in @jobs. */ 333 u32 job_count; 334 }; 335 336 struct v3d_job { 337 struct drm_sched_job base; 338 339 struct kref refcount; 340 341 struct v3d_dev *v3d; 342 343 /* The queue that the job was submitted on. */ 344 enum v3d_queue queue; 345 346 /* This is the array of BOs that were looked up at the start 347 * of submission. 348 */ 349 struct drm_gem_object **bo; 350 u32 bo_count; 351 352 /* v3d fence to be signaled by IRQ handler when the job is complete. */ 353 struct dma_fence *irq_fence; 354 355 /* scheduler fence for when the job is considered complete and 356 * the BO reservations can be released. 357 */ 358 struct dma_fence *done_fence; 359 360 /* Pointer to a performance monitor object if the user requested it, 361 * NULL otherwise. 362 */ 363 struct v3d_perfmon *perfmon; 364 365 /* File descriptor of the process that submitted the job that could be used 366 * to collect per-process information about the GPU. 367 */ 368 struct v3d_file_priv *file_priv; 369 370 /* Pointers to this job's per-fd and global queue stats. */ 371 struct v3d_stats *client_stats; 372 struct v3d_stats *global_stats; 373 374 /* Callback for the freeing of the job on refcount going to 0. */ 375 void (*free)(struct kref *ref); 376 377 bool has_pm_ref; 378 379 /* Whether the job needs implicit dependencies, i.e. must wait for 380 * other contexts still writing its BOs. 381 */ 382 bool has_implicit_dep; 383 }; 384 385 struct v3d_bin_job { 386 struct v3d_job base; 387 388 /* GPU virtual addresses of the start/end of the CL job. */ 389 u32 start, end; 390 391 u32 timedout_ctca, timedout_ctra; 392 393 /* Corresponding render job, for attaching our overflow memory. */ 394 struct v3d_render_job *render; 395 396 /* Submitted tile memory allocation start/size, tile state. */ 397 u32 qma, qms, qts; 398 }; 399 400 struct v3d_render_job { 401 struct v3d_job base; 402 403 /* GPU virtual addresses of the start/end of the CL job. */ 404 u32 start, end; 405 406 u32 timedout_ctca, timedout_ctra; 407 408 /* List of overflow BOs used in the job that need to be 409 * released once the job is complete. 410 */ 411 struct list_head unref_list; 412 }; 413 414 struct v3d_tfu_job { 415 struct v3d_job base; 416 417 struct drm_v3d_submit_tfu args; 418 }; 419 420 struct v3d_csd_job { 421 struct v3d_job base; 422 423 u32 timedout_batches; 424 425 struct drm_v3d_submit_csd args; 426 }; 427 428 enum v3d_cpu_job_type { 429 V3D_CPU_JOB_TYPE_INDIRECT_CSD = 1, 430 V3D_CPU_JOB_TYPE_TIMESTAMP_QUERY, 431 V3D_CPU_JOB_TYPE_RESET_TIMESTAMP_QUERY, 432 V3D_CPU_JOB_TYPE_COPY_TIMESTAMP_QUERY, 433 V3D_CPU_JOB_TYPE_RESET_PERFORMANCE_QUERY, 434 V3D_CPU_JOB_TYPE_COPY_PERFORMANCE_QUERY, 435 }; 436 437 struct v3d_timestamp_query { 438 /* Offset of this query in the timestamp BO for its value. */ 439 u32 offset; 440 441 /* Syncobj that indicates the timestamp availability */ 442 struct drm_syncobj *syncobj; 443 }; 444 445 struct v3d_performance_query { 446 /* Performance monitor IDs for this query */ 447 u32 *kperfmon_ids; 448 449 /* Syncobj that indicates the query availability */ 450 struct drm_syncobj *syncobj; 451 }; 452 453 struct v3d_indirect_csd_info { 454 /* Indirect CSD */ 455 struct v3d_csd_job *job; 456 457 /* Indirect CSD args, stashed by the extension parser and later used 458 * to create the CSD job from them. 459 */ 460 struct drm_v3d_submit_csd args; 461 462 /* Offset within the BO where the workgroup counts are stored */ 463 u32 offset; 464 465 /* Workgroups size */ 466 u32 wg_size; 467 468 /* Indices of the uniforms with the workgroup dispatch counts 469 * in the uniform stream. 470 */ 471 u32 wg_uniform_offsets[3]; 472 473 /* Indirect BO */ 474 struct drm_gem_object *indirect; 475 }; 476 477 struct v3d_timestamp_query_info { 478 struct v3d_timestamp_query *queries; 479 480 u32 count; 481 }; 482 483 struct v3d_performance_query_info { 484 struct v3d_performance_query *queries; 485 486 /* Number of performance queries */ 487 u32 count; 488 489 /* Number of performance monitors related to that query pool */ 490 u32 nperfmons; 491 492 /* Number of performance counters related to that query pool */ 493 u32 ncounters; 494 }; 495 496 struct v3d_copy_query_results_info { 497 /* Define if should write to buffer using 64 or 32 bits */ 498 bool do_64bit; 499 500 /* Define if it can write to buffer even if the query is not available */ 501 bool do_partial; 502 503 /* Define if it should write availability bit to buffer */ 504 bool availability_bit; 505 506 /* Offset of the copy buffer in the BO */ 507 u32 offset; 508 509 /* Stride of the copy buffer in the BO */ 510 u32 stride; 511 }; 512 513 struct v3d_cpu_job { 514 struct v3d_job base; 515 516 enum v3d_cpu_job_type job_type; 517 518 struct v3d_indirect_csd_info indirect_csd; 519 520 struct v3d_timestamp_query_info timestamp_query; 521 522 struct v3d_copy_query_results_info copy; 523 524 struct v3d_performance_query_info performance_query; 525 }; 526 527 typedef void (*v3d_cpu_job_fn)(struct v3d_cpu_job *); 528 529 struct v3d_submit_outsync { 530 struct drm_syncobj *syncobj; 531 }; 532 533 struct v3d_submit_ext { 534 u32 flags; 535 u32 wait_stage; 536 537 u32 in_sync_count; 538 u64 in_syncs; 539 540 u32 out_sync_count; 541 struct v3d_submit_outsync *out_syncs; 542 }; 543 544 /** 545 * __wait_for - magic wait macro 546 * 547 * Macro to help avoid open coding check/wait/timeout patterns. Note that it's 548 * important that we check the condition again after having timed out, since the 549 * timeout could be due to preemption or similar and we've never had a chance to 550 * check the condition before the timeout. 551 */ 552 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \ 553 const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \ 554 long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \ 555 int ret__; \ 556 might_sleep(); \ 557 for (;;) { \ 558 const bool expired__ = ktime_after(ktime_get_raw(), end__); \ 559 OP; \ 560 /* Guarantee COND check prior to timeout */ \ 561 barrier(); \ 562 if (COND) { \ 563 ret__ = 0; \ 564 break; \ 565 } \ 566 if (expired__) { \ 567 ret__ = -ETIMEDOUT; \ 568 break; \ 569 } \ 570 usleep_range(wait__, wait__ * 2); \ 571 if (wait__ < (Wmax)) \ 572 wait__ <<= 1; \ 573 } \ 574 ret__; \ 575 }) 576 577 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \ 578 (Wmax)) 579 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000) 580 581 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) 582 { 583 /* nsecs_to_jiffies64() does not guard against overflow */ 584 if ((NSEC_PER_SEC % HZ) != 0 && 585 div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ) 586 return MAX_JIFFY_OFFSET; 587 588 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); 589 } 590 591 /* v3d_bo.c */ 592 struct drm_gem_object *v3d_create_object(struct drm_device *dev, size_t size); 593 void v3d_free_object(struct drm_gem_object *gem_obj); 594 struct v3d_bo *v3d_bo_create(struct drm_device *dev, struct drm_file *file_priv, 595 size_t size); 596 void v3d_get_bo_vaddr(struct v3d_bo *bo); 597 void v3d_put_bo_vaddr(struct v3d_bo *bo); 598 int v3d_create_bo_ioctl(struct drm_device *dev, void *data, 599 struct drm_file *file_priv); 600 int v3d_mmap_bo_ioctl(struct drm_device *dev, void *data, 601 struct drm_file *file_priv); 602 int v3d_get_bo_offset_ioctl(struct drm_device *dev, void *data, 603 struct drm_file *file_priv); 604 int v3d_wait_bo_ioctl(struct drm_device *dev, void *data, 605 struct drm_file *file_priv); 606 struct drm_gem_object *v3d_prime_import_sg_table(struct drm_device *dev, 607 struct dma_buf_attachment *attach, 608 struct sg_table *sgt); 609 610 /* v3d_debugfs.c */ 611 void v3d_debugfs_init(struct drm_minor *minor); 612 613 /* v3d_drv.c */ 614 void v3d_get_stats(const struct v3d_stats *stats, u64 timestamp, 615 u64 *active_runtime, u64 *jobs_completed); 616 617 /* v3d_fence.c */ 618 extern const struct dma_fence_ops v3d_fence_ops; 619 struct dma_fence *v3d_fence_create(struct v3d_dev *v3d, enum v3d_queue q); 620 621 /* v3d_gem.c */ 622 extern bool super_pages; 623 void v3d_init_hw_state(struct v3d_dev *v3d); 624 int v3d_gem_init(struct drm_device *dev); 625 void v3d_gem_destroy(struct drm_device *dev); 626 void v3d_reset_sms(struct v3d_dev *v3d); 627 void v3d_reset(struct v3d_dev *v3d); 628 void v3d_invalidate_caches(struct v3d_dev *v3d); 629 void v3d_clean_caches(struct v3d_dev *v3d); 630 631 /* v3d_submit.c */ 632 void v3d_job_cleanup(struct v3d_job *job); 633 void v3d_job_put(struct v3d_job *job); 634 int v3d_submit_cl_ioctl(struct drm_device *dev, void *data, 635 struct drm_file *file_priv); 636 int v3d_submit_tfu_ioctl(struct drm_device *dev, void *data, 637 struct drm_file *file_priv); 638 int v3d_submit_csd_ioctl(struct drm_device *dev, void *data, 639 struct drm_file *file_priv); 640 int v3d_submit_cpu_ioctl(struct drm_device *dev, void *data, 641 struct drm_file *file_priv); 642 643 /* v3d_irq.c */ 644 int v3d_irq_init(struct v3d_dev *v3d); 645 void v3d_irq_enable(struct v3d_dev *v3d); 646 void v3d_irq_disable(struct v3d_dev *v3d); 647 void v3d_irq_reset(struct v3d_dev *v3d); 648 649 /* v3d_mmu.c */ 650 int v3d_mmu_flush_all(struct v3d_dev *v3d); 651 int v3d_mmu_set_page_table(struct v3d_dev *v3d); 652 void v3d_mmu_insert_ptes(struct v3d_bo *bo); 653 void v3d_mmu_remove_ptes(struct v3d_bo *bo); 654 655 /* v3d_power.c */ 656 int v3d_power_suspend(struct device *dev); 657 int v3d_power_resume(struct device *dev); 658 659 static __always_inline int v3d_pm_runtime_get(struct v3d_dev *v3d) 660 { 661 return pm_runtime_resume_and_get(v3d->drm.dev); 662 } 663 664 static __always_inline int v3d_pm_runtime_put(struct v3d_dev *v3d) 665 { 666 return pm_runtime_put_autosuspend(v3d->drm.dev); 667 } 668 669 /* v3d_sched.c */ 670 void v3d_timestamp_query_info_free(struct v3d_timestamp_query_info *query_info, 671 unsigned int count); 672 void v3d_performance_query_info_free(struct v3d_performance_query_info *query_info, 673 unsigned int count); 674 struct v3d_stats *v3d_stats_alloc(void); 675 void v3d_stats_release(struct kref *refcount); 676 void v3d_job_update_stats(struct v3d_job *job); 677 int v3d_sched_init(struct v3d_dev *v3d); 678 void v3d_sched_fini(struct v3d_dev *v3d); 679 680 static inline struct v3d_stats *v3d_stats_get(struct v3d_stats *stats) 681 { 682 kref_get(&stats->refcount); 683 return stats; 684 } 685 686 static inline void v3d_stats_put(struct v3d_stats *stats) 687 { 688 kref_put(&stats->refcount, v3d_stats_release); 689 } 690 691 /* v3d_perfmon.c */ 692 void v3d_perfmon_init(struct v3d_dev *v3d); 693 void v3d_perfmon_get(struct v3d_perfmon *perfmon); 694 void v3d_perfmon_put(struct v3d_perfmon *perfmon); 695 void v3d_perfmon_start(struct v3d_dev *v3d, struct v3d_perfmon *perfmon); 696 void v3d_perfmon_stop(struct v3d_dev *v3d, struct v3d_perfmon *perfmon, 697 bool capture); 698 void v3d_perfmon_stop_locked(struct v3d_dev *v3d, struct v3d_perfmon *perfmon, 699 bool capture); 700 void v3d_perfmon_suspend(struct v3d_dev *v3d); 701 void v3d_perfmon_resume(struct v3d_dev *v3d); 702 struct v3d_perfmon *v3d_perfmon_find(struct v3d_file_priv *v3d_priv, int id); 703 void v3d_perfmon_open_file(struct v3d_file_priv *v3d_priv); 704 void v3d_perfmon_close_file(struct v3d_file_priv *v3d_priv); 705 int v3d_perfmon_create_ioctl(struct drm_device *dev, void *data, 706 struct drm_file *file_priv); 707 int v3d_perfmon_destroy_ioctl(struct drm_device *dev, void *data, 708 struct drm_file *file_priv); 709 int v3d_perfmon_get_values_ioctl(struct drm_device *dev, void *data, 710 struct drm_file *file_priv); 711 int v3d_perfmon_get_counter_ioctl(struct drm_device *dev, void *data, 712 struct drm_file *file_priv); 713 int v3d_perfmon_set_global_ioctl(struct drm_device *dev, void *data, 714 struct drm_file *file_priv); 715 716 /* v3d_sysfs.c */ 717 int v3d_sysfs_init(struct device *dev); 718 void v3d_sysfs_destroy(struct device *dev); 719