1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2015-2018 Broadcom */ 3 4 #include <linux/delay.h> 5 #include <linux/mutex.h> 6 #include <linux/spinlock_types.h> 7 #include <linux/workqueue.h> 8 9 #include <drm/drm_encoder.h> 10 #include <drm/drm_gem.h> 11 #include <drm/drm_gem_shmem_helper.h> 12 #include <drm/gpu_scheduler.h> 13 14 #include "v3d_performance_counters.h" 15 16 #include "uapi/drm/v3d_drm.h" 17 18 struct clk; 19 struct platform_device; 20 struct reset_control; 21 22 #define GMP_GRANULARITY (128 * 1024) 23 24 #define V3D_MMU_PAGE_SHIFT 12 25 26 #define V3D_MAX_QUEUES (V3D_CPU + 1) 27 28 static inline char *v3d_queue_to_string(enum v3d_queue queue) 29 { 30 switch (queue) { 31 case V3D_BIN: return "bin"; 32 case V3D_RENDER: return "render"; 33 case V3D_TFU: return "tfu"; 34 case V3D_CSD: return "csd"; 35 case V3D_CACHE_CLEAN: return "cache_clean"; 36 case V3D_CPU: return "cpu"; 37 } 38 return "UNKNOWN"; 39 } 40 41 struct v3d_stats { 42 u64 start_ns; 43 u64 enabled_ns; 44 u64 jobs_completed; 45 46 /* 47 * This seqcount is used to protect the access to the GPU stats 48 * variables. It must be used as, while we are reading the stats, 49 * IRQs can happen and the stats can be updated. 50 */ 51 seqcount_t lock; 52 }; 53 54 struct v3d_queue_state { 55 struct drm_gpu_scheduler sched; 56 57 u64 fence_context; 58 u64 emit_seqno; 59 60 /* Stores the GPU stats for this queue in the global context. */ 61 struct v3d_stats stats; 62 }; 63 64 /* Performance monitor object. The perform lifetime is controlled by userspace 65 * using perfmon related ioctls. A perfmon can be attached to a submit_cl 66 * request, and when this is the case, HW perf counters will be activated just 67 * before the submit_cl is submitted to the GPU and disabled when the job is 68 * done. This way, only events related to a specific job will be counted. 69 */ 70 struct v3d_perfmon { 71 /* Tracks the number of users of the perfmon, when this counter reaches 72 * zero the perfmon is destroyed. 73 */ 74 refcount_t refcnt; 75 76 /* Protects perfmon stop, as it can be invoked from multiple places. */ 77 struct mutex lock; 78 79 /* Number of counters activated in this perfmon instance 80 * (should be less than DRM_V3D_MAX_PERF_COUNTERS). 81 */ 82 u8 ncounters; 83 84 /* Events counted by the HW perf counters. */ 85 u8 counters[DRM_V3D_MAX_PERF_COUNTERS]; 86 87 /* Storage for counter values. Counters are incremented by the 88 * HW perf counter values every time the perfmon is attached 89 * to a GPU job. This way, perfmon users don't have to 90 * retrieve the results after each job if they want to track 91 * events covering several submissions. Note that counter 92 * values can't be reset, but you can fake a reset by 93 * destroying the perfmon and creating a new one. 94 */ 95 u64 values[] __counted_by(ncounters); 96 }; 97 98 struct v3d_dev { 99 struct drm_device drm; 100 101 /* Short representation (e.g. 33, 41) of the V3D tech version 102 * and revision. 103 */ 104 int ver; 105 bool single_irq_line; 106 107 /* Different revisions of V3D have different total number of performance 108 * counters 109 */ 110 unsigned int max_counters; 111 112 void __iomem *hub_regs; 113 void __iomem *core_regs[3]; 114 void __iomem *bridge_regs; 115 void __iomem *gca_regs; 116 struct clk *clk; 117 struct reset_control *reset; 118 119 /* Virtual and DMA addresses of the single shared page table. */ 120 volatile u32 *pt; 121 dma_addr_t pt_paddr; 122 123 /* Virtual and DMA addresses of the MMU's scratch page. When 124 * a read or write is invalid in the MMU, it will be 125 * redirected here. 126 */ 127 void *mmu_scratch; 128 dma_addr_t mmu_scratch_paddr; 129 /* virtual address bits from V3D to the MMU. */ 130 int va_width; 131 132 /* Number of V3D cores. */ 133 u32 cores; 134 135 /* Allocator managing the address space. All units are in 136 * number of pages. 137 */ 138 struct drm_mm mm; 139 spinlock_t mm_lock; 140 141 struct work_struct overflow_mem_work; 142 143 struct v3d_bin_job *bin_job; 144 struct v3d_render_job *render_job; 145 struct v3d_tfu_job *tfu_job; 146 struct v3d_csd_job *csd_job; 147 struct v3d_cpu_job *cpu_job; 148 149 struct v3d_queue_state queue[V3D_MAX_QUEUES]; 150 151 /* Spinlock used to synchronize the overflow memory 152 * management against bin job submission. 153 */ 154 spinlock_t job_lock; 155 156 /* Used to track the active perfmon if any. */ 157 struct v3d_perfmon *active_perfmon; 158 159 /* Protects bo_stats */ 160 struct mutex bo_lock; 161 162 /* Lock taken when resetting the GPU, to keep multiple 163 * processes from trying to park the scheduler threads and 164 * reset at once. 165 */ 166 struct mutex reset_lock; 167 168 /* Lock taken when creating and pushing the GPU scheduler 169 * jobs, to keep the sched-fence seqnos in order. 170 */ 171 struct mutex sched_lock; 172 173 /* Lock taken during a cache clean and when initiating an L2 174 * flush, to keep L2 flushes from interfering with the 175 * synchronous L2 cleans. 176 */ 177 struct mutex cache_clean_lock; 178 179 struct { 180 u32 num_allocated; 181 u32 pages_allocated; 182 } bo_stats; 183 }; 184 185 static inline struct v3d_dev * 186 to_v3d_dev(struct drm_device *dev) 187 { 188 return container_of(dev, struct v3d_dev, drm); 189 } 190 191 static inline bool 192 v3d_has_csd(struct v3d_dev *v3d) 193 { 194 return v3d->ver >= 41; 195 } 196 197 #define v3d_to_pdev(v3d) to_platform_device((v3d)->drm.dev) 198 199 /* The per-fd struct, which tracks the MMU mappings. */ 200 struct v3d_file_priv { 201 struct v3d_dev *v3d; 202 203 struct { 204 struct idr idr; 205 struct mutex lock; 206 } perfmon; 207 208 struct drm_sched_entity sched_entity[V3D_MAX_QUEUES]; 209 210 /* Stores the GPU stats for a specific queue for this fd. */ 211 struct v3d_stats stats[V3D_MAX_QUEUES]; 212 }; 213 214 struct v3d_bo { 215 struct drm_gem_shmem_object base; 216 217 struct drm_mm_node node; 218 219 /* List entry for the BO's position in 220 * v3d_render_job->unref_list 221 */ 222 struct list_head unref_head; 223 224 void *vaddr; 225 }; 226 227 static inline struct v3d_bo * 228 to_v3d_bo(struct drm_gem_object *bo) 229 { 230 return (struct v3d_bo *)bo; 231 } 232 233 struct v3d_fence { 234 struct dma_fence base; 235 struct drm_device *dev; 236 /* v3d seqno for signaled() test */ 237 u64 seqno; 238 enum v3d_queue queue; 239 }; 240 241 static inline struct v3d_fence * 242 to_v3d_fence(struct dma_fence *fence) 243 { 244 return (struct v3d_fence *)fence; 245 } 246 247 #define V3D_READ(offset) readl(v3d->hub_regs + offset) 248 #define V3D_WRITE(offset, val) writel(val, v3d->hub_regs + offset) 249 250 #define V3D_BRIDGE_READ(offset) readl(v3d->bridge_regs + offset) 251 #define V3D_BRIDGE_WRITE(offset, val) writel(val, v3d->bridge_regs + offset) 252 253 #define V3D_GCA_READ(offset) readl(v3d->gca_regs + offset) 254 #define V3D_GCA_WRITE(offset, val) writel(val, v3d->gca_regs + offset) 255 256 #define V3D_CORE_READ(core, offset) readl(v3d->core_regs[core] + offset) 257 #define V3D_CORE_WRITE(core, offset, val) writel(val, v3d->core_regs[core] + offset) 258 259 struct v3d_job { 260 struct drm_sched_job base; 261 262 struct kref refcount; 263 264 struct v3d_dev *v3d; 265 266 /* This is the array of BOs that were looked up at the start 267 * of submission. 268 */ 269 struct drm_gem_object **bo; 270 u32 bo_count; 271 272 /* v3d fence to be signaled by IRQ handler when the job is complete. */ 273 struct dma_fence *irq_fence; 274 275 /* scheduler fence for when the job is considered complete and 276 * the BO reservations can be released. 277 */ 278 struct dma_fence *done_fence; 279 280 /* Pointer to a performance monitor object if the user requested it, 281 * NULL otherwise. 282 */ 283 struct v3d_perfmon *perfmon; 284 285 /* File descriptor of the process that submitted the job that could be used 286 * for collecting stats by process of GPU usage. 287 */ 288 struct drm_file *file; 289 290 /* Callback for the freeing of the job on refcount going to 0. */ 291 void (*free)(struct kref *ref); 292 }; 293 294 struct v3d_bin_job { 295 struct v3d_job base; 296 297 /* GPU virtual addresses of the start/end of the CL job. */ 298 u32 start, end; 299 300 u32 timedout_ctca, timedout_ctra; 301 302 /* Corresponding render job, for attaching our overflow memory. */ 303 struct v3d_render_job *render; 304 305 /* Submitted tile memory allocation start/size, tile state. */ 306 u32 qma, qms, qts; 307 }; 308 309 struct v3d_render_job { 310 struct v3d_job base; 311 312 /* GPU virtual addresses of the start/end of the CL job. */ 313 u32 start, end; 314 315 u32 timedout_ctca, timedout_ctra; 316 317 /* List of overflow BOs used in the job that need to be 318 * released once the job is complete. 319 */ 320 struct list_head unref_list; 321 }; 322 323 struct v3d_tfu_job { 324 struct v3d_job base; 325 326 struct drm_v3d_submit_tfu args; 327 }; 328 329 struct v3d_csd_job { 330 struct v3d_job base; 331 332 u32 timedout_batches; 333 334 struct drm_v3d_submit_csd args; 335 }; 336 337 enum v3d_cpu_job_type { 338 V3D_CPU_JOB_TYPE_INDIRECT_CSD = 1, 339 V3D_CPU_JOB_TYPE_TIMESTAMP_QUERY, 340 V3D_CPU_JOB_TYPE_RESET_TIMESTAMP_QUERY, 341 V3D_CPU_JOB_TYPE_COPY_TIMESTAMP_QUERY, 342 V3D_CPU_JOB_TYPE_RESET_PERFORMANCE_QUERY, 343 V3D_CPU_JOB_TYPE_COPY_PERFORMANCE_QUERY, 344 }; 345 346 struct v3d_timestamp_query { 347 /* Offset of this query in the timestamp BO for its value. */ 348 u32 offset; 349 350 /* Syncobj that indicates the timestamp availability */ 351 struct drm_syncobj *syncobj; 352 }; 353 354 /* Number of perfmons required to handle all supported performance counters */ 355 #define V3D_MAX_PERFMONS DIV_ROUND_UP(V3D_MAX_COUNTERS, \ 356 DRM_V3D_MAX_PERF_COUNTERS) 357 358 struct v3d_performance_query { 359 /* Performance monitor IDs for this query */ 360 u32 kperfmon_ids[V3D_MAX_PERFMONS]; 361 362 /* Syncobj that indicates the query availability */ 363 struct drm_syncobj *syncobj; 364 }; 365 366 struct v3d_indirect_csd_info { 367 /* Indirect CSD */ 368 struct v3d_csd_job *job; 369 370 /* Clean cache job associated to the Indirect CSD job */ 371 struct v3d_job *clean_job; 372 373 /* Offset within the BO where the workgroup counts are stored */ 374 u32 offset; 375 376 /* Workgroups size */ 377 u32 wg_size; 378 379 /* Indices of the uniforms with the workgroup dispatch counts 380 * in the uniform stream. 381 */ 382 u32 wg_uniform_offsets[3]; 383 384 /* Indirect BO */ 385 struct drm_gem_object *indirect; 386 387 /* Context of the Indirect CSD job */ 388 struct ww_acquire_ctx acquire_ctx; 389 }; 390 391 struct v3d_timestamp_query_info { 392 struct v3d_timestamp_query *queries; 393 394 u32 count; 395 }; 396 397 struct v3d_performance_query_info { 398 struct v3d_performance_query *queries; 399 400 /* Number of performance queries */ 401 u32 count; 402 403 /* Number of performance monitors related to that query pool */ 404 u32 nperfmons; 405 406 /* Number of performance counters related to that query pool */ 407 u32 ncounters; 408 }; 409 410 struct v3d_copy_query_results_info { 411 /* Define if should write to buffer using 64 or 32 bits */ 412 bool do_64bit; 413 414 /* Define if it can write to buffer even if the query is not available */ 415 bool do_partial; 416 417 /* Define if it should write availability bit to buffer */ 418 bool availability_bit; 419 420 /* Offset of the copy buffer in the BO */ 421 u32 offset; 422 423 /* Stride of the copy buffer in the BO */ 424 u32 stride; 425 }; 426 427 struct v3d_cpu_job { 428 struct v3d_job base; 429 430 enum v3d_cpu_job_type job_type; 431 432 struct v3d_indirect_csd_info indirect_csd; 433 434 struct v3d_timestamp_query_info timestamp_query; 435 436 struct v3d_copy_query_results_info copy; 437 438 struct v3d_performance_query_info performance_query; 439 }; 440 441 typedef void (*v3d_cpu_job_fn)(struct v3d_cpu_job *); 442 443 struct v3d_submit_outsync { 444 struct drm_syncobj *syncobj; 445 }; 446 447 struct v3d_submit_ext { 448 u32 flags; 449 u32 wait_stage; 450 451 u32 in_sync_count; 452 u64 in_syncs; 453 454 u32 out_sync_count; 455 struct v3d_submit_outsync *out_syncs; 456 }; 457 458 /** 459 * __wait_for - magic wait macro 460 * 461 * Macro to help avoid open coding check/wait/timeout patterns. Note that it's 462 * important that we check the condition again after having timed out, since the 463 * timeout could be due to preemption or similar and we've never had a chance to 464 * check the condition before the timeout. 465 */ 466 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \ 467 const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \ 468 long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \ 469 int ret__; \ 470 might_sleep(); \ 471 for (;;) { \ 472 const bool expired__ = ktime_after(ktime_get_raw(), end__); \ 473 OP; \ 474 /* Guarantee COND check prior to timeout */ \ 475 barrier(); \ 476 if (COND) { \ 477 ret__ = 0; \ 478 break; \ 479 } \ 480 if (expired__) { \ 481 ret__ = -ETIMEDOUT; \ 482 break; \ 483 } \ 484 usleep_range(wait__, wait__ * 2); \ 485 if (wait__ < (Wmax)) \ 486 wait__ <<= 1; \ 487 } \ 488 ret__; \ 489 }) 490 491 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \ 492 (Wmax)) 493 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000) 494 495 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) 496 { 497 /* nsecs_to_jiffies64() does not guard against overflow */ 498 if ((NSEC_PER_SEC % HZ) != 0 && 499 div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ) 500 return MAX_JIFFY_OFFSET; 501 502 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); 503 } 504 505 /* v3d_bo.c */ 506 struct drm_gem_object *v3d_create_object(struct drm_device *dev, size_t size); 507 void v3d_free_object(struct drm_gem_object *gem_obj); 508 struct v3d_bo *v3d_bo_create(struct drm_device *dev, struct drm_file *file_priv, 509 size_t size); 510 void v3d_get_bo_vaddr(struct v3d_bo *bo); 511 void v3d_put_bo_vaddr(struct v3d_bo *bo); 512 int v3d_create_bo_ioctl(struct drm_device *dev, void *data, 513 struct drm_file *file_priv); 514 int v3d_mmap_bo_ioctl(struct drm_device *dev, void *data, 515 struct drm_file *file_priv); 516 int v3d_get_bo_offset_ioctl(struct drm_device *dev, void *data, 517 struct drm_file *file_priv); 518 int v3d_wait_bo_ioctl(struct drm_device *dev, void *data, 519 struct drm_file *file_priv); 520 struct drm_gem_object *v3d_prime_import_sg_table(struct drm_device *dev, 521 struct dma_buf_attachment *attach, 522 struct sg_table *sgt); 523 524 /* v3d_debugfs.c */ 525 void v3d_debugfs_init(struct drm_minor *minor); 526 527 /* v3d_drv.c */ 528 void v3d_get_stats(const struct v3d_stats *stats, u64 timestamp, 529 u64 *active_runtime, u64 *jobs_completed); 530 531 /* v3d_fence.c */ 532 extern const struct dma_fence_ops v3d_fence_ops; 533 struct dma_fence *v3d_fence_create(struct v3d_dev *v3d, enum v3d_queue queue); 534 535 /* v3d_gem.c */ 536 int v3d_gem_init(struct drm_device *dev); 537 void v3d_gem_destroy(struct drm_device *dev); 538 void v3d_reset(struct v3d_dev *v3d); 539 void v3d_invalidate_caches(struct v3d_dev *v3d); 540 void v3d_clean_caches(struct v3d_dev *v3d); 541 542 /* v3d_submit.c */ 543 void v3d_job_cleanup(struct v3d_job *job); 544 void v3d_job_put(struct v3d_job *job); 545 int v3d_submit_cl_ioctl(struct drm_device *dev, void *data, 546 struct drm_file *file_priv); 547 int v3d_submit_tfu_ioctl(struct drm_device *dev, void *data, 548 struct drm_file *file_priv); 549 int v3d_submit_csd_ioctl(struct drm_device *dev, void *data, 550 struct drm_file *file_priv); 551 int v3d_submit_cpu_ioctl(struct drm_device *dev, void *data, 552 struct drm_file *file_priv); 553 554 /* v3d_irq.c */ 555 int v3d_irq_init(struct v3d_dev *v3d); 556 void v3d_irq_enable(struct v3d_dev *v3d); 557 void v3d_irq_disable(struct v3d_dev *v3d); 558 void v3d_irq_reset(struct v3d_dev *v3d); 559 560 /* v3d_mmu.c */ 561 int v3d_mmu_set_page_table(struct v3d_dev *v3d); 562 void v3d_mmu_insert_ptes(struct v3d_bo *bo); 563 void v3d_mmu_remove_ptes(struct v3d_bo *bo); 564 565 /* v3d_sched.c */ 566 void v3d_job_update_stats(struct v3d_job *job, enum v3d_queue queue); 567 int v3d_sched_init(struct v3d_dev *v3d); 568 void v3d_sched_fini(struct v3d_dev *v3d); 569 570 /* v3d_perfmon.c */ 571 void v3d_perfmon_get(struct v3d_perfmon *perfmon); 572 void v3d_perfmon_put(struct v3d_perfmon *perfmon); 573 void v3d_perfmon_start(struct v3d_dev *v3d, struct v3d_perfmon *perfmon); 574 void v3d_perfmon_stop(struct v3d_dev *v3d, struct v3d_perfmon *perfmon, 575 bool capture); 576 struct v3d_perfmon *v3d_perfmon_find(struct v3d_file_priv *v3d_priv, int id); 577 void v3d_perfmon_open_file(struct v3d_file_priv *v3d_priv); 578 void v3d_perfmon_close_file(struct v3d_file_priv *v3d_priv); 579 int v3d_perfmon_create_ioctl(struct drm_device *dev, void *data, 580 struct drm_file *file_priv); 581 int v3d_perfmon_destroy_ioctl(struct drm_device *dev, void *data, 582 struct drm_file *file_priv); 583 int v3d_perfmon_get_values_ioctl(struct drm_device *dev, void *data, 584 struct drm_file *file_priv); 585 int v3d_perfmon_get_counter_ioctl(struct drm_device *dev, void *data, 586 struct drm_file *file_priv); 587 588 /* v3d_sysfs.c */ 589 int v3d_sysfs_init(struct device *dev); 590 void v3d_sysfs_destroy(struct device *dev); 591