1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2015-2018 Broadcom */ 3 4 #include <linux/delay.h> 5 #include <linux/mutex.h> 6 #include <linux/spinlock_types.h> 7 #include <linux/workqueue.h> 8 9 #include <drm/drm_encoder.h> 10 #include <drm/drm_gem.h> 11 #include <drm/drm_gem_shmem_helper.h> 12 #include <drm/gpu_scheduler.h> 13 14 #include "v3d_performance_counters.h" 15 16 #include "uapi/drm/v3d_drm.h" 17 18 struct clk; 19 struct platform_device; 20 struct reset_control; 21 22 #define V3D_MMU_PAGE_SHIFT 12 23 #define V3D_PAGE_FACTOR (PAGE_SIZE >> V3D_MMU_PAGE_SHIFT) 24 25 #define V3D_MAX_QUEUES (V3D_CPU + 1) 26 27 static inline char *v3d_queue_to_string(enum v3d_queue queue) 28 { 29 switch (queue) { 30 case V3D_BIN: return "bin"; 31 case V3D_RENDER: return "render"; 32 case V3D_TFU: return "tfu"; 33 case V3D_CSD: return "csd"; 34 case V3D_CACHE_CLEAN: return "cache_clean"; 35 case V3D_CPU: return "cpu"; 36 } 37 return "UNKNOWN"; 38 } 39 40 struct v3d_stats { 41 struct kref refcount; 42 43 u64 start_ns; 44 u64 enabled_ns; 45 u64 jobs_completed; 46 47 /* 48 * This seqcount is used to protect the access to the GPU stats 49 * variables. It must be used as, while we are reading the stats, 50 * IRQs can happen and the stats can be updated. 51 * 52 * However, we use the raw seqcount helpers to interact with this lock 53 * to avoid false positives from lockdep, which is unable to detect that 54 * our readers are never from irq or softirq context, and that, for CPU 55 * job queues, even the write side never is. 56 */ 57 seqcount_t lock; 58 59 atomic_t reset_counter; 60 }; 61 62 struct v3d_queue_state { 63 struct drm_gpu_scheduler sched; 64 65 u64 fence_context; 66 u64 emit_seqno; 67 68 /* Stores the GPU stats for this queue in the global context. */ 69 struct v3d_stats *stats; 70 71 /* Currently active job for this queue */ 72 struct v3d_job *active_job; 73 spinlock_t queue_lock; 74 }; 75 76 /* Performance monitor object. The perform lifetime is controlled by userspace 77 * using perfmon related ioctls. A perfmon can be attached to a submit_cl 78 * request, and when this is the case, HW perf counters will be activated just 79 * before the submit_cl is submitted to the GPU and disabled when the job is 80 * done. This way, only events related to a specific job will be counted. 81 */ 82 struct v3d_perfmon { 83 /* Tracks the number of users of the perfmon, when this counter reaches 84 * zero the perfmon is destroyed. 85 */ 86 refcount_t refcnt; 87 88 /* Protects perfmon stop, as it can be invoked from multiple places. */ 89 struct mutex lock; 90 91 /* Number of counters activated in this perfmon instance 92 * (should be less than DRM_V3D_MAX_PERF_COUNTERS). 93 */ 94 u8 ncounters; 95 96 /* Events counted by the HW perf counters. */ 97 u8 counters[DRM_V3D_MAX_PERF_COUNTERS]; 98 99 /* Storage for counter values. Counters are incremented by the 100 * HW perf counter values every time the perfmon is attached 101 * to a GPU job. This way, perfmon users don't have to 102 * retrieve the results after each job if they want to track 103 * events covering several submissions. Note that counter 104 * values can't be reset, but you can fake a reset by 105 * destroying the perfmon and creating a new one. 106 */ 107 u64 values[] __counted_by(ncounters); 108 }; 109 110 enum v3d_gen { 111 V3D_GEN_33 = 33, 112 V3D_GEN_41 = 41, 113 V3D_GEN_42 = 42, 114 V3D_GEN_71 = 71, 115 }; 116 117 enum v3d_irq { 118 V3D_CORE_IRQ, 119 V3D_HUB_IRQ, 120 V3D_MAX_IRQS, 121 }; 122 123 struct v3d_dev { 124 struct drm_device drm; 125 126 /* Short representation (e.g. 33, 41) of the V3D tech version */ 127 enum v3d_gen ver; 128 129 /* Short representation (e.g. 5, 6) of the V3D tech revision */ 130 int rev; 131 132 bool single_irq_line; 133 134 int irq[V3D_MAX_IRQS]; 135 136 struct v3d_perfmon_info perfmon_info; 137 138 void __iomem *hub_regs; 139 void __iomem *core_regs[3]; 140 void __iomem *bridge_regs; 141 void __iomem *gca_regs; 142 void __iomem *sms_regs; 143 struct clk *clk; 144 struct reset_control *reset; 145 146 /* Virtual and DMA addresses of the single shared page table. */ 147 volatile u32 *pt; 148 dma_addr_t pt_paddr; 149 150 /* Virtual and DMA addresses of the MMU's scratch page. When 151 * a read or write is invalid in the MMU, it will be 152 * redirected here. 153 */ 154 void *mmu_scratch; 155 dma_addr_t mmu_scratch_paddr; 156 /* virtual address bits from V3D to the MMU. */ 157 int va_width; 158 159 /* Number of V3D cores. */ 160 u32 cores; 161 162 /* Allocator managing the address space. All units are in 163 * number of pages. 164 */ 165 struct drm_mm mm; 166 spinlock_t mm_lock; 167 168 struct work_struct overflow_mem_work; 169 170 struct v3d_queue_state queue[V3D_MAX_QUEUES]; 171 172 /* Used to track the active perfmon if any. */ 173 struct v3d_perfmon *active_perfmon; 174 175 /* Protects bo_stats */ 176 struct mutex bo_lock; 177 178 /* Lock taken when resetting the GPU, to keep multiple 179 * processes from trying to park the scheduler threads and 180 * reset at once. 181 */ 182 struct mutex reset_lock; 183 184 /* Lock taken when creating and pushing the GPU scheduler 185 * jobs, to keep the sched-fence seqnos in order. 186 */ 187 struct mutex sched_lock; 188 189 /* Lock taken during a cache clean and when initiating an L2 190 * flush, to keep L2 flushes from interfering with the 191 * synchronous L2 cleans. 192 */ 193 struct mutex cache_clean_lock; 194 195 struct { 196 u32 num_allocated; 197 u32 pages_allocated; 198 } bo_stats; 199 200 /* To support a performance analysis tool in user space, we require 201 * a single, globally configured performance monitor (perfmon) for 202 * all jobs. 203 */ 204 struct v3d_perfmon *global_perfmon; 205 206 /* Global reset counter incremented on each GPU reset. */ 207 atomic_t reset_counter; 208 }; 209 210 static inline struct v3d_dev * 211 to_v3d_dev(struct drm_device *dev) 212 { 213 return container_of(dev, struct v3d_dev, drm); 214 } 215 216 static inline bool 217 v3d_has_csd(struct v3d_dev *v3d) 218 { 219 return v3d->ver >= V3D_GEN_41; 220 } 221 222 #define v3d_to_pdev(v3d) to_platform_device((v3d)->drm.dev) 223 224 /* The per-fd struct, which tracks the MMU mappings. */ 225 struct v3d_file_priv { 226 struct v3d_dev *v3d; 227 228 struct xarray perfmons; 229 230 struct drm_sched_entity sched_entity[V3D_MAX_QUEUES]; 231 232 /* Stores the GPU stats for a specific queue for this fd. */ 233 struct v3d_stats *stats[V3D_MAX_QUEUES]; 234 }; 235 236 struct v3d_bo { 237 struct drm_gem_shmem_object base; 238 239 struct drm_mm_node node; 240 241 /* List entry for the BO's position in 242 * v3d_render_job->unref_list 243 */ 244 struct list_head unref_head; 245 246 void *vaddr; 247 }; 248 249 static inline struct v3d_bo * 250 to_v3d_bo(struct drm_gem_object *bo) 251 { 252 return (struct v3d_bo *)bo; 253 } 254 255 struct v3d_fence { 256 struct dma_fence base; 257 struct drm_device *dev; 258 /* v3d seqno for signaled() test */ 259 u64 seqno; 260 enum v3d_queue queue; 261 }; 262 263 static inline struct v3d_fence * 264 to_v3d_fence(struct dma_fence *fence) 265 { 266 return (struct v3d_fence *)fence; 267 } 268 269 #define V3D_READ(offset) readl(v3d->hub_regs + offset) 270 #define V3D_WRITE(offset, val) writel(val, v3d->hub_regs + offset) 271 272 #define V3D_BRIDGE_READ(offset) readl(v3d->bridge_regs + offset) 273 #define V3D_BRIDGE_WRITE(offset, val) writel(val, v3d->bridge_regs + offset) 274 275 #define V3D_GCA_READ(offset) readl(v3d->gca_regs + offset) 276 #define V3D_GCA_WRITE(offset, val) writel(val, v3d->gca_regs + offset) 277 278 #define V3D_SMS_IDLE 0x0 279 #define V3D_SMS_ISOLATING_FOR_RESET 0xa 280 #define V3D_SMS_RESETTING 0xb 281 #define V3D_SMS_ISOLATING_FOR_POWER_OFF 0xc 282 #define V3D_SMS_POWER_OFF_STATE 0xd 283 284 #define V3D_SMS_READ(offset) readl(v3d->sms_regs + (offset)) 285 #define V3D_SMS_WRITE(offset, val) writel(val, v3d->sms_regs + (offset)) 286 287 #define V3D_CORE_READ(core, offset) readl(v3d->core_regs[core] + offset) 288 #define V3D_CORE_WRITE(core, offset, val) writel(val, v3d->core_regs[core] + offset) 289 290 struct v3d_job { 291 struct drm_sched_job base; 292 293 struct kref refcount; 294 295 struct v3d_dev *v3d; 296 297 /* This is the array of BOs that were looked up at the start 298 * of submission. 299 */ 300 struct drm_gem_object **bo; 301 u32 bo_count; 302 303 /* v3d fence to be signaled by IRQ handler when the job is complete. */ 304 struct dma_fence *irq_fence; 305 306 /* scheduler fence for when the job is considered complete and 307 * the BO reservations can be released. 308 */ 309 struct dma_fence *done_fence; 310 311 /* Pointer to a performance monitor object if the user requested it, 312 * NULL otherwise. 313 */ 314 struct v3d_perfmon *perfmon; 315 316 /* File descriptor of the process that submitted the job that could be used 317 * to collect per-process information about the GPU. 318 */ 319 struct v3d_file_priv *file_priv; 320 321 /* Pointers to this job's per-fd and global queue stats. */ 322 struct v3d_stats *client_stats; 323 struct v3d_stats *global_stats; 324 325 /* Callback for the freeing of the job on refcount going to 0. */ 326 void (*free)(struct kref *ref); 327 }; 328 329 struct v3d_bin_job { 330 struct v3d_job base; 331 332 /* GPU virtual addresses of the start/end of the CL job. */ 333 u32 start, end; 334 335 u32 timedout_ctca, timedout_ctra; 336 337 /* Corresponding render job, for attaching our overflow memory. */ 338 struct v3d_render_job *render; 339 340 /* Submitted tile memory allocation start/size, tile state. */ 341 u32 qma, qms, qts; 342 }; 343 344 struct v3d_render_job { 345 struct v3d_job base; 346 347 /* GPU virtual addresses of the start/end of the CL job. */ 348 u32 start, end; 349 350 u32 timedout_ctca, timedout_ctra; 351 352 /* List of overflow BOs used in the job that need to be 353 * released once the job is complete. 354 */ 355 struct list_head unref_list; 356 }; 357 358 struct v3d_tfu_job { 359 struct v3d_job base; 360 361 struct drm_v3d_submit_tfu args; 362 }; 363 364 struct v3d_csd_job { 365 struct v3d_job base; 366 367 u32 timedout_batches; 368 369 struct drm_v3d_submit_csd args; 370 }; 371 372 enum v3d_cpu_job_type { 373 V3D_CPU_JOB_TYPE_INDIRECT_CSD = 1, 374 V3D_CPU_JOB_TYPE_TIMESTAMP_QUERY, 375 V3D_CPU_JOB_TYPE_RESET_TIMESTAMP_QUERY, 376 V3D_CPU_JOB_TYPE_COPY_TIMESTAMP_QUERY, 377 V3D_CPU_JOB_TYPE_RESET_PERFORMANCE_QUERY, 378 V3D_CPU_JOB_TYPE_COPY_PERFORMANCE_QUERY, 379 }; 380 381 struct v3d_timestamp_query { 382 /* Offset of this query in the timestamp BO for its value. */ 383 u32 offset; 384 385 /* Syncobj that indicates the timestamp availability */ 386 struct drm_syncobj *syncobj; 387 }; 388 389 struct v3d_performance_query { 390 /* Performance monitor IDs for this query */ 391 u32 *kperfmon_ids; 392 393 /* Syncobj that indicates the query availability */ 394 struct drm_syncobj *syncobj; 395 }; 396 397 struct v3d_indirect_csd_info { 398 /* Indirect CSD */ 399 struct v3d_csd_job *job; 400 401 /* Clean cache job associated to the Indirect CSD job */ 402 struct v3d_job *clean_job; 403 404 /* Offset within the BO where the workgroup counts are stored */ 405 u32 offset; 406 407 /* Workgroups size */ 408 u32 wg_size; 409 410 /* Indices of the uniforms with the workgroup dispatch counts 411 * in the uniform stream. 412 */ 413 u32 wg_uniform_offsets[3]; 414 415 /* Indirect BO */ 416 struct drm_gem_object *indirect; 417 418 /* Context of the Indirect CSD job */ 419 struct ww_acquire_ctx acquire_ctx; 420 }; 421 422 struct v3d_timestamp_query_info { 423 struct v3d_timestamp_query *queries; 424 425 u32 count; 426 }; 427 428 struct v3d_performance_query_info { 429 struct v3d_performance_query *queries; 430 431 /* Number of performance queries */ 432 u32 count; 433 434 /* Number of performance monitors related to that query pool */ 435 u32 nperfmons; 436 437 /* Number of performance counters related to that query pool */ 438 u32 ncounters; 439 }; 440 441 struct v3d_copy_query_results_info { 442 /* Define if should write to buffer using 64 or 32 bits */ 443 bool do_64bit; 444 445 /* Define if it can write to buffer even if the query is not available */ 446 bool do_partial; 447 448 /* Define if it should write availability bit to buffer */ 449 bool availability_bit; 450 451 /* Offset of the copy buffer in the BO */ 452 u32 offset; 453 454 /* Stride of the copy buffer in the BO */ 455 u32 stride; 456 }; 457 458 struct v3d_cpu_job { 459 struct v3d_job base; 460 461 enum v3d_cpu_job_type job_type; 462 463 struct v3d_indirect_csd_info indirect_csd; 464 465 struct v3d_timestamp_query_info timestamp_query; 466 467 struct v3d_copy_query_results_info copy; 468 469 struct v3d_performance_query_info performance_query; 470 }; 471 472 typedef void (*v3d_cpu_job_fn)(struct v3d_cpu_job *); 473 474 struct v3d_submit_outsync { 475 struct drm_syncobj *syncobj; 476 }; 477 478 struct v3d_submit_ext { 479 u32 flags; 480 u32 wait_stage; 481 482 u32 in_sync_count; 483 u64 in_syncs; 484 485 u32 out_sync_count; 486 struct v3d_submit_outsync *out_syncs; 487 }; 488 489 /** 490 * __wait_for - magic wait macro 491 * 492 * Macro to help avoid open coding check/wait/timeout patterns. Note that it's 493 * important that we check the condition again after having timed out, since the 494 * timeout could be due to preemption or similar and we've never had a chance to 495 * check the condition before the timeout. 496 */ 497 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \ 498 const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \ 499 long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \ 500 int ret__; \ 501 might_sleep(); \ 502 for (;;) { \ 503 const bool expired__ = ktime_after(ktime_get_raw(), end__); \ 504 OP; \ 505 /* Guarantee COND check prior to timeout */ \ 506 barrier(); \ 507 if (COND) { \ 508 ret__ = 0; \ 509 break; \ 510 } \ 511 if (expired__) { \ 512 ret__ = -ETIMEDOUT; \ 513 break; \ 514 } \ 515 usleep_range(wait__, wait__ * 2); \ 516 if (wait__ < (Wmax)) \ 517 wait__ <<= 1; \ 518 } \ 519 ret__; \ 520 }) 521 522 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \ 523 (Wmax)) 524 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000) 525 526 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) 527 { 528 /* nsecs_to_jiffies64() does not guard against overflow */ 529 if ((NSEC_PER_SEC % HZ) != 0 && 530 div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ) 531 return MAX_JIFFY_OFFSET; 532 533 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); 534 } 535 536 /* v3d_bo.c */ 537 struct drm_gem_object *v3d_create_object(struct drm_device *dev, size_t size); 538 void v3d_free_object(struct drm_gem_object *gem_obj); 539 struct v3d_bo *v3d_bo_create(struct drm_device *dev, struct drm_file *file_priv, 540 size_t size); 541 void v3d_get_bo_vaddr(struct v3d_bo *bo); 542 void v3d_put_bo_vaddr(struct v3d_bo *bo); 543 int v3d_create_bo_ioctl(struct drm_device *dev, void *data, 544 struct drm_file *file_priv); 545 int v3d_mmap_bo_ioctl(struct drm_device *dev, void *data, 546 struct drm_file *file_priv); 547 int v3d_get_bo_offset_ioctl(struct drm_device *dev, void *data, 548 struct drm_file *file_priv); 549 int v3d_wait_bo_ioctl(struct drm_device *dev, void *data, 550 struct drm_file *file_priv); 551 struct drm_gem_object *v3d_prime_import_sg_table(struct drm_device *dev, 552 struct dma_buf_attachment *attach, 553 struct sg_table *sgt); 554 555 /* v3d_debugfs.c */ 556 void v3d_debugfs_init(struct drm_minor *minor); 557 558 /* v3d_drv.c */ 559 void v3d_get_stats(const struct v3d_stats *stats, u64 timestamp, 560 u64 *active_runtime, u64 *jobs_completed); 561 562 /* v3d_fence.c */ 563 extern const struct dma_fence_ops v3d_fence_ops; 564 struct dma_fence *v3d_fence_create(struct v3d_dev *v3d, enum v3d_queue q); 565 566 /* v3d_gem.c */ 567 extern bool super_pages; 568 int v3d_gem_init(struct drm_device *dev); 569 void v3d_gem_destroy(struct drm_device *dev); 570 void v3d_reset_sms(struct v3d_dev *v3d); 571 void v3d_reset(struct v3d_dev *v3d); 572 void v3d_invalidate_caches(struct v3d_dev *v3d); 573 void v3d_clean_caches(struct v3d_dev *v3d); 574 575 /* v3d_submit.c */ 576 void v3d_job_cleanup(struct v3d_job *job); 577 void v3d_job_put(struct v3d_job *job); 578 int v3d_submit_cl_ioctl(struct drm_device *dev, void *data, 579 struct drm_file *file_priv); 580 int v3d_submit_tfu_ioctl(struct drm_device *dev, void *data, 581 struct drm_file *file_priv); 582 int v3d_submit_csd_ioctl(struct drm_device *dev, void *data, 583 struct drm_file *file_priv); 584 int v3d_submit_cpu_ioctl(struct drm_device *dev, void *data, 585 struct drm_file *file_priv); 586 587 /* v3d_irq.c */ 588 int v3d_irq_init(struct v3d_dev *v3d); 589 void v3d_irq_enable(struct v3d_dev *v3d); 590 void v3d_irq_disable(struct v3d_dev *v3d); 591 void v3d_irq_reset(struct v3d_dev *v3d); 592 593 /* v3d_mmu.c */ 594 int v3d_mmu_flush_all(struct v3d_dev *v3d); 595 int v3d_mmu_set_page_table(struct v3d_dev *v3d); 596 void v3d_mmu_insert_ptes(struct v3d_bo *bo); 597 void v3d_mmu_remove_ptes(struct v3d_bo *bo); 598 599 /* v3d_sched.c */ 600 void v3d_timestamp_query_info_free(struct v3d_timestamp_query_info *query_info, 601 unsigned int count); 602 void v3d_performance_query_info_free(struct v3d_performance_query_info *query_info, 603 unsigned int count); 604 struct v3d_stats *v3d_stats_alloc(void); 605 void v3d_stats_release(struct kref *refcount); 606 void v3d_job_update_stats(struct v3d_job *job); 607 int v3d_sched_init(struct v3d_dev *v3d); 608 void v3d_sched_fini(struct v3d_dev *v3d); 609 610 static inline struct v3d_stats *v3d_stats_get(struct v3d_stats *stats) 611 { 612 kref_get(&stats->refcount); 613 return stats; 614 } 615 616 static inline void v3d_stats_put(struct v3d_stats *stats) 617 { 618 kref_put(&stats->refcount, v3d_stats_release); 619 } 620 621 /* v3d_perfmon.c */ 622 void v3d_perfmon_init(struct v3d_dev *v3d); 623 void v3d_perfmon_get(struct v3d_perfmon *perfmon); 624 void v3d_perfmon_put(struct v3d_perfmon *perfmon); 625 void v3d_perfmon_start(struct v3d_dev *v3d, struct v3d_perfmon *perfmon); 626 void v3d_perfmon_stop(struct v3d_dev *v3d, struct v3d_perfmon *perfmon, 627 bool capture); 628 struct v3d_perfmon *v3d_perfmon_find(struct v3d_file_priv *v3d_priv, int id); 629 void v3d_perfmon_open_file(struct v3d_file_priv *v3d_priv); 630 void v3d_perfmon_close_file(struct v3d_file_priv *v3d_priv); 631 int v3d_perfmon_create_ioctl(struct drm_device *dev, void *data, 632 struct drm_file *file_priv); 633 int v3d_perfmon_destroy_ioctl(struct drm_device *dev, void *data, 634 struct drm_file *file_priv); 635 int v3d_perfmon_get_values_ioctl(struct drm_device *dev, void *data, 636 struct drm_file *file_priv); 637 int v3d_perfmon_get_counter_ioctl(struct drm_device *dev, void *data, 638 struct drm_file *file_priv); 639 int v3d_perfmon_set_global_ioctl(struct drm_device *dev, void *data, 640 struct drm_file *file_priv); 641 642 /* v3d_sysfs.c */ 643 int v3d_sysfs_init(struct device *dev); 644 void v3d_sysfs_destroy(struct device *dev); 645