1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2015-2018 Broadcom */ 3 4 #include <linux/delay.h> 5 #include <linux/mutex.h> 6 #include <linux/spinlock_types.h> 7 #include <linux/workqueue.h> 8 9 #include <drm/drm_encoder.h> 10 #include <drm/drm_gem.h> 11 #include <drm/drm_gem_shmem_helper.h> 12 #include <drm/gpu_scheduler.h> 13 14 #include "v3d_performance_counters.h" 15 16 #include "uapi/drm/v3d_drm.h" 17 18 struct clk; 19 struct platform_device; 20 struct reset_control; 21 22 #define V3D_MMU_PAGE_SHIFT 12 23 #define V3D_PAGE_FACTOR (PAGE_SIZE >> V3D_MMU_PAGE_SHIFT) 24 25 #define V3D_MAX_QUEUES (V3D_CPU + 1) 26 27 static inline char *v3d_queue_to_string(enum v3d_queue queue) 28 { 29 switch (queue) { 30 case V3D_BIN: return "bin"; 31 case V3D_RENDER: return "render"; 32 case V3D_TFU: return "tfu"; 33 case V3D_CSD: return "csd"; 34 case V3D_CACHE_CLEAN: return "cache_clean"; 35 case V3D_CPU: return "cpu"; 36 } 37 return "UNKNOWN"; 38 } 39 40 struct v3d_stats { 41 u64 start_ns; 42 u64 enabled_ns; 43 u64 jobs_completed; 44 45 /* 46 * This seqcount is used to protect the access to the GPU stats 47 * variables. It must be used as, while we are reading the stats, 48 * IRQs can happen and the stats can be updated. 49 */ 50 seqcount_t lock; 51 }; 52 53 struct v3d_queue_state { 54 struct drm_gpu_scheduler sched; 55 56 u64 fence_context; 57 u64 emit_seqno; 58 59 /* Stores the GPU stats for this queue in the global context. */ 60 struct v3d_stats stats; 61 62 /* Currently active job for this queue */ 63 struct v3d_job *active_job; 64 spinlock_t queue_lock; 65 }; 66 67 /* Performance monitor object. The perform lifetime is controlled by userspace 68 * using perfmon related ioctls. A perfmon can be attached to a submit_cl 69 * request, and when this is the case, HW perf counters will be activated just 70 * before the submit_cl is submitted to the GPU and disabled when the job is 71 * done. This way, only events related to a specific job will be counted. 72 */ 73 struct v3d_perfmon { 74 /* Tracks the number of users of the perfmon, when this counter reaches 75 * zero the perfmon is destroyed. 76 */ 77 refcount_t refcnt; 78 79 /* Protects perfmon stop, as it can be invoked from multiple places. */ 80 struct mutex lock; 81 82 /* Number of counters activated in this perfmon instance 83 * (should be less than DRM_V3D_MAX_PERF_COUNTERS). 84 */ 85 u8 ncounters; 86 87 /* Events counted by the HW perf counters. */ 88 u8 counters[DRM_V3D_MAX_PERF_COUNTERS]; 89 90 /* Storage for counter values. Counters are incremented by the 91 * HW perf counter values every time the perfmon is attached 92 * to a GPU job. This way, perfmon users don't have to 93 * retrieve the results after each job if they want to track 94 * events covering several submissions. Note that counter 95 * values can't be reset, but you can fake a reset by 96 * destroying the perfmon and creating a new one. 97 */ 98 u64 values[] __counted_by(ncounters); 99 }; 100 101 enum v3d_gen { 102 V3D_GEN_33 = 33, 103 V3D_GEN_41 = 41, 104 V3D_GEN_42 = 42, 105 V3D_GEN_71 = 71, 106 }; 107 108 enum v3d_irq { 109 V3D_CORE_IRQ, 110 V3D_HUB_IRQ, 111 V3D_MAX_IRQS, 112 }; 113 114 struct v3d_dev { 115 struct drm_device drm; 116 117 /* Short representation (e.g. 33, 41) of the V3D tech version */ 118 enum v3d_gen ver; 119 120 /* Short representation (e.g. 5, 6) of the V3D tech revision */ 121 int rev; 122 123 bool single_irq_line; 124 125 int irq[V3D_MAX_IRQS]; 126 127 struct v3d_perfmon_info perfmon_info; 128 129 void __iomem *hub_regs; 130 void __iomem *core_regs[3]; 131 void __iomem *bridge_regs; 132 void __iomem *gca_regs; 133 void __iomem *sms_regs; 134 struct clk *clk; 135 struct reset_control *reset; 136 137 /* Virtual and DMA addresses of the single shared page table. */ 138 volatile u32 *pt; 139 dma_addr_t pt_paddr; 140 141 /* Virtual and DMA addresses of the MMU's scratch page. When 142 * a read or write is invalid in the MMU, it will be 143 * redirected here. 144 */ 145 void *mmu_scratch; 146 dma_addr_t mmu_scratch_paddr; 147 /* virtual address bits from V3D to the MMU. */ 148 int va_width; 149 150 /* Number of V3D cores. */ 151 u32 cores; 152 153 /* Allocator managing the address space. All units are in 154 * number of pages. 155 */ 156 struct drm_mm mm; 157 spinlock_t mm_lock; 158 159 /* 160 * tmpfs instance used for shmem backed objects 161 */ 162 struct vfsmount *gemfs; 163 164 struct work_struct overflow_mem_work; 165 166 struct v3d_queue_state queue[V3D_MAX_QUEUES]; 167 168 /* Used to track the active perfmon if any. */ 169 struct v3d_perfmon *active_perfmon; 170 171 /* Protects bo_stats */ 172 struct mutex bo_lock; 173 174 /* Lock taken when resetting the GPU, to keep multiple 175 * processes from trying to park the scheduler threads and 176 * reset at once. 177 */ 178 struct mutex reset_lock; 179 180 /* Lock taken when creating and pushing the GPU scheduler 181 * jobs, to keep the sched-fence seqnos in order. 182 */ 183 struct mutex sched_lock; 184 185 /* Lock taken during a cache clean and when initiating an L2 186 * flush, to keep L2 flushes from interfering with the 187 * synchronous L2 cleans. 188 */ 189 struct mutex cache_clean_lock; 190 191 struct { 192 u32 num_allocated; 193 u32 pages_allocated; 194 } bo_stats; 195 196 /* To support a performance analysis tool in user space, we require 197 * a single, globally configured performance monitor (perfmon) for 198 * all jobs. 199 */ 200 struct v3d_perfmon *global_perfmon; 201 202 /* Global reset counter. The counter must be incremented when 203 * a GPU reset happens. It must be protected by @reset_lock. 204 */ 205 unsigned int reset_counter; 206 }; 207 208 static inline struct v3d_dev * 209 to_v3d_dev(struct drm_device *dev) 210 { 211 return container_of(dev, struct v3d_dev, drm); 212 } 213 214 static inline bool 215 v3d_has_csd(struct v3d_dev *v3d) 216 { 217 return v3d->ver >= V3D_GEN_41; 218 } 219 220 #define v3d_to_pdev(v3d) to_platform_device((v3d)->drm.dev) 221 222 /* The per-fd struct, which tracks the MMU mappings. */ 223 struct v3d_file_priv { 224 struct v3d_dev *v3d; 225 226 struct { 227 struct idr idr; 228 struct mutex lock; 229 } perfmon; 230 231 struct drm_sched_entity sched_entity[V3D_MAX_QUEUES]; 232 233 /* Stores the GPU stats for a specific queue for this fd. */ 234 struct v3d_stats stats[V3D_MAX_QUEUES]; 235 236 /* Per-fd reset counter, must be incremented when a job submitted 237 * by this fd causes a GPU reset. It must be protected by 238 * &struct v3d_dev->reset_lock. 239 */ 240 unsigned int reset_counter; 241 }; 242 243 struct v3d_bo { 244 struct drm_gem_shmem_object base; 245 246 struct drm_mm_node node; 247 248 /* List entry for the BO's position in 249 * v3d_render_job->unref_list 250 */ 251 struct list_head unref_head; 252 253 void *vaddr; 254 }; 255 256 static inline struct v3d_bo * 257 to_v3d_bo(struct drm_gem_object *bo) 258 { 259 return (struct v3d_bo *)bo; 260 } 261 262 struct v3d_fence { 263 struct dma_fence base; 264 struct drm_device *dev; 265 /* v3d seqno for signaled() test */ 266 u64 seqno; 267 enum v3d_queue queue; 268 }; 269 270 static inline struct v3d_fence * 271 to_v3d_fence(struct dma_fence *fence) 272 { 273 return (struct v3d_fence *)fence; 274 } 275 276 #define V3D_READ(offset) readl(v3d->hub_regs + offset) 277 #define V3D_WRITE(offset, val) writel(val, v3d->hub_regs + offset) 278 279 #define V3D_BRIDGE_READ(offset) readl(v3d->bridge_regs + offset) 280 #define V3D_BRIDGE_WRITE(offset, val) writel(val, v3d->bridge_regs + offset) 281 282 #define V3D_GCA_READ(offset) readl(v3d->gca_regs + offset) 283 #define V3D_GCA_WRITE(offset, val) writel(val, v3d->gca_regs + offset) 284 285 #define V3D_SMS_IDLE 0x0 286 #define V3D_SMS_ISOLATING_FOR_RESET 0xa 287 #define V3D_SMS_RESETTING 0xb 288 #define V3D_SMS_ISOLATING_FOR_POWER_OFF 0xc 289 #define V3D_SMS_POWER_OFF_STATE 0xd 290 291 #define V3D_SMS_READ(offset) readl(v3d->sms_regs + (offset)) 292 #define V3D_SMS_WRITE(offset, val) writel(val, v3d->sms_regs + (offset)) 293 294 #define V3D_CORE_READ(core, offset) readl(v3d->core_regs[core] + offset) 295 #define V3D_CORE_WRITE(core, offset, val) writel(val, v3d->core_regs[core] + offset) 296 297 struct v3d_job { 298 struct drm_sched_job base; 299 300 struct kref refcount; 301 302 struct v3d_dev *v3d; 303 304 /* This is the array of BOs that were looked up at the start 305 * of submission. 306 */ 307 struct drm_gem_object **bo; 308 u32 bo_count; 309 310 /* v3d fence to be signaled by IRQ handler when the job is complete. */ 311 struct dma_fence *irq_fence; 312 313 /* scheduler fence for when the job is considered complete and 314 * the BO reservations can be released. 315 */ 316 struct dma_fence *done_fence; 317 318 /* Pointer to a performance monitor object if the user requested it, 319 * NULL otherwise. 320 */ 321 struct v3d_perfmon *perfmon; 322 323 /* File descriptor of the process that submitted the job that could be used 324 * to collect per-process information about the GPU. 325 */ 326 struct v3d_file_priv *file_priv; 327 328 /* Callback for the freeing of the job on refcount going to 0. */ 329 void (*free)(struct kref *ref); 330 }; 331 332 struct v3d_bin_job { 333 struct v3d_job base; 334 335 /* GPU virtual addresses of the start/end of the CL job. */ 336 u32 start, end; 337 338 u32 timedout_ctca, timedout_ctra; 339 340 /* Corresponding render job, for attaching our overflow memory. */ 341 struct v3d_render_job *render; 342 343 /* Submitted tile memory allocation start/size, tile state. */ 344 u32 qma, qms, qts; 345 }; 346 347 struct v3d_render_job { 348 struct v3d_job base; 349 350 /* GPU virtual addresses of the start/end of the CL job. */ 351 u32 start, end; 352 353 u32 timedout_ctca, timedout_ctra; 354 355 /* List of overflow BOs used in the job that need to be 356 * released once the job is complete. 357 */ 358 struct list_head unref_list; 359 }; 360 361 struct v3d_tfu_job { 362 struct v3d_job base; 363 364 struct drm_v3d_submit_tfu args; 365 }; 366 367 struct v3d_csd_job { 368 struct v3d_job base; 369 370 u32 timedout_batches; 371 372 struct drm_v3d_submit_csd args; 373 }; 374 375 enum v3d_cpu_job_type { 376 V3D_CPU_JOB_TYPE_INDIRECT_CSD = 1, 377 V3D_CPU_JOB_TYPE_TIMESTAMP_QUERY, 378 V3D_CPU_JOB_TYPE_RESET_TIMESTAMP_QUERY, 379 V3D_CPU_JOB_TYPE_COPY_TIMESTAMP_QUERY, 380 V3D_CPU_JOB_TYPE_RESET_PERFORMANCE_QUERY, 381 V3D_CPU_JOB_TYPE_COPY_PERFORMANCE_QUERY, 382 }; 383 384 struct v3d_timestamp_query { 385 /* Offset of this query in the timestamp BO for its value. */ 386 u32 offset; 387 388 /* Syncobj that indicates the timestamp availability */ 389 struct drm_syncobj *syncobj; 390 }; 391 392 struct v3d_performance_query { 393 /* Performance monitor IDs for this query */ 394 u32 *kperfmon_ids; 395 396 /* Syncobj that indicates the query availability */ 397 struct drm_syncobj *syncobj; 398 }; 399 400 struct v3d_indirect_csd_info { 401 /* Indirect CSD */ 402 struct v3d_csd_job *job; 403 404 /* Clean cache job associated to the Indirect CSD job */ 405 struct v3d_job *clean_job; 406 407 /* Offset within the BO where the workgroup counts are stored */ 408 u32 offset; 409 410 /* Workgroups size */ 411 u32 wg_size; 412 413 /* Indices of the uniforms with the workgroup dispatch counts 414 * in the uniform stream. 415 */ 416 u32 wg_uniform_offsets[3]; 417 418 /* Indirect BO */ 419 struct drm_gem_object *indirect; 420 421 /* Context of the Indirect CSD job */ 422 struct ww_acquire_ctx acquire_ctx; 423 }; 424 425 struct v3d_timestamp_query_info { 426 struct v3d_timestamp_query *queries; 427 428 u32 count; 429 }; 430 431 struct v3d_performance_query_info { 432 struct v3d_performance_query *queries; 433 434 /* Number of performance queries */ 435 u32 count; 436 437 /* Number of performance monitors related to that query pool */ 438 u32 nperfmons; 439 440 /* Number of performance counters related to that query pool */ 441 u32 ncounters; 442 }; 443 444 struct v3d_copy_query_results_info { 445 /* Define if should write to buffer using 64 or 32 bits */ 446 bool do_64bit; 447 448 /* Define if it can write to buffer even if the query is not available */ 449 bool do_partial; 450 451 /* Define if it should write availability bit to buffer */ 452 bool availability_bit; 453 454 /* Offset of the copy buffer in the BO */ 455 u32 offset; 456 457 /* Stride of the copy buffer in the BO */ 458 u32 stride; 459 }; 460 461 struct v3d_cpu_job { 462 struct v3d_job base; 463 464 enum v3d_cpu_job_type job_type; 465 466 struct v3d_indirect_csd_info indirect_csd; 467 468 struct v3d_timestamp_query_info timestamp_query; 469 470 struct v3d_copy_query_results_info copy; 471 472 struct v3d_performance_query_info performance_query; 473 }; 474 475 typedef void (*v3d_cpu_job_fn)(struct v3d_cpu_job *); 476 477 struct v3d_submit_outsync { 478 struct drm_syncobj *syncobj; 479 }; 480 481 struct v3d_submit_ext { 482 u32 flags; 483 u32 wait_stage; 484 485 u32 in_sync_count; 486 u64 in_syncs; 487 488 u32 out_sync_count; 489 struct v3d_submit_outsync *out_syncs; 490 }; 491 492 /** 493 * __wait_for - magic wait macro 494 * 495 * Macro to help avoid open coding check/wait/timeout patterns. Note that it's 496 * important that we check the condition again after having timed out, since the 497 * timeout could be due to preemption or similar and we've never had a chance to 498 * check the condition before the timeout. 499 */ 500 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \ 501 const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \ 502 long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \ 503 int ret__; \ 504 might_sleep(); \ 505 for (;;) { \ 506 const bool expired__ = ktime_after(ktime_get_raw(), end__); \ 507 OP; \ 508 /* Guarantee COND check prior to timeout */ \ 509 barrier(); \ 510 if (COND) { \ 511 ret__ = 0; \ 512 break; \ 513 } \ 514 if (expired__) { \ 515 ret__ = -ETIMEDOUT; \ 516 break; \ 517 } \ 518 usleep_range(wait__, wait__ * 2); \ 519 if (wait__ < (Wmax)) \ 520 wait__ <<= 1; \ 521 } \ 522 ret__; \ 523 }) 524 525 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \ 526 (Wmax)) 527 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000) 528 529 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) 530 { 531 /* nsecs_to_jiffies64() does not guard against overflow */ 532 if ((NSEC_PER_SEC % HZ) != 0 && 533 div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ) 534 return MAX_JIFFY_OFFSET; 535 536 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); 537 } 538 539 /* v3d_bo.c */ 540 struct drm_gem_object *v3d_create_object(struct drm_device *dev, size_t size); 541 void v3d_free_object(struct drm_gem_object *gem_obj); 542 struct v3d_bo *v3d_bo_create(struct drm_device *dev, struct drm_file *file_priv, 543 size_t size); 544 void v3d_get_bo_vaddr(struct v3d_bo *bo); 545 void v3d_put_bo_vaddr(struct v3d_bo *bo); 546 int v3d_create_bo_ioctl(struct drm_device *dev, void *data, 547 struct drm_file *file_priv); 548 int v3d_mmap_bo_ioctl(struct drm_device *dev, void *data, 549 struct drm_file *file_priv); 550 int v3d_get_bo_offset_ioctl(struct drm_device *dev, void *data, 551 struct drm_file *file_priv); 552 int v3d_wait_bo_ioctl(struct drm_device *dev, void *data, 553 struct drm_file *file_priv); 554 struct drm_gem_object *v3d_prime_import_sg_table(struct drm_device *dev, 555 struct dma_buf_attachment *attach, 556 struct sg_table *sgt); 557 558 /* v3d_debugfs.c */ 559 void v3d_debugfs_init(struct drm_minor *minor); 560 561 /* v3d_drv.c */ 562 void v3d_get_stats(const struct v3d_stats *stats, u64 timestamp, 563 u64 *active_runtime, u64 *jobs_completed); 564 565 /* v3d_fence.c */ 566 extern const struct dma_fence_ops v3d_fence_ops; 567 struct dma_fence *v3d_fence_create(struct v3d_dev *v3d, enum v3d_queue q); 568 569 /* v3d_gem.c */ 570 int v3d_gem_init(struct drm_device *dev); 571 void v3d_gem_destroy(struct drm_device *dev); 572 void v3d_reset_sms(struct v3d_dev *v3d); 573 void v3d_reset(struct v3d_dev *v3d); 574 void v3d_invalidate_caches(struct v3d_dev *v3d); 575 void v3d_clean_caches(struct v3d_dev *v3d); 576 577 /* v3d_gemfs.c */ 578 extern bool super_pages; 579 void v3d_gemfs_init(struct v3d_dev *v3d); 580 void v3d_gemfs_fini(struct v3d_dev *v3d); 581 582 /* v3d_submit.c */ 583 void v3d_job_cleanup(struct v3d_job *job); 584 void v3d_job_put(struct v3d_job *job); 585 int v3d_submit_cl_ioctl(struct drm_device *dev, void *data, 586 struct drm_file *file_priv); 587 int v3d_submit_tfu_ioctl(struct drm_device *dev, void *data, 588 struct drm_file *file_priv); 589 int v3d_submit_csd_ioctl(struct drm_device *dev, void *data, 590 struct drm_file *file_priv); 591 int v3d_submit_cpu_ioctl(struct drm_device *dev, void *data, 592 struct drm_file *file_priv); 593 594 /* v3d_irq.c */ 595 int v3d_irq_init(struct v3d_dev *v3d); 596 void v3d_irq_enable(struct v3d_dev *v3d); 597 void v3d_irq_disable(struct v3d_dev *v3d); 598 void v3d_irq_reset(struct v3d_dev *v3d); 599 600 /* v3d_mmu.c */ 601 int v3d_mmu_flush_all(struct v3d_dev *v3d); 602 int v3d_mmu_set_page_table(struct v3d_dev *v3d); 603 void v3d_mmu_insert_ptes(struct v3d_bo *bo); 604 void v3d_mmu_remove_ptes(struct v3d_bo *bo); 605 606 /* v3d_sched.c */ 607 void v3d_timestamp_query_info_free(struct v3d_timestamp_query_info *query_info, 608 unsigned int count); 609 void v3d_performance_query_info_free(struct v3d_performance_query_info *query_info, 610 unsigned int count); 611 void v3d_job_update_stats(struct v3d_job *job, enum v3d_queue q); 612 int v3d_sched_init(struct v3d_dev *v3d); 613 void v3d_sched_fini(struct v3d_dev *v3d); 614 615 /* v3d_perfmon.c */ 616 void v3d_perfmon_init(struct v3d_dev *v3d); 617 void v3d_perfmon_get(struct v3d_perfmon *perfmon); 618 void v3d_perfmon_put(struct v3d_perfmon *perfmon); 619 void v3d_perfmon_start(struct v3d_dev *v3d, struct v3d_perfmon *perfmon); 620 void v3d_perfmon_stop(struct v3d_dev *v3d, struct v3d_perfmon *perfmon, 621 bool capture); 622 struct v3d_perfmon *v3d_perfmon_find(struct v3d_file_priv *v3d_priv, int id); 623 void v3d_perfmon_open_file(struct v3d_file_priv *v3d_priv); 624 void v3d_perfmon_close_file(struct v3d_file_priv *v3d_priv); 625 int v3d_perfmon_create_ioctl(struct drm_device *dev, void *data, 626 struct drm_file *file_priv); 627 int v3d_perfmon_destroy_ioctl(struct drm_device *dev, void *data, 628 struct drm_file *file_priv); 629 int v3d_perfmon_get_values_ioctl(struct drm_device *dev, void *data, 630 struct drm_file *file_priv); 631 int v3d_perfmon_get_counter_ioctl(struct drm_device *dev, void *data, 632 struct drm_file *file_priv); 633 int v3d_perfmon_set_global_ioctl(struct drm_device *dev, void *data, 634 struct drm_file *file_priv); 635 636 /* v3d_sysfs.c */ 637 int v3d_sysfs_init(struct device *dev); 638 void v3d_sysfs_destroy(struct device *dev); 639