1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2014-2018 Broadcom */ 3 4 /** 5 * DOC: Broadcom V3D Graphics Driver 6 * 7 * This driver supports the Broadcom V3D 3.3 and 4.1 OpenGL ES GPUs. 8 * For V3D 2.x support, see the VC4 driver. 9 * 10 * The V3D GPU includes a tiled render (composed of a bin and render 11 * pipelines), the TFU (texture formatting unit), and the CSD (compute 12 * shader dispatch). 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/device.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/io.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/of_platform.h> 22 #include <linux/platform_device.h> 23 #include <linux/sched/clock.h> 24 #include <linux/reset.h> 25 26 #include <drm/drm_drv.h> 27 #include <drm/drm_managed.h> 28 #include <uapi/drm/v3d_drm.h> 29 30 #include "v3d_drv.h" 31 #include "v3d_regs.h" 32 33 #define DRIVER_NAME "v3d" 34 #define DRIVER_DESC "Broadcom V3D graphics" 35 #define DRIVER_MAJOR 1 36 #define DRIVER_MINOR 0 37 #define DRIVER_PATCHLEVEL 0 38 39 /* Only expose the `super_pages` modparam if THP is enabled. */ 40 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 41 bool super_pages = true; 42 module_param_named(super_pages, super_pages, bool, 0400); 43 MODULE_PARM_DESC(super_pages, "Enable/Disable Super Pages support."); 44 #endif 45 46 static int v3d_get_param_ioctl(struct drm_device *dev, void *data, 47 struct drm_file *file_priv) 48 { 49 struct v3d_dev *v3d = to_v3d_dev(dev); 50 struct drm_v3d_get_param *args = data; 51 static const u32 reg_map[] = { 52 [DRM_V3D_PARAM_V3D_UIFCFG] = V3D_HUB_UIFCFG, 53 [DRM_V3D_PARAM_V3D_HUB_IDENT1] = V3D_HUB_IDENT1, 54 [DRM_V3D_PARAM_V3D_HUB_IDENT2] = V3D_HUB_IDENT2, 55 [DRM_V3D_PARAM_V3D_HUB_IDENT3] = V3D_HUB_IDENT3, 56 [DRM_V3D_PARAM_V3D_CORE0_IDENT0] = V3D_CTL_IDENT0, 57 [DRM_V3D_PARAM_V3D_CORE0_IDENT1] = V3D_CTL_IDENT1, 58 [DRM_V3D_PARAM_V3D_CORE0_IDENT2] = V3D_CTL_IDENT2, 59 }; 60 61 if (args->pad != 0) 62 return -EINVAL; 63 64 /* Note that DRM_V3D_PARAM_V3D_CORE0_IDENT0 is 0, so we need 65 * to explicitly allow it in the "the register in our 66 * parameter map" check. 67 */ 68 if (args->param < ARRAY_SIZE(reg_map) && 69 (reg_map[args->param] || 70 args->param == DRM_V3D_PARAM_V3D_CORE0_IDENT0)) { 71 u32 offset = reg_map[args->param]; 72 73 if (args->value != 0) 74 return -EINVAL; 75 76 if (args->param >= DRM_V3D_PARAM_V3D_CORE0_IDENT0 && 77 args->param <= DRM_V3D_PARAM_V3D_CORE0_IDENT2) { 78 args->value = V3D_CORE_READ(0, offset); 79 } else { 80 args->value = V3D_READ(offset); 81 } 82 return 0; 83 } 84 85 switch (args->param) { 86 case DRM_V3D_PARAM_SUPPORTS_TFU: 87 args->value = 1; 88 return 0; 89 case DRM_V3D_PARAM_SUPPORTS_CSD: 90 args->value = v3d_has_csd(v3d); 91 return 0; 92 case DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH: 93 args->value = 1; 94 return 0; 95 case DRM_V3D_PARAM_SUPPORTS_PERFMON: 96 args->value = (v3d->ver >= V3D_GEN_41); 97 return 0; 98 case DRM_V3D_PARAM_SUPPORTS_MULTISYNC_EXT: 99 args->value = 1; 100 return 0; 101 case DRM_V3D_PARAM_SUPPORTS_CPU_QUEUE: 102 args->value = 1; 103 return 0; 104 case DRM_V3D_PARAM_MAX_PERF_COUNTERS: 105 args->value = v3d->perfmon_info.max_counters; 106 return 0; 107 case DRM_V3D_PARAM_SUPPORTS_SUPER_PAGES: 108 args->value = !!v3d->gemfs; 109 return 0; 110 default: 111 DRM_DEBUG("Unknown parameter %d\n", args->param); 112 return -EINVAL; 113 } 114 } 115 116 static int 117 v3d_open(struct drm_device *dev, struct drm_file *file) 118 { 119 struct v3d_dev *v3d = to_v3d_dev(dev); 120 struct v3d_file_priv *v3d_priv; 121 struct drm_gpu_scheduler *sched; 122 int i; 123 124 v3d_priv = kzalloc(sizeof(*v3d_priv), GFP_KERNEL); 125 if (!v3d_priv) 126 return -ENOMEM; 127 128 v3d_priv->v3d = v3d; 129 130 for (i = 0; i < V3D_MAX_QUEUES; i++) { 131 sched = &v3d->queue[i].sched; 132 drm_sched_entity_init(&v3d_priv->sched_entity[i], 133 DRM_SCHED_PRIORITY_NORMAL, &sched, 134 1, NULL); 135 136 memset(&v3d_priv->stats[i], 0, sizeof(v3d_priv->stats[i])); 137 seqcount_init(&v3d_priv->stats[i].lock); 138 } 139 140 v3d_perfmon_open_file(v3d_priv); 141 file->driver_priv = v3d_priv; 142 143 return 0; 144 } 145 146 static void 147 v3d_postclose(struct drm_device *dev, struct drm_file *file) 148 { 149 struct v3d_file_priv *v3d_priv = file->driver_priv; 150 enum v3d_queue q; 151 152 for (q = 0; q < V3D_MAX_QUEUES; q++) 153 drm_sched_entity_destroy(&v3d_priv->sched_entity[q]); 154 155 v3d_perfmon_close_file(v3d_priv); 156 kfree(v3d_priv); 157 } 158 159 void v3d_get_stats(const struct v3d_stats *stats, u64 timestamp, 160 u64 *active_runtime, u64 *jobs_completed) 161 { 162 unsigned int seq; 163 164 do { 165 seq = read_seqcount_begin(&stats->lock); 166 *active_runtime = stats->enabled_ns; 167 if (stats->start_ns) 168 *active_runtime += timestamp - stats->start_ns; 169 *jobs_completed = stats->jobs_completed; 170 } while (read_seqcount_retry(&stats->lock, seq)); 171 } 172 173 static void v3d_show_fdinfo(struct drm_printer *p, struct drm_file *file) 174 { 175 struct v3d_file_priv *file_priv = file->driver_priv; 176 u64 timestamp = local_clock(); 177 enum v3d_queue queue; 178 179 for (queue = 0; queue < V3D_MAX_QUEUES; queue++) { 180 struct v3d_stats *stats = &file_priv->stats[queue]; 181 u64 active_runtime, jobs_completed; 182 183 v3d_get_stats(stats, timestamp, &active_runtime, &jobs_completed); 184 185 /* Note that, in case of a GPU reset, the time spent during an 186 * attempt of executing the job is not computed in the runtime. 187 */ 188 drm_printf(p, "drm-engine-%s: \t%llu ns\n", 189 v3d_queue_to_string(queue), active_runtime); 190 191 /* Note that we only count jobs that completed. Therefore, jobs 192 * that were resubmitted due to a GPU reset are not computed. 193 */ 194 drm_printf(p, "v3d-jobs-%s: \t%llu jobs\n", 195 v3d_queue_to_string(queue), jobs_completed); 196 } 197 198 drm_show_memory_stats(p, file); 199 } 200 201 static const struct file_operations v3d_drm_fops = { 202 .owner = THIS_MODULE, 203 DRM_GEM_FOPS, 204 .show_fdinfo = drm_show_fdinfo, 205 }; 206 207 /* DRM_AUTH is required on SUBMIT_CL for now, while we don't have GMP 208 * protection between clients. Note that render nodes would be 209 * able to submit CLs that could access BOs from clients authenticated 210 * with the master node. The TFU doesn't use the GMP, so it would 211 * need to stay DRM_AUTH until we do buffer size/offset validation. 212 */ 213 static const struct drm_ioctl_desc v3d_drm_ioctls[] = { 214 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CL, v3d_submit_cl_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 215 DRM_IOCTL_DEF_DRV(V3D_WAIT_BO, v3d_wait_bo_ioctl, DRM_RENDER_ALLOW), 216 DRM_IOCTL_DEF_DRV(V3D_CREATE_BO, v3d_create_bo_ioctl, DRM_RENDER_ALLOW), 217 DRM_IOCTL_DEF_DRV(V3D_MMAP_BO, v3d_mmap_bo_ioctl, DRM_RENDER_ALLOW), 218 DRM_IOCTL_DEF_DRV(V3D_GET_PARAM, v3d_get_param_ioctl, DRM_RENDER_ALLOW), 219 DRM_IOCTL_DEF_DRV(V3D_GET_BO_OFFSET, v3d_get_bo_offset_ioctl, DRM_RENDER_ALLOW), 220 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_TFU, v3d_submit_tfu_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 221 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CSD, v3d_submit_csd_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 222 DRM_IOCTL_DEF_DRV(V3D_PERFMON_CREATE, v3d_perfmon_create_ioctl, DRM_RENDER_ALLOW), 223 DRM_IOCTL_DEF_DRV(V3D_PERFMON_DESTROY, v3d_perfmon_destroy_ioctl, DRM_RENDER_ALLOW), 224 DRM_IOCTL_DEF_DRV(V3D_PERFMON_GET_VALUES, v3d_perfmon_get_values_ioctl, DRM_RENDER_ALLOW), 225 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CPU, v3d_submit_cpu_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 226 DRM_IOCTL_DEF_DRV(V3D_PERFMON_GET_COUNTER, v3d_perfmon_get_counter_ioctl, DRM_RENDER_ALLOW), 227 DRM_IOCTL_DEF_DRV(V3D_PERFMON_SET_GLOBAL, v3d_perfmon_set_global_ioctl, DRM_RENDER_ALLOW), 228 }; 229 230 static const struct drm_driver v3d_drm_driver = { 231 .driver_features = (DRIVER_GEM | 232 DRIVER_RENDER | 233 DRIVER_SYNCOBJ), 234 235 .open = v3d_open, 236 .postclose = v3d_postclose, 237 238 #if defined(CONFIG_DEBUG_FS) 239 .debugfs_init = v3d_debugfs_init, 240 #endif 241 242 .gem_create_object = v3d_create_object, 243 .gem_prime_import_sg_table = v3d_prime_import_sg_table, 244 245 .ioctls = v3d_drm_ioctls, 246 .num_ioctls = ARRAY_SIZE(v3d_drm_ioctls), 247 .fops = &v3d_drm_fops, 248 .show_fdinfo = v3d_show_fdinfo, 249 250 .name = DRIVER_NAME, 251 .desc = DRIVER_DESC, 252 .major = DRIVER_MAJOR, 253 .minor = DRIVER_MINOR, 254 .patchlevel = DRIVER_PATCHLEVEL, 255 }; 256 257 static const struct of_device_id v3d_of_match[] = { 258 { .compatible = "brcm,2711-v3d", .data = (void *)V3D_GEN_42 }, 259 { .compatible = "brcm,2712-v3d", .data = (void *)V3D_GEN_71 }, 260 { .compatible = "brcm,7268-v3d", .data = (void *)V3D_GEN_33 }, 261 { .compatible = "brcm,7278-v3d", .data = (void *)V3D_GEN_41 }, 262 {}, 263 }; 264 MODULE_DEVICE_TABLE(of, v3d_of_match); 265 266 static void 267 v3d_idle_sms(struct v3d_dev *v3d) 268 { 269 if (v3d->ver < V3D_GEN_71) 270 return; 271 272 V3D_SMS_WRITE(V3D_SMS_TEE_CS, V3D_SMS_CLEAR_POWER_OFF); 273 274 if (wait_for((V3D_GET_FIELD(V3D_SMS_READ(V3D_SMS_TEE_CS), 275 V3D_SMS_STATE) == V3D_SMS_IDLE), 100)) { 276 DRM_ERROR("Failed to power up SMS\n"); 277 } 278 279 v3d_reset_sms(v3d); 280 } 281 282 static void 283 v3d_power_off_sms(struct v3d_dev *v3d) 284 { 285 if (v3d->ver < V3D_GEN_71) 286 return; 287 288 V3D_SMS_WRITE(V3D_SMS_TEE_CS, V3D_SMS_POWER_OFF); 289 290 if (wait_for((V3D_GET_FIELD(V3D_SMS_READ(V3D_SMS_TEE_CS), 291 V3D_SMS_STATE) == V3D_SMS_POWER_OFF_STATE), 100)) { 292 DRM_ERROR("Failed to power off SMS\n"); 293 } 294 } 295 296 static int 297 map_regs(struct v3d_dev *v3d, void __iomem **regs, const char *name) 298 { 299 *regs = devm_platform_ioremap_resource_byname(v3d_to_pdev(v3d), name); 300 return PTR_ERR_OR_ZERO(*regs); 301 } 302 303 static int v3d_platform_drm_probe(struct platform_device *pdev) 304 { 305 struct device *dev = &pdev->dev; 306 struct drm_device *drm; 307 struct v3d_dev *v3d; 308 enum v3d_gen gen; 309 int ret; 310 u32 mmu_debug; 311 u32 ident1, ident3; 312 u64 mask; 313 314 v3d = devm_drm_dev_alloc(dev, &v3d_drm_driver, struct v3d_dev, drm); 315 if (IS_ERR(v3d)) 316 return PTR_ERR(v3d); 317 318 drm = &v3d->drm; 319 320 platform_set_drvdata(pdev, drm); 321 322 gen = (uintptr_t)of_device_get_match_data(dev); 323 v3d->ver = gen; 324 325 ret = map_regs(v3d, &v3d->hub_regs, "hub"); 326 if (ret) 327 return ret; 328 329 ret = map_regs(v3d, &v3d->core_regs[0], "core0"); 330 if (ret) 331 return ret; 332 333 if (v3d->ver >= V3D_GEN_71) { 334 ret = map_regs(v3d, &v3d->sms_regs, "sms"); 335 if (ret) 336 return ret; 337 } 338 339 v3d->clk = devm_clk_get_optional(dev, NULL); 340 if (IS_ERR(v3d->clk)) 341 return dev_err_probe(dev, PTR_ERR(v3d->clk), "Failed to get V3D clock\n"); 342 343 ret = clk_prepare_enable(v3d->clk); 344 if (ret) { 345 dev_err(&pdev->dev, "Couldn't enable the V3D clock\n"); 346 return ret; 347 } 348 349 v3d_idle_sms(v3d); 350 351 mmu_debug = V3D_READ(V3D_MMU_DEBUG_INFO); 352 mask = DMA_BIT_MASK(30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_PA_WIDTH)); 353 ret = dma_set_mask_and_coherent(dev, mask); 354 if (ret) 355 goto clk_disable; 356 357 v3d->va_width = 30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_VA_WIDTH); 358 359 ident1 = V3D_READ(V3D_HUB_IDENT1); 360 v3d->ver = (V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER) * 10 + 361 V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV)); 362 /* Make sure that the V3D tech version retrieved from the HW is equal 363 * to the one advertised by the device tree. 364 */ 365 WARN_ON(v3d->ver != gen); 366 367 v3d->cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES); 368 WARN_ON(v3d->cores > 1); /* multicore not yet implemented */ 369 370 ident3 = V3D_READ(V3D_HUB_IDENT3); 371 v3d->rev = V3D_GET_FIELD(ident3, V3D_HUB_IDENT3_IPREV); 372 373 v3d_perfmon_init(v3d); 374 375 v3d->reset = devm_reset_control_get_exclusive(dev, NULL); 376 if (IS_ERR(v3d->reset)) { 377 ret = PTR_ERR(v3d->reset); 378 379 if (ret == -EPROBE_DEFER) 380 goto clk_disable; 381 382 v3d->reset = NULL; 383 ret = map_regs(v3d, &v3d->bridge_regs, "bridge"); 384 if (ret) { 385 dev_err(dev, 386 "Failed to get reset control or bridge regs\n"); 387 goto clk_disable; 388 } 389 } 390 391 if (v3d->ver < V3D_GEN_41) { 392 ret = map_regs(v3d, &v3d->gca_regs, "gca"); 393 if (ret) 394 goto clk_disable; 395 } 396 397 v3d->mmu_scratch = dma_alloc_wc(dev, 4096, &v3d->mmu_scratch_paddr, 398 GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO); 399 if (!v3d->mmu_scratch) { 400 dev_err(dev, "Failed to allocate MMU scratch page\n"); 401 ret = -ENOMEM; 402 goto clk_disable; 403 } 404 405 ret = v3d_gem_init(drm); 406 if (ret) 407 goto dma_free; 408 409 ret = v3d_irq_init(v3d); 410 if (ret) 411 goto gem_destroy; 412 413 ret = drm_dev_register(drm, 0); 414 if (ret) 415 goto irq_disable; 416 417 ret = v3d_sysfs_init(dev); 418 if (ret) 419 goto drm_unregister; 420 421 return 0; 422 423 drm_unregister: 424 drm_dev_unregister(drm); 425 irq_disable: 426 v3d_irq_disable(v3d); 427 gem_destroy: 428 v3d_gem_destroy(drm); 429 dma_free: 430 dma_free_wc(dev, 4096, v3d->mmu_scratch, v3d->mmu_scratch_paddr); 431 clk_disable: 432 clk_disable_unprepare(v3d->clk); 433 return ret; 434 } 435 436 static void v3d_platform_drm_remove(struct platform_device *pdev) 437 { 438 struct drm_device *drm = platform_get_drvdata(pdev); 439 struct v3d_dev *v3d = to_v3d_dev(drm); 440 struct device *dev = &pdev->dev; 441 442 v3d_sysfs_destroy(dev); 443 444 drm_dev_unregister(drm); 445 446 v3d_gem_destroy(drm); 447 448 dma_free_wc(v3d->drm.dev, 4096, v3d->mmu_scratch, 449 v3d->mmu_scratch_paddr); 450 451 v3d_power_off_sms(v3d); 452 453 clk_disable_unprepare(v3d->clk); 454 } 455 456 static struct platform_driver v3d_platform_driver = { 457 .probe = v3d_platform_drm_probe, 458 .remove = v3d_platform_drm_remove, 459 .driver = { 460 .name = "v3d", 461 .of_match_table = v3d_of_match, 462 }, 463 }; 464 465 module_platform_driver(v3d_platform_driver); 466 467 MODULE_ALIAS("platform:v3d-drm"); 468 MODULE_DESCRIPTION("Broadcom V3D DRM Driver"); 469 MODULE_AUTHOR("Eric Anholt <eric@anholt.net>"); 470 MODULE_LICENSE("GPL v2"); 471