1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2014-2018 Broadcom */ 3 4 /** 5 * DOC: Broadcom V3D Graphics Driver 6 * 7 * This driver supports the Broadcom V3D 3.3 and 4.1 OpenGL ES GPUs. 8 * For V3D 2.x support, see the VC4 driver. 9 * 10 * The V3D GPU includes a tiled render (composed of a bin and render 11 * pipelines), the TFU (texture formatting unit), and the CSD (compute 12 * shader dispatch). 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/device.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/io.h> 19 #include <linux/module.h> 20 #include <linux/of_platform.h> 21 #include <linux/platform_device.h> 22 #include <linux/sched/clock.h> 23 #include <linux/reset.h> 24 25 #include <drm/drm_drv.h> 26 #include <drm/drm_managed.h> 27 #include <uapi/drm/v3d_drm.h> 28 29 #include "v3d_drv.h" 30 #include "v3d_regs.h" 31 32 #define DRIVER_NAME "v3d" 33 #define DRIVER_DESC "Broadcom V3D graphics" 34 #define DRIVER_MAJOR 1 35 #define DRIVER_MINOR 0 36 #define DRIVER_PATCHLEVEL 0 37 38 /* Only expose the `super_pages` modparam if THP is enabled. */ 39 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 40 bool super_pages = true; 41 module_param_named(super_pages, super_pages, bool, 0400); 42 MODULE_PARM_DESC(super_pages, "Enable/Disable Super Pages support."); 43 #endif 44 45 static int v3d_get_param_ioctl(struct drm_device *dev, void *data, 46 struct drm_file *file_priv) 47 { 48 struct v3d_dev *v3d = to_v3d_dev(dev); 49 struct drm_v3d_get_param *args = data; 50 static const u32 reg_map[] = { 51 [DRM_V3D_PARAM_V3D_UIFCFG] = V3D_HUB_UIFCFG, 52 [DRM_V3D_PARAM_V3D_HUB_IDENT1] = V3D_HUB_IDENT1, 53 [DRM_V3D_PARAM_V3D_HUB_IDENT2] = V3D_HUB_IDENT2, 54 [DRM_V3D_PARAM_V3D_HUB_IDENT3] = V3D_HUB_IDENT3, 55 [DRM_V3D_PARAM_V3D_CORE0_IDENT0] = V3D_CTL_IDENT0, 56 [DRM_V3D_PARAM_V3D_CORE0_IDENT1] = V3D_CTL_IDENT1, 57 [DRM_V3D_PARAM_V3D_CORE0_IDENT2] = V3D_CTL_IDENT2, 58 }; 59 60 if (args->pad != 0) 61 return -EINVAL; 62 63 /* Note that DRM_V3D_PARAM_V3D_CORE0_IDENT0 is 0, so we need 64 * to explicitly allow it in the "the register in our 65 * parameter map" check. 66 */ 67 if (args->param < ARRAY_SIZE(reg_map) && 68 (reg_map[args->param] || 69 args->param == DRM_V3D_PARAM_V3D_CORE0_IDENT0)) { 70 u32 offset = reg_map[args->param]; 71 72 if (args->value != 0) 73 return -EINVAL; 74 75 if (args->param >= DRM_V3D_PARAM_V3D_CORE0_IDENT0 && 76 args->param <= DRM_V3D_PARAM_V3D_CORE0_IDENT2) { 77 args->value = V3D_CORE_READ(0, offset); 78 } else { 79 args->value = V3D_READ(offset); 80 } 81 return 0; 82 } 83 84 switch (args->param) { 85 case DRM_V3D_PARAM_SUPPORTS_TFU: 86 args->value = 1; 87 return 0; 88 case DRM_V3D_PARAM_SUPPORTS_CSD: 89 args->value = v3d_has_csd(v3d); 90 return 0; 91 case DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH: 92 args->value = 1; 93 return 0; 94 case DRM_V3D_PARAM_SUPPORTS_PERFMON: 95 args->value = (v3d->ver >= 40); 96 return 0; 97 case DRM_V3D_PARAM_SUPPORTS_MULTISYNC_EXT: 98 args->value = 1; 99 return 0; 100 case DRM_V3D_PARAM_SUPPORTS_CPU_QUEUE: 101 args->value = 1; 102 return 0; 103 case DRM_V3D_PARAM_MAX_PERF_COUNTERS: 104 args->value = v3d->perfmon_info.max_counters; 105 return 0; 106 case DRM_V3D_PARAM_SUPPORTS_SUPER_PAGES: 107 args->value = !!v3d->gemfs; 108 return 0; 109 default: 110 DRM_DEBUG("Unknown parameter %d\n", args->param); 111 return -EINVAL; 112 } 113 } 114 115 static int 116 v3d_open(struct drm_device *dev, struct drm_file *file) 117 { 118 struct v3d_dev *v3d = to_v3d_dev(dev); 119 struct v3d_file_priv *v3d_priv; 120 struct drm_gpu_scheduler *sched; 121 int i; 122 123 v3d_priv = kzalloc(sizeof(*v3d_priv), GFP_KERNEL); 124 if (!v3d_priv) 125 return -ENOMEM; 126 127 v3d_priv->v3d = v3d; 128 129 for (i = 0; i < V3D_MAX_QUEUES; i++) { 130 sched = &v3d->queue[i].sched; 131 drm_sched_entity_init(&v3d_priv->sched_entity[i], 132 DRM_SCHED_PRIORITY_NORMAL, &sched, 133 1, NULL); 134 135 memset(&v3d_priv->stats[i], 0, sizeof(v3d_priv->stats[i])); 136 seqcount_init(&v3d_priv->stats[i].lock); 137 } 138 139 v3d_perfmon_open_file(v3d_priv); 140 file->driver_priv = v3d_priv; 141 142 return 0; 143 } 144 145 static void 146 v3d_postclose(struct drm_device *dev, struct drm_file *file) 147 { 148 struct v3d_file_priv *v3d_priv = file->driver_priv; 149 enum v3d_queue q; 150 151 for (q = 0; q < V3D_MAX_QUEUES; q++) 152 drm_sched_entity_destroy(&v3d_priv->sched_entity[q]); 153 154 v3d_perfmon_close_file(v3d_priv); 155 kfree(v3d_priv); 156 } 157 158 void v3d_get_stats(const struct v3d_stats *stats, u64 timestamp, 159 u64 *active_runtime, u64 *jobs_completed) 160 { 161 unsigned int seq; 162 163 do { 164 seq = read_seqcount_begin(&stats->lock); 165 *active_runtime = stats->enabled_ns; 166 if (stats->start_ns) 167 *active_runtime += timestamp - stats->start_ns; 168 *jobs_completed = stats->jobs_completed; 169 } while (read_seqcount_retry(&stats->lock, seq)); 170 } 171 172 static void v3d_show_fdinfo(struct drm_printer *p, struct drm_file *file) 173 { 174 struct v3d_file_priv *file_priv = file->driver_priv; 175 u64 timestamp = local_clock(); 176 enum v3d_queue queue; 177 178 for (queue = 0; queue < V3D_MAX_QUEUES; queue++) { 179 struct v3d_stats *stats = &file_priv->stats[queue]; 180 u64 active_runtime, jobs_completed; 181 182 v3d_get_stats(stats, timestamp, &active_runtime, &jobs_completed); 183 184 /* Note that, in case of a GPU reset, the time spent during an 185 * attempt of executing the job is not computed in the runtime. 186 */ 187 drm_printf(p, "drm-engine-%s: \t%llu ns\n", 188 v3d_queue_to_string(queue), active_runtime); 189 190 /* Note that we only count jobs that completed. Therefore, jobs 191 * that were resubmitted due to a GPU reset are not computed. 192 */ 193 drm_printf(p, "v3d-jobs-%s: \t%llu jobs\n", 194 v3d_queue_to_string(queue), jobs_completed); 195 } 196 197 drm_show_memory_stats(p, file); 198 } 199 200 static const struct file_operations v3d_drm_fops = { 201 .owner = THIS_MODULE, 202 DRM_GEM_FOPS, 203 .show_fdinfo = drm_show_fdinfo, 204 }; 205 206 /* DRM_AUTH is required on SUBMIT_CL for now, while we don't have GMP 207 * protection between clients. Note that render nodes would be 208 * able to submit CLs that could access BOs from clients authenticated 209 * with the master node. The TFU doesn't use the GMP, so it would 210 * need to stay DRM_AUTH until we do buffer size/offset validation. 211 */ 212 static const struct drm_ioctl_desc v3d_drm_ioctls[] = { 213 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CL, v3d_submit_cl_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 214 DRM_IOCTL_DEF_DRV(V3D_WAIT_BO, v3d_wait_bo_ioctl, DRM_RENDER_ALLOW), 215 DRM_IOCTL_DEF_DRV(V3D_CREATE_BO, v3d_create_bo_ioctl, DRM_RENDER_ALLOW), 216 DRM_IOCTL_DEF_DRV(V3D_MMAP_BO, v3d_mmap_bo_ioctl, DRM_RENDER_ALLOW), 217 DRM_IOCTL_DEF_DRV(V3D_GET_PARAM, v3d_get_param_ioctl, DRM_RENDER_ALLOW), 218 DRM_IOCTL_DEF_DRV(V3D_GET_BO_OFFSET, v3d_get_bo_offset_ioctl, DRM_RENDER_ALLOW), 219 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_TFU, v3d_submit_tfu_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 220 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CSD, v3d_submit_csd_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 221 DRM_IOCTL_DEF_DRV(V3D_PERFMON_CREATE, v3d_perfmon_create_ioctl, DRM_RENDER_ALLOW), 222 DRM_IOCTL_DEF_DRV(V3D_PERFMON_DESTROY, v3d_perfmon_destroy_ioctl, DRM_RENDER_ALLOW), 223 DRM_IOCTL_DEF_DRV(V3D_PERFMON_GET_VALUES, v3d_perfmon_get_values_ioctl, DRM_RENDER_ALLOW), 224 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CPU, v3d_submit_cpu_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 225 DRM_IOCTL_DEF_DRV(V3D_PERFMON_GET_COUNTER, v3d_perfmon_get_counter_ioctl, DRM_RENDER_ALLOW), 226 DRM_IOCTL_DEF_DRV(V3D_PERFMON_SET_GLOBAL, v3d_perfmon_set_global_ioctl, DRM_RENDER_ALLOW), 227 }; 228 229 static const struct drm_driver v3d_drm_driver = { 230 .driver_features = (DRIVER_GEM | 231 DRIVER_RENDER | 232 DRIVER_SYNCOBJ), 233 234 .open = v3d_open, 235 .postclose = v3d_postclose, 236 237 #if defined(CONFIG_DEBUG_FS) 238 .debugfs_init = v3d_debugfs_init, 239 #endif 240 241 .gem_create_object = v3d_create_object, 242 .gem_prime_import_sg_table = v3d_prime_import_sg_table, 243 244 .ioctls = v3d_drm_ioctls, 245 .num_ioctls = ARRAY_SIZE(v3d_drm_ioctls), 246 .fops = &v3d_drm_fops, 247 .show_fdinfo = v3d_show_fdinfo, 248 249 .name = DRIVER_NAME, 250 .desc = DRIVER_DESC, 251 .major = DRIVER_MAJOR, 252 .minor = DRIVER_MINOR, 253 .patchlevel = DRIVER_PATCHLEVEL, 254 }; 255 256 static const struct of_device_id v3d_of_match[] = { 257 { .compatible = "brcm,2711-v3d" }, 258 { .compatible = "brcm,2712-v3d" }, 259 { .compatible = "brcm,7268-v3d" }, 260 { .compatible = "brcm,7278-v3d" }, 261 {}, 262 }; 263 MODULE_DEVICE_TABLE(of, v3d_of_match); 264 265 static int 266 map_regs(struct v3d_dev *v3d, void __iomem **regs, const char *name) 267 { 268 *regs = devm_platform_ioremap_resource_byname(v3d_to_pdev(v3d), name); 269 return PTR_ERR_OR_ZERO(*regs); 270 } 271 272 static int v3d_platform_drm_probe(struct platform_device *pdev) 273 { 274 struct device *dev = &pdev->dev; 275 struct drm_device *drm; 276 struct v3d_dev *v3d; 277 int ret; 278 u32 mmu_debug; 279 u32 ident1, ident3; 280 u64 mask; 281 282 v3d = devm_drm_dev_alloc(dev, &v3d_drm_driver, struct v3d_dev, drm); 283 if (IS_ERR(v3d)) 284 return PTR_ERR(v3d); 285 286 drm = &v3d->drm; 287 288 platform_set_drvdata(pdev, drm); 289 290 ret = map_regs(v3d, &v3d->hub_regs, "hub"); 291 if (ret) 292 return ret; 293 294 ret = map_regs(v3d, &v3d->core_regs[0], "core0"); 295 if (ret) 296 return ret; 297 298 mmu_debug = V3D_READ(V3D_MMU_DEBUG_INFO); 299 mask = DMA_BIT_MASK(30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_PA_WIDTH)); 300 ret = dma_set_mask_and_coherent(dev, mask); 301 if (ret) 302 return ret; 303 304 v3d->va_width = 30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_VA_WIDTH); 305 306 ident1 = V3D_READ(V3D_HUB_IDENT1); 307 v3d->ver = (V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER) * 10 + 308 V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV)); 309 v3d->cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES); 310 WARN_ON(v3d->cores > 1); /* multicore not yet implemented */ 311 312 ident3 = V3D_READ(V3D_HUB_IDENT3); 313 v3d->rev = V3D_GET_FIELD(ident3, V3D_HUB_IDENT3_IPREV); 314 315 v3d_perfmon_init(v3d); 316 317 v3d->reset = devm_reset_control_get_exclusive(dev, NULL); 318 if (IS_ERR(v3d->reset)) { 319 ret = PTR_ERR(v3d->reset); 320 321 if (ret == -EPROBE_DEFER) 322 return ret; 323 324 v3d->reset = NULL; 325 ret = map_regs(v3d, &v3d->bridge_regs, "bridge"); 326 if (ret) { 327 dev_err(dev, 328 "Failed to get reset control or bridge regs\n"); 329 return ret; 330 } 331 } 332 333 if (v3d->ver < 41) { 334 ret = map_regs(v3d, &v3d->gca_regs, "gca"); 335 if (ret) 336 return ret; 337 } 338 339 v3d->mmu_scratch = dma_alloc_wc(dev, 4096, &v3d->mmu_scratch_paddr, 340 GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO); 341 if (!v3d->mmu_scratch) { 342 dev_err(dev, "Failed to allocate MMU scratch page\n"); 343 return -ENOMEM; 344 } 345 346 ret = v3d_gem_init(drm); 347 if (ret) 348 goto dma_free; 349 350 ret = v3d_irq_init(v3d); 351 if (ret) 352 goto gem_destroy; 353 354 ret = drm_dev_register(drm, 0); 355 if (ret) 356 goto irq_disable; 357 358 ret = v3d_sysfs_init(dev); 359 if (ret) 360 goto drm_unregister; 361 362 return 0; 363 364 drm_unregister: 365 drm_dev_unregister(drm); 366 irq_disable: 367 v3d_irq_disable(v3d); 368 gem_destroy: 369 v3d_gem_destroy(drm); 370 dma_free: 371 dma_free_wc(dev, 4096, v3d->mmu_scratch, v3d->mmu_scratch_paddr); 372 return ret; 373 } 374 375 static void v3d_platform_drm_remove(struct platform_device *pdev) 376 { 377 struct drm_device *drm = platform_get_drvdata(pdev); 378 struct v3d_dev *v3d = to_v3d_dev(drm); 379 struct device *dev = &pdev->dev; 380 381 v3d_sysfs_destroy(dev); 382 383 drm_dev_unregister(drm); 384 385 v3d_gem_destroy(drm); 386 387 dma_free_wc(v3d->drm.dev, 4096, v3d->mmu_scratch, 388 v3d->mmu_scratch_paddr); 389 } 390 391 static struct platform_driver v3d_platform_driver = { 392 .probe = v3d_platform_drm_probe, 393 .remove = v3d_platform_drm_remove, 394 .driver = { 395 .name = "v3d", 396 .of_match_table = v3d_of_match, 397 }, 398 }; 399 400 module_platform_driver(v3d_platform_driver); 401 402 MODULE_ALIAS("platform:v3d-drm"); 403 MODULE_DESCRIPTION("Broadcom V3D DRM Driver"); 404 MODULE_AUTHOR("Eric Anholt <eric@anholt.net>"); 405 MODULE_LICENSE("GPL v2"); 406