1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2014-2018 Broadcom */ 3 4 /** 5 * DOC: Broadcom V3D Graphics Driver 6 * 7 * This driver supports the Broadcom V3D 3.3 and 4.1 OpenGL ES GPUs. 8 * For V3D 2.x support, see the VC4 driver. 9 * 10 * The V3D GPU includes a tiled render (composed of a bin and render 11 * pipelines), the TFU (texture formatting unit), and the CSD (compute 12 * shader dispatch). 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/device.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/io.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/of_platform.h> 22 #include <linux/platform_device.h> 23 #include <linux/sched/clock.h> 24 #include <linux/reset.h> 25 26 #include <drm/drm_drv.h> 27 #include <drm/drm_managed.h> 28 #include <uapi/drm/v3d_drm.h> 29 30 #include "v3d_drv.h" 31 #include "v3d_regs.h" 32 33 #define DRIVER_NAME "v3d" 34 #define DRIVER_DESC "Broadcom V3D graphics" 35 #define DRIVER_MAJOR 1 36 #define DRIVER_MINOR 0 37 #define DRIVER_PATCHLEVEL 0 38 39 /* Only expose the `super_pages` modparam if THP is enabled. */ 40 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 41 bool super_pages = true; 42 module_param_named(super_pages, super_pages, bool, 0400); 43 MODULE_PARM_DESC(super_pages, "Enable/Disable Super Pages support."); 44 #endif 45 46 static int v3d_get_param_ioctl(struct drm_device *dev, void *data, 47 struct drm_file *file_priv) 48 { 49 struct v3d_file_priv *v3d_priv = file_priv->driver_priv; 50 struct v3d_dev *v3d = to_v3d_dev(dev); 51 struct drm_v3d_get_param *args = data; 52 static const u32 reg_map[] = { 53 [DRM_V3D_PARAM_V3D_UIFCFG] = V3D_HUB_UIFCFG, 54 [DRM_V3D_PARAM_V3D_HUB_IDENT1] = V3D_HUB_IDENT1, 55 [DRM_V3D_PARAM_V3D_HUB_IDENT2] = V3D_HUB_IDENT2, 56 [DRM_V3D_PARAM_V3D_HUB_IDENT3] = V3D_HUB_IDENT3, 57 [DRM_V3D_PARAM_V3D_CORE0_IDENT0] = V3D_CTL_IDENT0, 58 [DRM_V3D_PARAM_V3D_CORE0_IDENT1] = V3D_CTL_IDENT1, 59 [DRM_V3D_PARAM_V3D_CORE0_IDENT2] = V3D_CTL_IDENT2, 60 }; 61 62 if (args->pad != 0) 63 return -EINVAL; 64 65 /* Note that DRM_V3D_PARAM_V3D_CORE0_IDENT0 is 0, so we need 66 * to explicitly allow it in the "the register in our 67 * parameter map" check. 68 */ 69 if (args->param < ARRAY_SIZE(reg_map) && 70 (reg_map[args->param] || 71 args->param == DRM_V3D_PARAM_V3D_CORE0_IDENT0)) { 72 u32 offset = reg_map[args->param]; 73 74 if (args->value != 0) 75 return -EINVAL; 76 77 if (args->param >= DRM_V3D_PARAM_V3D_CORE0_IDENT0 && 78 args->param <= DRM_V3D_PARAM_V3D_CORE0_IDENT2) { 79 args->value = V3D_CORE_READ(0, offset); 80 } else { 81 args->value = V3D_READ(offset); 82 } 83 return 0; 84 } 85 86 switch (args->param) { 87 case DRM_V3D_PARAM_SUPPORTS_TFU: 88 args->value = 1; 89 return 0; 90 case DRM_V3D_PARAM_SUPPORTS_CSD: 91 args->value = v3d_has_csd(v3d); 92 return 0; 93 case DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH: 94 args->value = 1; 95 return 0; 96 case DRM_V3D_PARAM_SUPPORTS_PERFMON: 97 args->value = (v3d->ver >= V3D_GEN_41); 98 return 0; 99 case DRM_V3D_PARAM_SUPPORTS_MULTISYNC_EXT: 100 args->value = 1; 101 return 0; 102 case DRM_V3D_PARAM_SUPPORTS_CPU_QUEUE: 103 args->value = 1; 104 return 0; 105 case DRM_V3D_PARAM_MAX_PERF_COUNTERS: 106 args->value = v3d->perfmon_info.max_counters; 107 return 0; 108 case DRM_V3D_PARAM_SUPPORTS_SUPER_PAGES: 109 args->value = !!v3d->gemfs; 110 return 0; 111 case DRM_V3D_PARAM_GLOBAL_RESET_COUNTER: 112 mutex_lock(&v3d->reset_lock); 113 args->value = v3d->reset_counter; 114 mutex_unlock(&v3d->reset_lock); 115 return 0; 116 case DRM_V3D_PARAM_CONTEXT_RESET_COUNTER: 117 mutex_lock(&v3d->reset_lock); 118 args->value = v3d_priv->reset_counter; 119 mutex_unlock(&v3d->reset_lock); 120 return 0; 121 default: 122 DRM_DEBUG("Unknown parameter %d\n", args->param); 123 return -EINVAL; 124 } 125 } 126 127 static int 128 v3d_open(struct drm_device *dev, struct drm_file *file) 129 { 130 struct v3d_dev *v3d = to_v3d_dev(dev); 131 struct v3d_file_priv *v3d_priv; 132 struct drm_gpu_scheduler *sched; 133 int i; 134 135 v3d_priv = kzalloc(sizeof(*v3d_priv), GFP_KERNEL); 136 if (!v3d_priv) 137 return -ENOMEM; 138 139 v3d_priv->v3d = v3d; 140 141 for (i = 0; i < V3D_MAX_QUEUES; i++) { 142 sched = &v3d->queue[i].sched; 143 drm_sched_entity_init(&v3d_priv->sched_entity[i], 144 DRM_SCHED_PRIORITY_NORMAL, &sched, 145 1, NULL); 146 147 memset(&v3d_priv->stats[i], 0, sizeof(v3d_priv->stats[i])); 148 seqcount_init(&v3d_priv->stats[i].lock); 149 } 150 151 v3d_perfmon_open_file(v3d_priv); 152 file->driver_priv = v3d_priv; 153 154 return 0; 155 } 156 157 static void 158 v3d_postclose(struct drm_device *dev, struct drm_file *file) 159 { 160 struct v3d_file_priv *v3d_priv = file->driver_priv; 161 enum v3d_queue q; 162 163 for (q = 0; q < V3D_MAX_QUEUES; q++) 164 drm_sched_entity_destroy(&v3d_priv->sched_entity[q]); 165 166 v3d_perfmon_close_file(v3d_priv); 167 kfree(v3d_priv); 168 } 169 170 void v3d_get_stats(const struct v3d_stats *stats, u64 timestamp, 171 u64 *active_runtime, u64 *jobs_completed) 172 { 173 unsigned int seq; 174 175 do { 176 seq = read_seqcount_begin(&stats->lock); 177 *active_runtime = stats->enabled_ns; 178 if (stats->start_ns) 179 *active_runtime += timestamp - stats->start_ns; 180 *jobs_completed = stats->jobs_completed; 181 } while (read_seqcount_retry(&stats->lock, seq)); 182 } 183 184 static void v3d_show_fdinfo(struct drm_printer *p, struct drm_file *file) 185 { 186 struct v3d_file_priv *file_priv = file->driver_priv; 187 u64 timestamp = local_clock(); 188 enum v3d_queue queue; 189 190 for (queue = 0; queue < V3D_MAX_QUEUES; queue++) { 191 struct v3d_stats *stats = &file_priv->stats[queue]; 192 u64 active_runtime, jobs_completed; 193 194 v3d_get_stats(stats, timestamp, &active_runtime, &jobs_completed); 195 196 /* Note that, in case of a GPU reset, the time spent during an 197 * attempt of executing the job is not computed in the runtime. 198 */ 199 drm_printf(p, "drm-engine-%s: \t%llu ns\n", 200 v3d_queue_to_string(queue), active_runtime); 201 202 /* Note that we only count jobs that completed. Therefore, jobs 203 * that were resubmitted due to a GPU reset are not computed. 204 */ 205 drm_printf(p, "v3d-jobs-%s: \t%llu jobs\n", 206 v3d_queue_to_string(queue), jobs_completed); 207 } 208 209 drm_show_memory_stats(p, file); 210 } 211 212 static const struct file_operations v3d_drm_fops = { 213 .owner = THIS_MODULE, 214 DRM_GEM_FOPS, 215 .show_fdinfo = drm_show_fdinfo, 216 }; 217 218 /* DRM_AUTH is required on SUBMIT_CL for now, while we don't have GMP 219 * protection between clients. Note that render nodes would be 220 * able to submit CLs that could access BOs from clients authenticated 221 * with the master node. The TFU doesn't use the GMP, so it would 222 * need to stay DRM_AUTH until we do buffer size/offset validation. 223 */ 224 static const struct drm_ioctl_desc v3d_drm_ioctls[] = { 225 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CL, v3d_submit_cl_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 226 DRM_IOCTL_DEF_DRV(V3D_WAIT_BO, v3d_wait_bo_ioctl, DRM_RENDER_ALLOW), 227 DRM_IOCTL_DEF_DRV(V3D_CREATE_BO, v3d_create_bo_ioctl, DRM_RENDER_ALLOW), 228 DRM_IOCTL_DEF_DRV(V3D_MMAP_BO, v3d_mmap_bo_ioctl, DRM_RENDER_ALLOW), 229 DRM_IOCTL_DEF_DRV(V3D_GET_PARAM, v3d_get_param_ioctl, DRM_RENDER_ALLOW), 230 DRM_IOCTL_DEF_DRV(V3D_GET_BO_OFFSET, v3d_get_bo_offset_ioctl, DRM_RENDER_ALLOW), 231 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_TFU, v3d_submit_tfu_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 232 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CSD, v3d_submit_csd_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 233 DRM_IOCTL_DEF_DRV(V3D_PERFMON_CREATE, v3d_perfmon_create_ioctl, DRM_RENDER_ALLOW), 234 DRM_IOCTL_DEF_DRV(V3D_PERFMON_DESTROY, v3d_perfmon_destroy_ioctl, DRM_RENDER_ALLOW), 235 DRM_IOCTL_DEF_DRV(V3D_PERFMON_GET_VALUES, v3d_perfmon_get_values_ioctl, DRM_RENDER_ALLOW), 236 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CPU, v3d_submit_cpu_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 237 DRM_IOCTL_DEF_DRV(V3D_PERFMON_GET_COUNTER, v3d_perfmon_get_counter_ioctl, DRM_RENDER_ALLOW), 238 DRM_IOCTL_DEF_DRV(V3D_PERFMON_SET_GLOBAL, v3d_perfmon_set_global_ioctl, DRM_RENDER_ALLOW), 239 }; 240 241 static const struct drm_driver v3d_drm_driver = { 242 .driver_features = (DRIVER_GEM | 243 DRIVER_RENDER | 244 DRIVER_SYNCOBJ), 245 246 .open = v3d_open, 247 .postclose = v3d_postclose, 248 249 #if defined(CONFIG_DEBUG_FS) 250 .debugfs_init = v3d_debugfs_init, 251 #endif 252 253 .gem_create_object = v3d_create_object, 254 .gem_prime_import_sg_table = v3d_prime_import_sg_table, 255 256 .ioctls = v3d_drm_ioctls, 257 .num_ioctls = ARRAY_SIZE(v3d_drm_ioctls), 258 .fops = &v3d_drm_fops, 259 .show_fdinfo = v3d_show_fdinfo, 260 261 .name = DRIVER_NAME, 262 .desc = DRIVER_DESC, 263 .major = DRIVER_MAJOR, 264 .minor = DRIVER_MINOR, 265 .patchlevel = DRIVER_PATCHLEVEL, 266 }; 267 268 static const struct of_device_id v3d_of_match[] = { 269 { .compatible = "brcm,2711-v3d", .data = (void *)V3D_GEN_42 }, 270 { .compatible = "brcm,2712-v3d", .data = (void *)V3D_GEN_71 }, 271 { .compatible = "brcm,7268-v3d", .data = (void *)V3D_GEN_33 }, 272 { .compatible = "brcm,7278-v3d", .data = (void *)V3D_GEN_41 }, 273 {}, 274 }; 275 MODULE_DEVICE_TABLE(of, v3d_of_match); 276 277 static void 278 v3d_idle_sms(struct v3d_dev *v3d) 279 { 280 if (v3d->ver < V3D_GEN_71) 281 return; 282 283 V3D_SMS_WRITE(V3D_SMS_TEE_CS, V3D_SMS_CLEAR_POWER_OFF); 284 285 if (wait_for((V3D_GET_FIELD(V3D_SMS_READ(V3D_SMS_TEE_CS), 286 V3D_SMS_STATE) == V3D_SMS_IDLE), 100)) { 287 DRM_ERROR("Failed to power up SMS\n"); 288 } 289 290 v3d_reset_sms(v3d); 291 } 292 293 static void 294 v3d_power_off_sms(struct v3d_dev *v3d) 295 { 296 if (v3d->ver < V3D_GEN_71) 297 return; 298 299 V3D_SMS_WRITE(V3D_SMS_TEE_CS, V3D_SMS_POWER_OFF); 300 301 if (wait_for((V3D_GET_FIELD(V3D_SMS_READ(V3D_SMS_TEE_CS), 302 V3D_SMS_STATE) == V3D_SMS_POWER_OFF_STATE), 100)) { 303 DRM_ERROR("Failed to power off SMS\n"); 304 } 305 } 306 307 static int 308 map_regs(struct v3d_dev *v3d, void __iomem **regs, const char *name) 309 { 310 *regs = devm_platform_ioremap_resource_byname(v3d_to_pdev(v3d), name); 311 return PTR_ERR_OR_ZERO(*regs); 312 } 313 314 static int v3d_platform_drm_probe(struct platform_device *pdev) 315 { 316 struct device *dev = &pdev->dev; 317 struct drm_device *drm; 318 struct v3d_dev *v3d; 319 enum v3d_gen gen; 320 int ret; 321 u32 mmu_debug; 322 u32 ident1, ident3; 323 u64 mask; 324 325 v3d = devm_drm_dev_alloc(dev, &v3d_drm_driver, struct v3d_dev, drm); 326 if (IS_ERR(v3d)) 327 return PTR_ERR(v3d); 328 329 drm = &v3d->drm; 330 331 platform_set_drvdata(pdev, drm); 332 333 gen = (uintptr_t)of_device_get_match_data(dev); 334 v3d->ver = gen; 335 336 ret = map_regs(v3d, &v3d->hub_regs, "hub"); 337 if (ret) 338 return ret; 339 340 ret = map_regs(v3d, &v3d->core_regs[0], "core0"); 341 if (ret) 342 return ret; 343 344 if (v3d->ver >= V3D_GEN_71) { 345 ret = map_regs(v3d, &v3d->sms_regs, "sms"); 346 if (ret) 347 return ret; 348 } 349 350 v3d->clk = devm_clk_get_optional(dev, NULL); 351 if (IS_ERR(v3d->clk)) 352 return dev_err_probe(dev, PTR_ERR(v3d->clk), "Failed to get V3D clock\n"); 353 354 ret = clk_prepare_enable(v3d->clk); 355 if (ret) { 356 dev_err(&pdev->dev, "Couldn't enable the V3D clock\n"); 357 return ret; 358 } 359 360 v3d_idle_sms(v3d); 361 362 mmu_debug = V3D_READ(V3D_MMU_DEBUG_INFO); 363 mask = DMA_BIT_MASK(30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_PA_WIDTH)); 364 ret = dma_set_mask_and_coherent(dev, mask); 365 if (ret) 366 goto clk_disable; 367 368 v3d->va_width = 30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_VA_WIDTH); 369 370 ident1 = V3D_READ(V3D_HUB_IDENT1); 371 v3d->ver = (V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER) * 10 + 372 V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV)); 373 /* Make sure that the V3D tech version retrieved from the HW is equal 374 * to the one advertised by the device tree. 375 */ 376 WARN_ON(v3d->ver != gen); 377 378 v3d->cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES); 379 WARN_ON(v3d->cores > 1); /* multicore not yet implemented */ 380 381 ident3 = V3D_READ(V3D_HUB_IDENT3); 382 v3d->rev = V3D_GET_FIELD(ident3, V3D_HUB_IDENT3_IPREV); 383 384 v3d_perfmon_init(v3d); 385 386 v3d->reset = devm_reset_control_get_exclusive(dev, NULL); 387 if (IS_ERR(v3d->reset)) { 388 ret = PTR_ERR(v3d->reset); 389 390 if (ret == -EPROBE_DEFER) 391 goto clk_disable; 392 393 v3d->reset = NULL; 394 ret = map_regs(v3d, &v3d->bridge_regs, "bridge"); 395 if (ret) { 396 dev_err(dev, 397 "Failed to get reset control or bridge regs\n"); 398 goto clk_disable; 399 } 400 } 401 402 if (v3d->ver < V3D_GEN_41) { 403 ret = map_regs(v3d, &v3d->gca_regs, "gca"); 404 if (ret) 405 goto clk_disable; 406 } 407 408 v3d->mmu_scratch = dma_alloc_wc(dev, 4096, &v3d->mmu_scratch_paddr, 409 GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO); 410 if (!v3d->mmu_scratch) { 411 dev_err(dev, "Failed to allocate MMU scratch page\n"); 412 ret = -ENOMEM; 413 goto clk_disable; 414 } 415 416 ret = v3d_gem_init(drm); 417 if (ret) 418 goto dma_free; 419 420 ret = v3d_irq_init(v3d); 421 if (ret) 422 goto gem_destroy; 423 424 ret = drm_dev_register(drm, 0); 425 if (ret) 426 goto irq_disable; 427 428 ret = v3d_sysfs_init(dev); 429 if (ret) 430 goto drm_unregister; 431 432 return 0; 433 434 drm_unregister: 435 drm_dev_unregister(drm); 436 irq_disable: 437 v3d_irq_disable(v3d); 438 gem_destroy: 439 v3d_gem_destroy(drm); 440 dma_free: 441 dma_free_wc(dev, 4096, v3d->mmu_scratch, v3d->mmu_scratch_paddr); 442 clk_disable: 443 clk_disable_unprepare(v3d->clk); 444 return ret; 445 } 446 447 static void v3d_platform_drm_remove(struct platform_device *pdev) 448 { 449 struct drm_device *drm = platform_get_drvdata(pdev); 450 struct v3d_dev *v3d = to_v3d_dev(drm); 451 struct device *dev = &pdev->dev; 452 453 v3d_sysfs_destroy(dev); 454 455 drm_dev_unregister(drm); 456 457 v3d_gem_destroy(drm); 458 459 dma_free_wc(v3d->drm.dev, 4096, v3d->mmu_scratch, 460 v3d->mmu_scratch_paddr); 461 462 v3d_power_off_sms(v3d); 463 464 clk_disable_unprepare(v3d->clk); 465 } 466 467 static struct platform_driver v3d_platform_driver = { 468 .probe = v3d_platform_drm_probe, 469 .remove = v3d_platform_drm_remove, 470 .driver = { 471 .name = "v3d", 472 .of_match_table = v3d_of_match, 473 }, 474 }; 475 476 module_platform_driver(v3d_platform_driver); 477 478 MODULE_ALIAS("platform:v3d-drm"); 479 MODULE_DESCRIPTION("Broadcom V3D DRM Driver"); 480 MODULE_AUTHOR("Eric Anholt <eric@anholt.net>"); 481 MODULE_LICENSE("GPL v2"); 482