1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2014-2018 Broadcom */ 3 4 /** 5 * DOC: Broadcom V3D Graphics Driver 6 * 7 * This driver supports the Broadcom V3D 3.3 and 4.1 OpenGL ES GPUs. 8 * For V3D 2.x support, see the VC4 driver. 9 * 10 * The V3D GPU includes a tiled render (composed of a bin and render 11 * pipelines), the TFU (texture formatting unit), and the CSD (compute 12 * shader dispatch). 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/device.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/io.h> 19 #include <linux/module.h> 20 #include <linux/of_platform.h> 21 #include <linux/platform_device.h> 22 #include <linux/sched/clock.h> 23 #include <linux/reset.h> 24 25 #include <drm/drm_drv.h> 26 #include <drm/drm_managed.h> 27 #include <uapi/drm/v3d_drm.h> 28 29 #include "v3d_drv.h" 30 #include "v3d_regs.h" 31 32 #define DRIVER_NAME "v3d" 33 #define DRIVER_DESC "Broadcom V3D graphics" 34 #define DRIVER_DATE "20180419" 35 #define DRIVER_MAJOR 1 36 #define DRIVER_MINOR 0 37 #define DRIVER_PATCHLEVEL 0 38 39 static int v3d_get_param_ioctl(struct drm_device *dev, void *data, 40 struct drm_file *file_priv) 41 { 42 struct v3d_dev *v3d = to_v3d_dev(dev); 43 struct drm_v3d_get_param *args = data; 44 static const u32 reg_map[] = { 45 [DRM_V3D_PARAM_V3D_UIFCFG] = V3D_HUB_UIFCFG, 46 [DRM_V3D_PARAM_V3D_HUB_IDENT1] = V3D_HUB_IDENT1, 47 [DRM_V3D_PARAM_V3D_HUB_IDENT2] = V3D_HUB_IDENT2, 48 [DRM_V3D_PARAM_V3D_HUB_IDENT3] = V3D_HUB_IDENT3, 49 [DRM_V3D_PARAM_V3D_CORE0_IDENT0] = V3D_CTL_IDENT0, 50 [DRM_V3D_PARAM_V3D_CORE0_IDENT1] = V3D_CTL_IDENT1, 51 [DRM_V3D_PARAM_V3D_CORE0_IDENT2] = V3D_CTL_IDENT2, 52 }; 53 54 if (args->pad != 0) 55 return -EINVAL; 56 57 /* Note that DRM_V3D_PARAM_V3D_CORE0_IDENT0 is 0, so we need 58 * to explicitly allow it in the "the register in our 59 * parameter map" check. 60 */ 61 if (args->param < ARRAY_SIZE(reg_map) && 62 (reg_map[args->param] || 63 args->param == DRM_V3D_PARAM_V3D_CORE0_IDENT0)) { 64 u32 offset = reg_map[args->param]; 65 66 if (args->value != 0) 67 return -EINVAL; 68 69 if (args->param >= DRM_V3D_PARAM_V3D_CORE0_IDENT0 && 70 args->param <= DRM_V3D_PARAM_V3D_CORE0_IDENT2) { 71 args->value = V3D_CORE_READ(0, offset); 72 } else { 73 args->value = V3D_READ(offset); 74 } 75 return 0; 76 } 77 78 switch (args->param) { 79 case DRM_V3D_PARAM_SUPPORTS_TFU: 80 args->value = 1; 81 return 0; 82 case DRM_V3D_PARAM_SUPPORTS_CSD: 83 args->value = v3d_has_csd(v3d); 84 return 0; 85 case DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH: 86 args->value = 1; 87 return 0; 88 case DRM_V3D_PARAM_SUPPORTS_PERFMON: 89 args->value = (v3d->ver >= 40); 90 return 0; 91 case DRM_V3D_PARAM_SUPPORTS_MULTISYNC_EXT: 92 args->value = 1; 93 return 0; 94 default: 95 DRM_DEBUG("Unknown parameter %d\n", args->param); 96 return -EINVAL; 97 } 98 } 99 100 static int 101 v3d_open(struct drm_device *dev, struct drm_file *file) 102 { 103 struct v3d_dev *v3d = to_v3d_dev(dev); 104 struct v3d_file_priv *v3d_priv; 105 struct drm_gpu_scheduler *sched; 106 int i; 107 108 v3d_priv = kzalloc(sizeof(*v3d_priv), GFP_KERNEL); 109 if (!v3d_priv) 110 return -ENOMEM; 111 112 v3d_priv->v3d = v3d; 113 114 for (i = 0; i < V3D_MAX_QUEUES; i++) { 115 v3d_priv->enabled_ns[i] = 0; 116 v3d_priv->start_ns[i] = 0; 117 v3d_priv->jobs_sent[i] = 0; 118 119 sched = &v3d->queue[i].sched; 120 drm_sched_entity_init(&v3d_priv->sched_entity[i], 121 DRM_SCHED_PRIORITY_NORMAL, &sched, 122 1, NULL); 123 } 124 125 v3d_perfmon_open_file(v3d_priv); 126 file->driver_priv = v3d_priv; 127 128 return 0; 129 } 130 131 static void 132 v3d_postclose(struct drm_device *dev, struct drm_file *file) 133 { 134 struct v3d_file_priv *v3d_priv = file->driver_priv; 135 enum v3d_queue q; 136 137 for (q = 0; q < V3D_MAX_QUEUES; q++) 138 drm_sched_entity_destroy(&v3d_priv->sched_entity[q]); 139 140 v3d_perfmon_close_file(v3d_priv); 141 kfree(v3d_priv); 142 } 143 144 static void v3d_show_fdinfo(struct drm_printer *p, struct drm_file *file) 145 { 146 struct v3d_file_priv *file_priv = file->driver_priv; 147 u64 timestamp = local_clock(); 148 enum v3d_queue queue; 149 150 for (queue = 0; queue < V3D_MAX_QUEUES; queue++) { 151 /* Note that, in case of a GPU reset, the time spent during an 152 * attempt of executing the job is not computed in the runtime. 153 */ 154 drm_printf(p, "drm-engine-%s: \t%llu ns\n", 155 v3d_queue_to_string(queue), 156 file_priv->start_ns[queue] ? file_priv->enabled_ns[queue] 157 + timestamp - file_priv->start_ns[queue] 158 : file_priv->enabled_ns[queue]); 159 160 /* Note that we only count jobs that completed. Therefore, jobs 161 * that were resubmitted due to a GPU reset are not computed. 162 */ 163 drm_printf(p, "v3d-jobs-%s: \t%llu jobs\n", 164 v3d_queue_to_string(queue), file_priv->jobs_sent[queue]); 165 } 166 } 167 168 static const struct file_operations v3d_drm_fops = { 169 .owner = THIS_MODULE, 170 DRM_GEM_FOPS, 171 .show_fdinfo = drm_show_fdinfo, 172 }; 173 174 /* DRM_AUTH is required on SUBMIT_CL for now, while we don't have GMP 175 * protection between clients. Note that render nodes would be 176 * able to submit CLs that could access BOs from clients authenticated 177 * with the master node. The TFU doesn't use the GMP, so it would 178 * need to stay DRM_AUTH until we do buffer size/offset validation. 179 */ 180 static const struct drm_ioctl_desc v3d_drm_ioctls[] = { 181 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CL, v3d_submit_cl_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 182 DRM_IOCTL_DEF_DRV(V3D_WAIT_BO, v3d_wait_bo_ioctl, DRM_RENDER_ALLOW), 183 DRM_IOCTL_DEF_DRV(V3D_CREATE_BO, v3d_create_bo_ioctl, DRM_RENDER_ALLOW), 184 DRM_IOCTL_DEF_DRV(V3D_MMAP_BO, v3d_mmap_bo_ioctl, DRM_RENDER_ALLOW), 185 DRM_IOCTL_DEF_DRV(V3D_GET_PARAM, v3d_get_param_ioctl, DRM_RENDER_ALLOW), 186 DRM_IOCTL_DEF_DRV(V3D_GET_BO_OFFSET, v3d_get_bo_offset_ioctl, DRM_RENDER_ALLOW), 187 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_TFU, v3d_submit_tfu_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 188 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CSD, v3d_submit_csd_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 189 DRM_IOCTL_DEF_DRV(V3D_PERFMON_CREATE, v3d_perfmon_create_ioctl, DRM_RENDER_ALLOW), 190 DRM_IOCTL_DEF_DRV(V3D_PERFMON_DESTROY, v3d_perfmon_destroy_ioctl, DRM_RENDER_ALLOW), 191 DRM_IOCTL_DEF_DRV(V3D_PERFMON_GET_VALUES, v3d_perfmon_get_values_ioctl, DRM_RENDER_ALLOW), 192 }; 193 194 static const struct drm_driver v3d_drm_driver = { 195 .driver_features = (DRIVER_GEM | 196 DRIVER_RENDER | 197 DRIVER_SYNCOBJ), 198 199 .open = v3d_open, 200 .postclose = v3d_postclose, 201 202 #if defined(CONFIG_DEBUG_FS) 203 .debugfs_init = v3d_debugfs_init, 204 #endif 205 206 .gem_create_object = v3d_create_object, 207 .gem_prime_import_sg_table = v3d_prime_import_sg_table, 208 209 .ioctls = v3d_drm_ioctls, 210 .num_ioctls = ARRAY_SIZE(v3d_drm_ioctls), 211 .fops = &v3d_drm_fops, 212 .show_fdinfo = v3d_show_fdinfo, 213 214 .name = DRIVER_NAME, 215 .desc = DRIVER_DESC, 216 .date = DRIVER_DATE, 217 .major = DRIVER_MAJOR, 218 .minor = DRIVER_MINOR, 219 .patchlevel = DRIVER_PATCHLEVEL, 220 }; 221 222 static const struct of_device_id v3d_of_match[] = { 223 { .compatible = "brcm,2711-v3d" }, 224 { .compatible = "brcm,2712-v3d" }, 225 { .compatible = "brcm,7268-v3d" }, 226 { .compatible = "brcm,7278-v3d" }, 227 {}, 228 }; 229 MODULE_DEVICE_TABLE(of, v3d_of_match); 230 231 static int 232 map_regs(struct v3d_dev *v3d, void __iomem **regs, const char *name) 233 { 234 *regs = devm_platform_ioremap_resource_byname(v3d_to_pdev(v3d), name); 235 return PTR_ERR_OR_ZERO(*regs); 236 } 237 238 static int v3d_platform_drm_probe(struct platform_device *pdev) 239 { 240 struct device *dev = &pdev->dev; 241 struct drm_device *drm; 242 struct v3d_dev *v3d; 243 int ret; 244 u32 mmu_debug; 245 u32 ident1; 246 u64 mask; 247 248 v3d = devm_drm_dev_alloc(dev, &v3d_drm_driver, struct v3d_dev, drm); 249 if (IS_ERR(v3d)) 250 return PTR_ERR(v3d); 251 252 drm = &v3d->drm; 253 254 platform_set_drvdata(pdev, drm); 255 256 ret = map_regs(v3d, &v3d->hub_regs, "hub"); 257 if (ret) 258 return ret; 259 260 ret = map_regs(v3d, &v3d->core_regs[0], "core0"); 261 if (ret) 262 return ret; 263 264 mmu_debug = V3D_READ(V3D_MMU_DEBUG_INFO); 265 mask = DMA_BIT_MASK(30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_PA_WIDTH)); 266 ret = dma_set_mask_and_coherent(dev, mask); 267 if (ret) 268 return ret; 269 270 v3d->va_width = 30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_VA_WIDTH); 271 272 ident1 = V3D_READ(V3D_HUB_IDENT1); 273 v3d->ver = (V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER) * 10 + 274 V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV)); 275 v3d->cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES); 276 WARN_ON(v3d->cores > 1); /* multicore not yet implemented */ 277 278 v3d->reset = devm_reset_control_get_exclusive(dev, NULL); 279 if (IS_ERR(v3d->reset)) { 280 ret = PTR_ERR(v3d->reset); 281 282 if (ret == -EPROBE_DEFER) 283 return ret; 284 285 v3d->reset = NULL; 286 ret = map_regs(v3d, &v3d->bridge_regs, "bridge"); 287 if (ret) { 288 dev_err(dev, 289 "Failed to get reset control or bridge regs\n"); 290 return ret; 291 } 292 } 293 294 if (v3d->ver < 41) { 295 ret = map_regs(v3d, &v3d->gca_regs, "gca"); 296 if (ret) 297 return ret; 298 } 299 300 v3d->mmu_scratch = dma_alloc_wc(dev, 4096, &v3d->mmu_scratch_paddr, 301 GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO); 302 if (!v3d->mmu_scratch) { 303 dev_err(dev, "Failed to allocate MMU scratch page\n"); 304 return -ENOMEM; 305 } 306 307 ret = v3d_gem_init(drm); 308 if (ret) 309 goto dma_free; 310 311 ret = v3d_irq_init(v3d); 312 if (ret) 313 goto gem_destroy; 314 315 ret = drm_dev_register(drm, 0); 316 if (ret) 317 goto irq_disable; 318 319 ret = v3d_sysfs_init(dev); 320 if (ret) 321 goto drm_unregister; 322 323 return 0; 324 325 drm_unregister: 326 drm_dev_unregister(drm); 327 irq_disable: 328 v3d_irq_disable(v3d); 329 gem_destroy: 330 v3d_gem_destroy(drm); 331 dma_free: 332 dma_free_wc(dev, 4096, v3d->mmu_scratch, v3d->mmu_scratch_paddr); 333 return ret; 334 } 335 336 static void v3d_platform_drm_remove(struct platform_device *pdev) 337 { 338 struct drm_device *drm = platform_get_drvdata(pdev); 339 struct v3d_dev *v3d = to_v3d_dev(drm); 340 struct device *dev = &pdev->dev; 341 342 v3d_sysfs_destroy(dev); 343 344 drm_dev_unregister(drm); 345 346 v3d_gem_destroy(drm); 347 348 dma_free_wc(v3d->drm.dev, 4096, v3d->mmu_scratch, 349 v3d->mmu_scratch_paddr); 350 } 351 352 static struct platform_driver v3d_platform_driver = { 353 .probe = v3d_platform_drm_probe, 354 .remove_new = v3d_platform_drm_remove, 355 .driver = { 356 .name = "v3d", 357 .of_match_table = v3d_of_match, 358 }, 359 }; 360 361 module_platform_driver(v3d_platform_driver); 362 363 MODULE_ALIAS("platform:v3d-drm"); 364 MODULE_DESCRIPTION("Broadcom V3D DRM Driver"); 365 MODULE_AUTHOR("Eric Anholt <eric@anholt.net>"); 366 MODULE_LICENSE("GPL v2"); 367