1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2014-2018 Broadcom */ 3 4 /** 5 * DOC: Broadcom V3D Graphics Driver 6 * 7 * This driver supports the Broadcom V3D 4.2 and 7.1 GPUs. 8 * 9 * Support for V3D 3.3 and 4.1 GPUs is deprecated and it will be removed 10 * in the next kernel release. 11 * 12 * For V3D 2.x support, see the VC4 driver. 13 * 14 * The V3D GPU includes a tiled render (composed of a bin and render 15 * pipelines), the TFU (texture formatting unit), and the CSD (compute 16 * shader dispatch). 17 */ 18 19 #include <linux/clk.h> 20 #include <linux/device.h> 21 #include <linux/dma-mapping.h> 22 #include <linux/io.h> 23 #include <linux/module.h> 24 #include <linux/of.h> 25 #include <linux/of_platform.h> 26 #include <linux/platform_device.h> 27 #include <linux/sched/clock.h> 28 #include <linux/reset.h> 29 30 #include <drm/drm_drv.h> 31 #include <drm/drm_managed.h> 32 #include <drm/drm_print.h> 33 #include <uapi/drm/v3d_drm.h> 34 35 #include "v3d_drv.h" 36 #include "v3d_regs.h" 37 38 #define DRIVER_NAME "v3d" 39 #define DRIVER_DESC "Broadcom V3D graphics" 40 #define DRIVER_MAJOR 1 41 #define DRIVER_MINOR 0 42 #define DRIVER_PATCHLEVEL 0 43 44 /* Only expose the `super_pages` modparam if THP is enabled. */ 45 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 46 bool super_pages = true; 47 module_param_named(super_pages, super_pages, bool, 0400); 48 MODULE_PARM_DESC(super_pages, "Enable/Disable Super Pages support."); 49 #endif 50 51 static int v3d_get_param_ioctl(struct drm_device *dev, void *data, 52 struct drm_file *file_priv) 53 { 54 struct v3d_file_priv *v3d_priv = file_priv->driver_priv; 55 struct v3d_dev *v3d = to_v3d_dev(dev); 56 struct drm_v3d_get_param *args = data; 57 static const u32 reg_map[] = { 58 [DRM_V3D_PARAM_V3D_UIFCFG] = V3D_HUB_UIFCFG, 59 [DRM_V3D_PARAM_V3D_HUB_IDENT1] = V3D_HUB_IDENT1, 60 [DRM_V3D_PARAM_V3D_HUB_IDENT2] = V3D_HUB_IDENT2, 61 [DRM_V3D_PARAM_V3D_HUB_IDENT3] = V3D_HUB_IDENT3, 62 [DRM_V3D_PARAM_V3D_CORE0_IDENT0] = V3D_CTL_IDENT0, 63 [DRM_V3D_PARAM_V3D_CORE0_IDENT1] = V3D_CTL_IDENT1, 64 [DRM_V3D_PARAM_V3D_CORE0_IDENT2] = V3D_CTL_IDENT2, 65 }; 66 int ret; 67 68 if (args->pad != 0) 69 return -EINVAL; 70 71 /* Note that DRM_V3D_PARAM_V3D_CORE0_IDENT0 is 0, so we need 72 * to explicitly allow it in the "the register in our 73 * parameter map" check. 74 */ 75 if (args->param < ARRAY_SIZE(reg_map) && 76 (reg_map[args->param] || 77 args->param == DRM_V3D_PARAM_V3D_CORE0_IDENT0)) { 78 u32 offset = reg_map[args->param]; 79 80 if (args->value != 0) 81 return -EINVAL; 82 83 ret = v3d_pm_runtime_get(v3d); 84 if (ret) 85 return ret; 86 87 if (args->param >= DRM_V3D_PARAM_V3D_CORE0_IDENT0 && 88 args->param <= DRM_V3D_PARAM_V3D_CORE0_IDENT2) { 89 args->value = V3D_CORE_READ(0, offset); 90 } else { 91 args->value = V3D_READ(offset); 92 } 93 94 v3d_pm_runtime_put(v3d); 95 96 return 0; 97 } 98 99 switch (args->param) { 100 case DRM_V3D_PARAM_SUPPORTS_TFU: 101 args->value = 1; 102 return 0; 103 case DRM_V3D_PARAM_SUPPORTS_CSD: 104 args->value = v3d_has_csd(v3d); 105 return 0; 106 case DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH: 107 args->value = 1; 108 return 0; 109 case DRM_V3D_PARAM_SUPPORTS_PERFMON: 110 args->value = (v3d->ver >= V3D_GEN_41); 111 return 0; 112 case DRM_V3D_PARAM_SUPPORTS_MULTISYNC_EXT: 113 args->value = 1; 114 return 0; 115 case DRM_V3D_PARAM_SUPPORTS_CPU_QUEUE: 116 args->value = 1; 117 return 0; 118 case DRM_V3D_PARAM_MAX_PERF_COUNTERS: 119 args->value = v3d->perfmon_info.max_counters; 120 return 0; 121 case DRM_V3D_PARAM_SUPPORTS_SUPER_PAGES: 122 args->value = !!drm_gem_get_huge_mnt(dev); 123 return 0; 124 case DRM_V3D_PARAM_GLOBAL_RESET_COUNTER: 125 args->value = atomic_read(&v3d->reset_counter); 126 return 0; 127 case DRM_V3D_PARAM_CONTEXT_RESET_COUNTER: 128 args->value = 0; 129 for (enum v3d_queue q = 0; q < V3D_MAX_QUEUES; q++) 130 args->value += atomic_read(&v3d_priv->stats[q]->reset_counter); 131 return 0; 132 default: 133 drm_dbg(dev, "Unknown parameter %d\n", args->param); 134 return -EINVAL; 135 } 136 } 137 138 static int 139 v3d_open(struct drm_device *dev, struct drm_file *file) 140 { 141 struct v3d_dev *v3d = to_v3d_dev(dev); 142 struct v3d_file_priv *v3d_priv; 143 struct drm_gpu_scheduler *sched; 144 int i, ret; 145 146 v3d_priv = kzalloc_obj(*v3d_priv); 147 if (!v3d_priv) 148 return -ENOMEM; 149 150 v3d_priv->v3d = v3d; 151 152 for (i = 0; i < V3D_MAX_QUEUES; i++) { 153 v3d_priv->stats[i] = v3d_stats_alloc(); 154 if (!v3d_priv->stats[i]) { 155 ret = -ENOMEM; 156 goto err_stats; 157 } 158 159 sched = &v3d->queue[i].sched; 160 ret = drm_sched_entity_init(&v3d_priv->sched_entity[i], 161 DRM_SCHED_PRIORITY_NORMAL, &sched, 162 1, NULL); 163 if (ret) 164 goto err_sched; 165 } 166 167 v3d_perfmon_open_file(v3d_priv); 168 file->driver_priv = v3d_priv; 169 170 return 0; 171 172 err_sched: 173 v3d_stats_put(v3d_priv->stats[i]); 174 err_stats: 175 for (i--; i >= 0; i--) { 176 drm_sched_entity_destroy(&v3d_priv->sched_entity[i]); 177 v3d_stats_put(v3d_priv->stats[i]); 178 } 179 kfree(v3d_priv); 180 return ret; 181 } 182 183 static void 184 v3d_postclose(struct drm_device *dev, struct drm_file *file) 185 { 186 struct v3d_file_priv *v3d_priv = file->driver_priv; 187 enum v3d_queue q; 188 189 for (q = 0; q < V3D_MAX_QUEUES; q++) { 190 drm_sched_entity_destroy(&v3d_priv->sched_entity[q]); 191 v3d_stats_put(v3d_priv->stats[q]); 192 } 193 194 v3d_perfmon_close_file(v3d_priv); 195 kfree(v3d_priv); 196 } 197 198 void v3d_get_stats(const struct v3d_stats *stats, u64 timestamp, 199 u64 *active_runtime, u64 *jobs_completed) 200 { 201 unsigned int seq; 202 203 do { 204 seq = raw_read_seqcount_begin(&stats->lock); 205 *active_runtime = stats->enabled_ns; 206 if (stats->start_ns) 207 *active_runtime += timestamp - stats->start_ns; 208 *jobs_completed = stats->jobs_completed; 209 } while (read_seqcount_retry(&stats->lock, seq)); 210 } 211 212 static void v3d_show_fdinfo(struct drm_printer *p, struct drm_file *file) 213 { 214 struct v3d_file_priv *file_priv = file->driver_priv; 215 u64 timestamp = local_clock(); 216 enum v3d_queue queue; 217 218 for (queue = 0; queue < V3D_MAX_QUEUES; queue++) { 219 struct v3d_stats *stats = file_priv->stats[queue]; 220 u64 active_runtime, jobs_completed; 221 222 v3d_get_stats(stats, timestamp, &active_runtime, &jobs_completed); 223 224 /* Note that, in case of a GPU reset, the time spent during an 225 * attempt of executing the job is not computed in the runtime. 226 */ 227 drm_printf(p, "drm-engine-%s: \t%llu ns\n", 228 v3d_queue_to_string(queue), active_runtime); 229 230 /* Note that we only count jobs that completed. Therefore, jobs 231 * that were resubmitted due to a GPU reset are not computed. 232 */ 233 drm_printf(p, "v3d-jobs-%s: \t%llu jobs\n", 234 v3d_queue_to_string(queue), jobs_completed); 235 } 236 237 drm_show_memory_stats(p, file); 238 } 239 240 static const struct file_operations v3d_drm_fops = { 241 .owner = THIS_MODULE, 242 DRM_GEM_FOPS, 243 .show_fdinfo = drm_show_fdinfo, 244 }; 245 246 /* DRM_AUTH is required on SUBMIT_CL for now, while we don't have GMP 247 * protection between clients. Note that render nodes would be 248 * able to submit CLs that could access BOs from clients authenticated 249 * with the master node. The TFU doesn't use the GMP, so it would 250 * need to stay DRM_AUTH until we do buffer size/offset validation. 251 */ 252 static const struct drm_ioctl_desc v3d_drm_ioctls[] = { 253 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CL, v3d_submit_cl_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 254 DRM_IOCTL_DEF_DRV(V3D_WAIT_BO, v3d_wait_bo_ioctl, DRM_RENDER_ALLOW), 255 DRM_IOCTL_DEF_DRV(V3D_CREATE_BO, v3d_create_bo_ioctl, DRM_RENDER_ALLOW), 256 DRM_IOCTL_DEF_DRV(V3D_MMAP_BO, v3d_mmap_bo_ioctl, DRM_RENDER_ALLOW), 257 DRM_IOCTL_DEF_DRV(V3D_GET_PARAM, v3d_get_param_ioctl, DRM_RENDER_ALLOW), 258 DRM_IOCTL_DEF_DRV(V3D_GET_BO_OFFSET, v3d_get_bo_offset_ioctl, DRM_RENDER_ALLOW), 259 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_TFU, v3d_submit_tfu_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 260 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CSD, v3d_submit_csd_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 261 DRM_IOCTL_DEF_DRV(V3D_PERFMON_CREATE, v3d_perfmon_create_ioctl, DRM_RENDER_ALLOW), 262 DRM_IOCTL_DEF_DRV(V3D_PERFMON_DESTROY, v3d_perfmon_destroy_ioctl, DRM_RENDER_ALLOW), 263 DRM_IOCTL_DEF_DRV(V3D_PERFMON_GET_VALUES, v3d_perfmon_get_values_ioctl, DRM_RENDER_ALLOW), 264 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CPU, v3d_submit_cpu_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 265 DRM_IOCTL_DEF_DRV(V3D_PERFMON_GET_COUNTER, v3d_perfmon_get_counter_ioctl, DRM_RENDER_ALLOW), 266 DRM_IOCTL_DEF_DRV(V3D_PERFMON_SET_GLOBAL, v3d_perfmon_set_global_ioctl, DRM_RENDER_ALLOW), 267 }; 268 269 static const struct drm_driver v3d_drm_driver = { 270 .driver_features = (DRIVER_GEM | 271 DRIVER_RENDER | 272 DRIVER_SYNCOBJ), 273 274 .open = v3d_open, 275 .postclose = v3d_postclose, 276 277 #if defined(CONFIG_DEBUG_FS) 278 .debugfs_init = v3d_debugfs_init, 279 #endif 280 281 .gem_create_object = v3d_create_object, 282 .gem_prime_import_sg_table = v3d_prime_import_sg_table, 283 284 .ioctls = v3d_drm_ioctls, 285 .num_ioctls = ARRAY_SIZE(v3d_drm_ioctls), 286 .fops = &v3d_drm_fops, 287 .show_fdinfo = v3d_show_fdinfo, 288 289 .name = DRIVER_NAME, 290 .desc = DRIVER_DESC, 291 .major = DRIVER_MAJOR, 292 .minor = DRIVER_MINOR, 293 .patchlevel = DRIVER_PATCHLEVEL, 294 }; 295 296 static const struct of_device_id v3d_of_match[] = { 297 { .compatible = "brcm,2711-v3d", .data = (void *)V3D_GEN_42 }, 298 { .compatible = "brcm,2712-v3d", .data = (void *)V3D_GEN_71 }, 299 { .compatible = "brcm,7268-v3d", .data = (void *)V3D_GEN_33 }, 300 { .compatible = "brcm,7278-v3d", .data = (void *)V3D_GEN_41 }, 301 {}, 302 }; 303 MODULE_DEVICE_TABLE(of, v3d_of_match); 304 305 static int 306 map_regs(struct v3d_dev *v3d, void __iomem **regs, const char *name) 307 { 308 *regs = devm_platform_ioremap_resource_byname(v3d_to_pdev(v3d), name); 309 return PTR_ERR_OR_ZERO(*regs); 310 } 311 312 static int v3d_platform_drm_probe(struct platform_device *pdev) 313 { 314 struct device *dev = &pdev->dev; 315 struct drm_device *drm; 316 struct v3d_dev *v3d; 317 enum v3d_gen gen; 318 int ret; 319 u32 mmu_debug; 320 u32 ident1, ident3; 321 u64 mask; 322 323 v3d = devm_drm_dev_alloc(dev, &v3d_drm_driver, struct v3d_dev, drm); 324 if (IS_ERR(v3d)) 325 return PTR_ERR(v3d); 326 327 drm = &v3d->drm; 328 329 platform_set_drvdata(pdev, drm); 330 331 gen = (uintptr_t)of_device_get_match_data(dev); 332 v3d->ver = gen; 333 334 ret = map_regs(v3d, &v3d->hub_regs, "hub"); 335 if (ret) 336 return ret; 337 338 ret = map_regs(v3d, &v3d->core_regs[0], "core0"); 339 if (ret) 340 return ret; 341 342 if (v3d->ver >= V3D_GEN_71) { 343 ret = map_regs(v3d, &v3d->sms_regs, "sms"); 344 if (ret) 345 return ret; 346 } 347 348 if (v3d->ver < V3D_GEN_41) { 349 ret = map_regs(v3d, &v3d->gca_regs, "gca"); 350 if (ret) 351 return ret; 352 } 353 354 v3d->reset = devm_reset_control_get_optional_exclusive(dev, NULL); 355 if (IS_ERR(v3d->reset)) 356 return dev_err_probe(dev, PTR_ERR(v3d->reset), 357 "Failed to get reset control\n"); 358 359 if (!v3d->reset) { 360 ret = map_regs(v3d, &v3d->bridge_regs, "bridge"); 361 if (ret) { 362 dev_err(dev, "Failed to get bridge registers\n"); 363 return ret; 364 } 365 } 366 367 v3d->clk = devm_clk_get_optional(dev, NULL); 368 if (IS_ERR(v3d->clk)) 369 return dev_err_probe(dev, PTR_ERR(v3d->clk), "Failed to get V3D clock\n"); 370 371 ret = v3d_irq_init(v3d); 372 if (ret) 373 return ret; 374 375 v3d_perfmon_init(v3d); 376 377 v3d->mmu_scratch = dma_alloc_wc(dev, 4096, &v3d->mmu_scratch_paddr, 378 GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO); 379 if (!v3d->mmu_scratch) { 380 dev_err(dev, "Failed to allocate MMU scratch page\n"); 381 return -ENOMEM; 382 } 383 384 ret = v3d_gem_init(drm); 385 if (ret) 386 goto dma_free; 387 388 ret = devm_pm_runtime_enable(dev); 389 if (ret) 390 goto gem_destroy; 391 392 ret = pm_runtime_resume_and_get(dev); 393 if (ret) 394 goto gem_destroy; 395 396 /* If PM is disabled, we need to call v3d_power_resume() manually. */ 397 if (!IS_ENABLED(CONFIG_PM)) { 398 ret = v3d_power_resume(dev); 399 if (ret) 400 goto gem_destroy; 401 } 402 403 mmu_debug = V3D_READ(V3D_MMU_DEBUG_INFO); 404 mask = DMA_BIT_MASK(30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_PA_WIDTH)); 405 ret = dma_set_mask_and_coherent(dev, mask); 406 if (ret) 407 goto runtime_pm_put; 408 409 dma_set_max_seg_size(&pdev->dev, UINT_MAX); 410 411 v3d->va_width = 30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_VA_WIDTH); 412 413 ident1 = V3D_READ(V3D_HUB_IDENT1); 414 v3d->ver = (V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER) * 10 + 415 V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV)); 416 /* Make sure that the V3D tech version retrieved from the HW is equal 417 * to the one advertised by the device tree. 418 */ 419 WARN_ON(v3d->ver != gen); 420 421 /* V3D 3.3 and V3D 4.1 has had no in-tree userspace since Mesa 422 * dropped support in 2024 (MR#25851) and they have no known users. 423 * Due to that, support is scheduled for removal in the next release. 424 */ 425 if (v3d->ver <= V3D_GEN_41) { 426 dev_warn(dev, 427 "V3D %u.%u support is deprecated and will be removed " 428 "in the next kernel release. If you rely on this hardware, " 429 "please report it to dri-devel@lists.freedesktop.org.\n", 430 v3d->ver / 10, v3d->ver % 10); 431 } 432 433 v3d->cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES); 434 WARN_ON(v3d->cores > 1); /* multicore not yet implemented */ 435 436 ident3 = V3D_READ(V3D_HUB_IDENT3); 437 v3d->rev = V3D_GET_FIELD(ident3, V3D_HUB_IDENT3_IPREV); 438 439 pm_runtime_set_autosuspend_delay(dev, 50); 440 pm_runtime_use_autosuspend(dev); 441 442 ret = drm_dev_register(drm, 0); 443 if (ret) 444 goto runtime_pm_put; 445 446 ret = v3d_sysfs_init(dev); 447 if (ret) 448 goto drm_unregister; 449 450 pm_runtime_mark_last_busy(dev); 451 pm_runtime_put_autosuspend(dev); 452 453 return 0; 454 455 drm_unregister: 456 drm_dev_unregister(drm); 457 runtime_pm_put: 458 pm_runtime_put_sync_suspend(dev); 459 gem_destroy: 460 v3d_gem_destroy(drm); 461 dma_free: 462 dma_free_wc(dev, 4096, v3d->mmu_scratch, v3d->mmu_scratch_paddr); 463 return ret; 464 } 465 466 static void v3d_platform_drm_remove(struct platform_device *pdev) 467 { 468 struct drm_device *drm = platform_get_drvdata(pdev); 469 struct v3d_dev *v3d = to_v3d_dev(drm); 470 struct device *dev = &pdev->dev; 471 472 v3d_sysfs_destroy(dev); 473 474 drm_dev_unregister(drm); 475 476 pm_runtime_suspend(dev); 477 478 /* If PM is disabled, we need to call v3d_power_suspend() manually. */ 479 if (!IS_ENABLED(CONFIG_PM)) 480 v3d_power_suspend(dev); 481 482 v3d_gem_destroy(drm); 483 484 dma_free_wc(dev, 4096, v3d->mmu_scratch, v3d->mmu_scratch_paddr); 485 } 486 487 static DEFINE_RUNTIME_DEV_PM_OPS(v3d_pm_ops, v3d_power_suspend, 488 v3d_power_resume, NULL); 489 490 static struct platform_driver v3d_platform_driver = { 491 .probe = v3d_platform_drm_probe, 492 .remove = v3d_platform_drm_remove, 493 .driver = { 494 .name = "v3d", 495 .of_match_table = v3d_of_match, 496 .pm = pm_ptr(&v3d_pm_ops), 497 }, 498 }; 499 500 module_platform_driver(v3d_platform_driver); 501 502 MODULE_ALIAS("platform:v3d-drm"); 503 MODULE_DESCRIPTION("Broadcom V3D DRM Driver"); 504 MODULE_AUTHOR("Eric Anholt <eric@anholt.net>"); 505 MODULE_LICENSE("GPL v2"); 506