1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2014-2018 Broadcom */ 3 4 /** 5 * DOC: Broadcom V3D Graphics Driver 6 * 7 * This driver supports the Broadcom V3D 3.3 and 4.1 OpenGL ES GPUs. 8 * For V3D 2.x support, see the VC4 driver. 9 * 10 * The V3D GPU includes a tiled render (composed of a bin and render 11 * pipelines), the TFU (texture formatting unit), and the CSD (compute 12 * shader dispatch). 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/device.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/io.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/of_platform.h> 22 #include <linux/platform_device.h> 23 #include <linux/sched/clock.h> 24 #include <linux/reset.h> 25 26 #include <drm/drm_drv.h> 27 #include <drm/drm_managed.h> 28 #include <uapi/drm/v3d_drm.h> 29 30 #include "v3d_drv.h" 31 #include "v3d_regs.h" 32 33 #define DRIVER_NAME "v3d" 34 #define DRIVER_DESC "Broadcom V3D graphics" 35 #define DRIVER_MAJOR 1 36 #define DRIVER_MINOR 0 37 #define DRIVER_PATCHLEVEL 0 38 39 /* Only expose the `super_pages` modparam if THP is enabled. */ 40 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 41 bool super_pages = true; 42 module_param_named(super_pages, super_pages, bool, 0400); 43 MODULE_PARM_DESC(super_pages, "Enable/Disable Super Pages support."); 44 #endif 45 46 static int v3d_get_param_ioctl(struct drm_device *dev, void *data, 47 struct drm_file *file_priv) 48 { 49 struct v3d_file_priv *v3d_priv = file_priv->driver_priv; 50 struct v3d_dev *v3d = to_v3d_dev(dev); 51 struct drm_v3d_get_param *args = data; 52 static const u32 reg_map[] = { 53 [DRM_V3D_PARAM_V3D_UIFCFG] = V3D_HUB_UIFCFG, 54 [DRM_V3D_PARAM_V3D_HUB_IDENT1] = V3D_HUB_IDENT1, 55 [DRM_V3D_PARAM_V3D_HUB_IDENT2] = V3D_HUB_IDENT2, 56 [DRM_V3D_PARAM_V3D_HUB_IDENT3] = V3D_HUB_IDENT3, 57 [DRM_V3D_PARAM_V3D_CORE0_IDENT0] = V3D_CTL_IDENT0, 58 [DRM_V3D_PARAM_V3D_CORE0_IDENT1] = V3D_CTL_IDENT1, 59 [DRM_V3D_PARAM_V3D_CORE0_IDENT2] = V3D_CTL_IDENT2, 60 }; 61 62 if (args->pad != 0) 63 return -EINVAL; 64 65 /* Note that DRM_V3D_PARAM_V3D_CORE0_IDENT0 is 0, so we need 66 * to explicitly allow it in the "the register in our 67 * parameter map" check. 68 */ 69 if (args->param < ARRAY_SIZE(reg_map) && 70 (reg_map[args->param] || 71 args->param == DRM_V3D_PARAM_V3D_CORE0_IDENT0)) { 72 u32 offset = reg_map[args->param]; 73 74 if (args->value != 0) 75 return -EINVAL; 76 77 if (args->param >= DRM_V3D_PARAM_V3D_CORE0_IDENT0 && 78 args->param <= DRM_V3D_PARAM_V3D_CORE0_IDENT2) { 79 args->value = V3D_CORE_READ(0, offset); 80 } else { 81 args->value = V3D_READ(offset); 82 } 83 return 0; 84 } 85 86 switch (args->param) { 87 case DRM_V3D_PARAM_SUPPORTS_TFU: 88 args->value = 1; 89 return 0; 90 case DRM_V3D_PARAM_SUPPORTS_CSD: 91 args->value = v3d_has_csd(v3d); 92 return 0; 93 case DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH: 94 args->value = 1; 95 return 0; 96 case DRM_V3D_PARAM_SUPPORTS_PERFMON: 97 args->value = (v3d->ver >= V3D_GEN_41); 98 return 0; 99 case DRM_V3D_PARAM_SUPPORTS_MULTISYNC_EXT: 100 args->value = 1; 101 return 0; 102 case DRM_V3D_PARAM_SUPPORTS_CPU_QUEUE: 103 args->value = 1; 104 return 0; 105 case DRM_V3D_PARAM_MAX_PERF_COUNTERS: 106 args->value = v3d->perfmon_info.max_counters; 107 return 0; 108 case DRM_V3D_PARAM_SUPPORTS_SUPER_PAGES: 109 args->value = !!v3d->gemfs; 110 return 0; 111 case DRM_V3D_PARAM_GLOBAL_RESET_COUNTER: 112 mutex_lock(&v3d->reset_lock); 113 args->value = v3d->reset_counter; 114 mutex_unlock(&v3d->reset_lock); 115 return 0; 116 case DRM_V3D_PARAM_CONTEXT_RESET_COUNTER: 117 mutex_lock(&v3d->reset_lock); 118 args->value = v3d_priv->reset_counter; 119 mutex_unlock(&v3d->reset_lock); 120 return 0; 121 default: 122 DRM_DEBUG("Unknown parameter %d\n", args->param); 123 return -EINVAL; 124 } 125 } 126 127 static int 128 v3d_open(struct drm_device *dev, struct drm_file *file) 129 { 130 struct v3d_dev *v3d = to_v3d_dev(dev); 131 struct v3d_file_priv *v3d_priv; 132 struct drm_gpu_scheduler *sched; 133 int i; 134 135 v3d_priv = kzalloc(sizeof(*v3d_priv), GFP_KERNEL); 136 if (!v3d_priv) 137 return -ENOMEM; 138 139 v3d_priv->v3d = v3d; 140 141 for (i = 0; i < V3D_MAX_QUEUES; i++) { 142 sched = &v3d->queue[i].sched; 143 drm_sched_entity_init(&v3d_priv->sched_entity[i], 144 DRM_SCHED_PRIORITY_NORMAL, &sched, 145 1, NULL); 146 147 memset(&v3d_priv->stats[i], 0, sizeof(v3d_priv->stats[i])); 148 seqcount_init(&v3d_priv->stats[i].lock); 149 } 150 151 v3d_perfmon_open_file(v3d_priv); 152 file->driver_priv = v3d_priv; 153 154 return 0; 155 } 156 157 static void 158 v3d_postclose(struct drm_device *dev, struct drm_file *file) 159 { 160 struct v3d_dev *v3d = to_v3d_dev(dev); 161 struct v3d_file_priv *v3d_priv = file->driver_priv; 162 unsigned long irqflags; 163 enum v3d_queue q; 164 165 for (q = 0; q < V3D_MAX_QUEUES; q++) { 166 struct v3d_queue_state *queue = &v3d->queue[q]; 167 struct v3d_job *job = queue->active_job; 168 169 drm_sched_entity_destroy(&v3d_priv->sched_entity[q]); 170 171 if (job && job->base.entity == &v3d_priv->sched_entity[q]) { 172 spin_lock_irqsave(&queue->queue_lock, irqflags); 173 job->file_priv = NULL; 174 spin_unlock_irqrestore(&queue->queue_lock, irqflags); 175 } 176 } 177 178 v3d_perfmon_close_file(v3d_priv); 179 kfree(v3d_priv); 180 } 181 182 void v3d_get_stats(const struct v3d_stats *stats, u64 timestamp, 183 u64 *active_runtime, u64 *jobs_completed) 184 { 185 unsigned int seq; 186 187 do { 188 seq = read_seqcount_begin(&stats->lock); 189 *active_runtime = stats->enabled_ns; 190 if (stats->start_ns) 191 *active_runtime += timestamp - stats->start_ns; 192 *jobs_completed = stats->jobs_completed; 193 } while (read_seqcount_retry(&stats->lock, seq)); 194 } 195 196 static void v3d_show_fdinfo(struct drm_printer *p, struct drm_file *file) 197 { 198 struct v3d_file_priv *file_priv = file->driver_priv; 199 u64 timestamp = local_clock(); 200 enum v3d_queue queue; 201 202 for (queue = 0; queue < V3D_MAX_QUEUES; queue++) { 203 struct v3d_stats *stats = &file_priv->stats[queue]; 204 u64 active_runtime, jobs_completed; 205 206 v3d_get_stats(stats, timestamp, &active_runtime, &jobs_completed); 207 208 /* Note that, in case of a GPU reset, the time spent during an 209 * attempt of executing the job is not computed in the runtime. 210 */ 211 drm_printf(p, "drm-engine-%s: \t%llu ns\n", 212 v3d_queue_to_string(queue), active_runtime); 213 214 /* Note that we only count jobs that completed. Therefore, jobs 215 * that were resubmitted due to a GPU reset are not computed. 216 */ 217 drm_printf(p, "v3d-jobs-%s: \t%llu jobs\n", 218 v3d_queue_to_string(queue), jobs_completed); 219 } 220 221 drm_show_memory_stats(p, file); 222 } 223 224 static const struct file_operations v3d_drm_fops = { 225 .owner = THIS_MODULE, 226 DRM_GEM_FOPS, 227 .show_fdinfo = drm_show_fdinfo, 228 }; 229 230 /* DRM_AUTH is required on SUBMIT_CL for now, while we don't have GMP 231 * protection between clients. Note that render nodes would be 232 * able to submit CLs that could access BOs from clients authenticated 233 * with the master node. The TFU doesn't use the GMP, so it would 234 * need to stay DRM_AUTH until we do buffer size/offset validation. 235 */ 236 static const struct drm_ioctl_desc v3d_drm_ioctls[] = { 237 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CL, v3d_submit_cl_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 238 DRM_IOCTL_DEF_DRV(V3D_WAIT_BO, v3d_wait_bo_ioctl, DRM_RENDER_ALLOW), 239 DRM_IOCTL_DEF_DRV(V3D_CREATE_BO, v3d_create_bo_ioctl, DRM_RENDER_ALLOW), 240 DRM_IOCTL_DEF_DRV(V3D_MMAP_BO, v3d_mmap_bo_ioctl, DRM_RENDER_ALLOW), 241 DRM_IOCTL_DEF_DRV(V3D_GET_PARAM, v3d_get_param_ioctl, DRM_RENDER_ALLOW), 242 DRM_IOCTL_DEF_DRV(V3D_GET_BO_OFFSET, v3d_get_bo_offset_ioctl, DRM_RENDER_ALLOW), 243 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_TFU, v3d_submit_tfu_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 244 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CSD, v3d_submit_csd_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 245 DRM_IOCTL_DEF_DRV(V3D_PERFMON_CREATE, v3d_perfmon_create_ioctl, DRM_RENDER_ALLOW), 246 DRM_IOCTL_DEF_DRV(V3D_PERFMON_DESTROY, v3d_perfmon_destroy_ioctl, DRM_RENDER_ALLOW), 247 DRM_IOCTL_DEF_DRV(V3D_PERFMON_GET_VALUES, v3d_perfmon_get_values_ioctl, DRM_RENDER_ALLOW), 248 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CPU, v3d_submit_cpu_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 249 DRM_IOCTL_DEF_DRV(V3D_PERFMON_GET_COUNTER, v3d_perfmon_get_counter_ioctl, DRM_RENDER_ALLOW), 250 DRM_IOCTL_DEF_DRV(V3D_PERFMON_SET_GLOBAL, v3d_perfmon_set_global_ioctl, DRM_RENDER_ALLOW), 251 }; 252 253 static const struct drm_driver v3d_drm_driver = { 254 .driver_features = (DRIVER_GEM | 255 DRIVER_RENDER | 256 DRIVER_SYNCOBJ), 257 258 .open = v3d_open, 259 .postclose = v3d_postclose, 260 261 #if defined(CONFIG_DEBUG_FS) 262 .debugfs_init = v3d_debugfs_init, 263 #endif 264 265 .gem_create_object = v3d_create_object, 266 .gem_prime_import_sg_table = v3d_prime_import_sg_table, 267 268 .ioctls = v3d_drm_ioctls, 269 .num_ioctls = ARRAY_SIZE(v3d_drm_ioctls), 270 .fops = &v3d_drm_fops, 271 .show_fdinfo = v3d_show_fdinfo, 272 273 .name = DRIVER_NAME, 274 .desc = DRIVER_DESC, 275 .major = DRIVER_MAJOR, 276 .minor = DRIVER_MINOR, 277 .patchlevel = DRIVER_PATCHLEVEL, 278 }; 279 280 static const struct of_device_id v3d_of_match[] = { 281 { .compatible = "brcm,2711-v3d", .data = (void *)V3D_GEN_42 }, 282 { .compatible = "brcm,2712-v3d", .data = (void *)V3D_GEN_71 }, 283 { .compatible = "brcm,7268-v3d", .data = (void *)V3D_GEN_33 }, 284 { .compatible = "brcm,7278-v3d", .data = (void *)V3D_GEN_41 }, 285 {}, 286 }; 287 MODULE_DEVICE_TABLE(of, v3d_of_match); 288 289 static void 290 v3d_idle_sms(struct v3d_dev *v3d) 291 { 292 if (v3d->ver < V3D_GEN_71) 293 return; 294 295 V3D_SMS_WRITE(V3D_SMS_TEE_CS, V3D_SMS_CLEAR_POWER_OFF); 296 297 if (wait_for((V3D_GET_FIELD(V3D_SMS_READ(V3D_SMS_TEE_CS), 298 V3D_SMS_STATE) == V3D_SMS_IDLE), 100)) { 299 DRM_ERROR("Failed to power up SMS\n"); 300 } 301 302 v3d_reset_sms(v3d); 303 } 304 305 static void 306 v3d_power_off_sms(struct v3d_dev *v3d) 307 { 308 if (v3d->ver < V3D_GEN_71) 309 return; 310 311 V3D_SMS_WRITE(V3D_SMS_TEE_CS, V3D_SMS_POWER_OFF); 312 313 if (wait_for((V3D_GET_FIELD(V3D_SMS_READ(V3D_SMS_TEE_CS), 314 V3D_SMS_STATE) == V3D_SMS_POWER_OFF_STATE), 100)) { 315 DRM_ERROR("Failed to power off SMS\n"); 316 } 317 } 318 319 static int 320 map_regs(struct v3d_dev *v3d, void __iomem **regs, const char *name) 321 { 322 *regs = devm_platform_ioremap_resource_byname(v3d_to_pdev(v3d), name); 323 return PTR_ERR_OR_ZERO(*regs); 324 } 325 326 static int v3d_platform_drm_probe(struct platform_device *pdev) 327 { 328 struct device *dev = &pdev->dev; 329 struct drm_device *drm; 330 struct v3d_dev *v3d; 331 enum v3d_gen gen; 332 int ret; 333 u32 mmu_debug; 334 u32 ident1, ident3; 335 u64 mask; 336 337 v3d = devm_drm_dev_alloc(dev, &v3d_drm_driver, struct v3d_dev, drm); 338 if (IS_ERR(v3d)) 339 return PTR_ERR(v3d); 340 341 drm = &v3d->drm; 342 343 platform_set_drvdata(pdev, drm); 344 345 gen = (uintptr_t)of_device_get_match_data(dev); 346 v3d->ver = gen; 347 348 ret = map_regs(v3d, &v3d->hub_regs, "hub"); 349 if (ret) 350 return ret; 351 352 ret = map_regs(v3d, &v3d->core_regs[0], "core0"); 353 if (ret) 354 return ret; 355 356 if (v3d->ver >= V3D_GEN_71) { 357 ret = map_regs(v3d, &v3d->sms_regs, "sms"); 358 if (ret) 359 return ret; 360 } 361 362 v3d->clk = devm_clk_get_optional(dev, NULL); 363 if (IS_ERR(v3d->clk)) 364 return dev_err_probe(dev, PTR_ERR(v3d->clk), "Failed to get V3D clock\n"); 365 366 ret = clk_prepare_enable(v3d->clk); 367 if (ret) { 368 dev_err(&pdev->dev, "Couldn't enable the V3D clock\n"); 369 return ret; 370 } 371 372 v3d_idle_sms(v3d); 373 374 mmu_debug = V3D_READ(V3D_MMU_DEBUG_INFO); 375 mask = DMA_BIT_MASK(30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_PA_WIDTH)); 376 ret = dma_set_mask_and_coherent(dev, mask); 377 if (ret) 378 goto clk_disable; 379 380 v3d->va_width = 30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_VA_WIDTH); 381 382 ident1 = V3D_READ(V3D_HUB_IDENT1); 383 v3d->ver = (V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER) * 10 + 384 V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV)); 385 /* Make sure that the V3D tech version retrieved from the HW is equal 386 * to the one advertised by the device tree. 387 */ 388 WARN_ON(v3d->ver != gen); 389 390 v3d->cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES); 391 WARN_ON(v3d->cores > 1); /* multicore not yet implemented */ 392 393 ident3 = V3D_READ(V3D_HUB_IDENT3); 394 v3d->rev = V3D_GET_FIELD(ident3, V3D_HUB_IDENT3_IPREV); 395 396 v3d_perfmon_init(v3d); 397 398 v3d->reset = devm_reset_control_get_exclusive(dev, NULL); 399 if (IS_ERR(v3d->reset)) { 400 ret = PTR_ERR(v3d->reset); 401 402 if (ret == -EPROBE_DEFER) 403 goto clk_disable; 404 405 v3d->reset = NULL; 406 ret = map_regs(v3d, &v3d->bridge_regs, "bridge"); 407 if (ret) { 408 dev_err(dev, 409 "Failed to get reset control or bridge regs\n"); 410 goto clk_disable; 411 } 412 } 413 414 if (v3d->ver < V3D_GEN_41) { 415 ret = map_regs(v3d, &v3d->gca_regs, "gca"); 416 if (ret) 417 goto clk_disable; 418 } 419 420 v3d->mmu_scratch = dma_alloc_wc(dev, 4096, &v3d->mmu_scratch_paddr, 421 GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO); 422 if (!v3d->mmu_scratch) { 423 dev_err(dev, "Failed to allocate MMU scratch page\n"); 424 ret = -ENOMEM; 425 goto clk_disable; 426 } 427 428 ret = v3d_gem_init(drm); 429 if (ret) 430 goto dma_free; 431 432 ret = v3d_irq_init(v3d); 433 if (ret) 434 goto gem_destroy; 435 436 ret = drm_dev_register(drm, 0); 437 if (ret) 438 goto irq_disable; 439 440 ret = v3d_sysfs_init(dev); 441 if (ret) 442 goto drm_unregister; 443 444 return 0; 445 446 drm_unregister: 447 drm_dev_unregister(drm); 448 irq_disable: 449 v3d_irq_disable(v3d); 450 gem_destroy: 451 v3d_gem_destroy(drm); 452 dma_free: 453 dma_free_wc(dev, 4096, v3d->mmu_scratch, v3d->mmu_scratch_paddr); 454 clk_disable: 455 clk_disable_unprepare(v3d->clk); 456 return ret; 457 } 458 459 static void v3d_platform_drm_remove(struct platform_device *pdev) 460 { 461 struct drm_device *drm = platform_get_drvdata(pdev); 462 struct v3d_dev *v3d = to_v3d_dev(drm); 463 struct device *dev = &pdev->dev; 464 465 v3d_sysfs_destroy(dev); 466 467 drm_dev_unregister(drm); 468 469 v3d_gem_destroy(drm); 470 471 dma_free_wc(v3d->drm.dev, 4096, v3d->mmu_scratch, 472 v3d->mmu_scratch_paddr); 473 474 v3d_power_off_sms(v3d); 475 476 clk_disable_unprepare(v3d->clk); 477 } 478 479 static struct platform_driver v3d_platform_driver = { 480 .probe = v3d_platform_drm_probe, 481 .remove = v3d_platform_drm_remove, 482 .driver = { 483 .name = "v3d", 484 .of_match_table = v3d_of_match, 485 }, 486 }; 487 488 module_platform_driver(v3d_platform_driver); 489 490 MODULE_ALIAS("platform:v3d-drm"); 491 MODULE_DESCRIPTION("Broadcom V3D DRM Driver"); 492 MODULE_AUTHOR("Eric Anholt <eric@anholt.net>"); 493 MODULE_LICENSE("GPL v2"); 494