1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2014-2018 Broadcom */ 3 4 /** 5 * DOC: Broadcom V3D Graphics Driver 6 * 7 * This driver supports the Broadcom V3D 3.3 and 4.1 OpenGL ES GPUs. 8 * For V3D 2.x support, see the VC4 driver. 9 * 10 * The V3D GPU includes a tiled render (composed of a bin and render 11 * pipelines), the TFU (texture formatting unit), and the CSD (compute 12 * shader dispatch). 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/device.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/io.h> 19 #include <linux/module.h> 20 #include <linux/of_platform.h> 21 #include <linux/platform_device.h> 22 #include <linux/sched/clock.h> 23 #include <linux/reset.h> 24 25 #include <drm/drm_drv.h> 26 #include <drm/drm_managed.h> 27 #include <uapi/drm/v3d_drm.h> 28 29 #include "v3d_drv.h" 30 #include "v3d_regs.h" 31 32 #define DRIVER_NAME "v3d" 33 #define DRIVER_DESC "Broadcom V3D graphics" 34 #define DRIVER_DATE "20180419" 35 #define DRIVER_MAJOR 1 36 #define DRIVER_MINOR 0 37 #define DRIVER_PATCHLEVEL 0 38 39 static int v3d_get_param_ioctl(struct drm_device *dev, void *data, 40 struct drm_file *file_priv) 41 { 42 struct v3d_dev *v3d = to_v3d_dev(dev); 43 struct drm_v3d_get_param *args = data; 44 static const u32 reg_map[] = { 45 [DRM_V3D_PARAM_V3D_UIFCFG] = V3D_HUB_UIFCFG, 46 [DRM_V3D_PARAM_V3D_HUB_IDENT1] = V3D_HUB_IDENT1, 47 [DRM_V3D_PARAM_V3D_HUB_IDENT2] = V3D_HUB_IDENT2, 48 [DRM_V3D_PARAM_V3D_HUB_IDENT3] = V3D_HUB_IDENT3, 49 [DRM_V3D_PARAM_V3D_CORE0_IDENT0] = V3D_CTL_IDENT0, 50 [DRM_V3D_PARAM_V3D_CORE0_IDENT1] = V3D_CTL_IDENT1, 51 [DRM_V3D_PARAM_V3D_CORE0_IDENT2] = V3D_CTL_IDENT2, 52 }; 53 54 if (args->pad != 0) 55 return -EINVAL; 56 57 /* Note that DRM_V3D_PARAM_V3D_CORE0_IDENT0 is 0, so we need 58 * to explicitly allow it in the "the register in our 59 * parameter map" check. 60 */ 61 if (args->param < ARRAY_SIZE(reg_map) && 62 (reg_map[args->param] || 63 args->param == DRM_V3D_PARAM_V3D_CORE0_IDENT0)) { 64 u32 offset = reg_map[args->param]; 65 66 if (args->value != 0) 67 return -EINVAL; 68 69 if (args->param >= DRM_V3D_PARAM_V3D_CORE0_IDENT0 && 70 args->param <= DRM_V3D_PARAM_V3D_CORE0_IDENT2) { 71 args->value = V3D_CORE_READ(0, offset); 72 } else { 73 args->value = V3D_READ(offset); 74 } 75 return 0; 76 } 77 78 switch (args->param) { 79 case DRM_V3D_PARAM_SUPPORTS_TFU: 80 args->value = 1; 81 return 0; 82 case DRM_V3D_PARAM_SUPPORTS_CSD: 83 args->value = v3d_has_csd(v3d); 84 return 0; 85 case DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH: 86 args->value = 1; 87 return 0; 88 case DRM_V3D_PARAM_SUPPORTS_PERFMON: 89 args->value = (v3d->ver >= 40); 90 return 0; 91 case DRM_V3D_PARAM_SUPPORTS_MULTISYNC_EXT: 92 args->value = 1; 93 return 0; 94 case DRM_V3D_PARAM_SUPPORTS_CPU_QUEUE: 95 args->value = 1; 96 return 0; 97 default: 98 DRM_DEBUG("Unknown parameter %d\n", args->param); 99 return -EINVAL; 100 } 101 } 102 103 static int 104 v3d_open(struct drm_device *dev, struct drm_file *file) 105 { 106 struct v3d_dev *v3d = to_v3d_dev(dev); 107 struct v3d_file_priv *v3d_priv; 108 struct drm_gpu_scheduler *sched; 109 int i; 110 111 v3d_priv = kzalloc(sizeof(*v3d_priv), GFP_KERNEL); 112 if (!v3d_priv) 113 return -ENOMEM; 114 115 v3d_priv->v3d = v3d; 116 117 for (i = 0; i < V3D_MAX_QUEUES; i++) { 118 sched = &v3d->queue[i].sched; 119 drm_sched_entity_init(&v3d_priv->sched_entity[i], 120 DRM_SCHED_PRIORITY_NORMAL, &sched, 121 1, NULL); 122 123 memset(&v3d_priv->stats[i], 0, sizeof(v3d_priv->stats[i])); 124 seqcount_init(&v3d_priv->stats[i].lock); 125 } 126 127 v3d_perfmon_open_file(v3d_priv); 128 file->driver_priv = v3d_priv; 129 130 return 0; 131 } 132 133 static void 134 v3d_postclose(struct drm_device *dev, struct drm_file *file) 135 { 136 struct v3d_file_priv *v3d_priv = file->driver_priv; 137 enum v3d_queue q; 138 139 for (q = 0; q < V3D_MAX_QUEUES; q++) 140 drm_sched_entity_destroy(&v3d_priv->sched_entity[q]); 141 142 v3d_perfmon_close_file(v3d_priv); 143 kfree(v3d_priv); 144 } 145 146 void v3d_get_stats(const struct v3d_stats *stats, u64 timestamp, 147 u64 *active_runtime, u64 *jobs_completed) 148 { 149 unsigned int seq; 150 151 do { 152 seq = read_seqcount_begin(&stats->lock); 153 *active_runtime = stats->enabled_ns; 154 if (stats->start_ns) 155 *active_runtime += timestamp - stats->start_ns; 156 *jobs_completed = stats->jobs_completed; 157 } while (read_seqcount_retry(&stats->lock, seq)); 158 } 159 160 static void v3d_show_fdinfo(struct drm_printer *p, struct drm_file *file) 161 { 162 struct v3d_file_priv *file_priv = file->driver_priv; 163 u64 timestamp = local_clock(); 164 enum v3d_queue queue; 165 166 for (queue = 0; queue < V3D_MAX_QUEUES; queue++) { 167 struct v3d_stats *stats = &file_priv->stats[queue]; 168 u64 active_runtime, jobs_completed; 169 170 v3d_get_stats(stats, timestamp, &active_runtime, &jobs_completed); 171 172 /* Note that, in case of a GPU reset, the time spent during an 173 * attempt of executing the job is not computed in the runtime. 174 */ 175 drm_printf(p, "drm-engine-%s: \t%llu ns\n", 176 v3d_queue_to_string(queue), active_runtime); 177 178 /* Note that we only count jobs that completed. Therefore, jobs 179 * that were resubmitted due to a GPU reset are not computed. 180 */ 181 drm_printf(p, "v3d-jobs-%s: \t%llu jobs\n", 182 v3d_queue_to_string(queue), jobs_completed); 183 } 184 } 185 186 static const struct file_operations v3d_drm_fops = { 187 .owner = THIS_MODULE, 188 DRM_GEM_FOPS, 189 .show_fdinfo = drm_show_fdinfo, 190 }; 191 192 /* DRM_AUTH is required on SUBMIT_CL for now, while we don't have GMP 193 * protection between clients. Note that render nodes would be 194 * able to submit CLs that could access BOs from clients authenticated 195 * with the master node. The TFU doesn't use the GMP, so it would 196 * need to stay DRM_AUTH until we do buffer size/offset validation. 197 */ 198 static const struct drm_ioctl_desc v3d_drm_ioctls[] = { 199 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CL, v3d_submit_cl_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 200 DRM_IOCTL_DEF_DRV(V3D_WAIT_BO, v3d_wait_bo_ioctl, DRM_RENDER_ALLOW), 201 DRM_IOCTL_DEF_DRV(V3D_CREATE_BO, v3d_create_bo_ioctl, DRM_RENDER_ALLOW), 202 DRM_IOCTL_DEF_DRV(V3D_MMAP_BO, v3d_mmap_bo_ioctl, DRM_RENDER_ALLOW), 203 DRM_IOCTL_DEF_DRV(V3D_GET_PARAM, v3d_get_param_ioctl, DRM_RENDER_ALLOW), 204 DRM_IOCTL_DEF_DRV(V3D_GET_BO_OFFSET, v3d_get_bo_offset_ioctl, DRM_RENDER_ALLOW), 205 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_TFU, v3d_submit_tfu_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 206 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CSD, v3d_submit_csd_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 207 DRM_IOCTL_DEF_DRV(V3D_PERFMON_CREATE, v3d_perfmon_create_ioctl, DRM_RENDER_ALLOW), 208 DRM_IOCTL_DEF_DRV(V3D_PERFMON_DESTROY, v3d_perfmon_destroy_ioctl, DRM_RENDER_ALLOW), 209 DRM_IOCTL_DEF_DRV(V3D_PERFMON_GET_VALUES, v3d_perfmon_get_values_ioctl, DRM_RENDER_ALLOW), 210 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CPU, v3d_submit_cpu_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 211 }; 212 213 static const struct drm_driver v3d_drm_driver = { 214 .driver_features = (DRIVER_GEM | 215 DRIVER_RENDER | 216 DRIVER_SYNCOBJ), 217 218 .open = v3d_open, 219 .postclose = v3d_postclose, 220 221 #if defined(CONFIG_DEBUG_FS) 222 .debugfs_init = v3d_debugfs_init, 223 #endif 224 225 .gem_create_object = v3d_create_object, 226 .gem_prime_import_sg_table = v3d_prime_import_sg_table, 227 228 .ioctls = v3d_drm_ioctls, 229 .num_ioctls = ARRAY_SIZE(v3d_drm_ioctls), 230 .fops = &v3d_drm_fops, 231 .show_fdinfo = v3d_show_fdinfo, 232 233 .name = DRIVER_NAME, 234 .desc = DRIVER_DESC, 235 .date = DRIVER_DATE, 236 .major = DRIVER_MAJOR, 237 .minor = DRIVER_MINOR, 238 .patchlevel = DRIVER_PATCHLEVEL, 239 }; 240 241 static const struct of_device_id v3d_of_match[] = { 242 { .compatible = "brcm,2711-v3d" }, 243 { .compatible = "brcm,2712-v3d" }, 244 { .compatible = "brcm,7268-v3d" }, 245 { .compatible = "brcm,7278-v3d" }, 246 {}, 247 }; 248 MODULE_DEVICE_TABLE(of, v3d_of_match); 249 250 static int 251 map_regs(struct v3d_dev *v3d, void __iomem **regs, const char *name) 252 { 253 *regs = devm_platform_ioremap_resource_byname(v3d_to_pdev(v3d), name); 254 return PTR_ERR_OR_ZERO(*regs); 255 } 256 257 static int v3d_platform_drm_probe(struct platform_device *pdev) 258 { 259 struct device *dev = &pdev->dev; 260 struct drm_device *drm; 261 struct v3d_dev *v3d; 262 int ret; 263 u32 mmu_debug; 264 u32 ident1; 265 u64 mask; 266 267 v3d = devm_drm_dev_alloc(dev, &v3d_drm_driver, struct v3d_dev, drm); 268 if (IS_ERR(v3d)) 269 return PTR_ERR(v3d); 270 271 drm = &v3d->drm; 272 273 platform_set_drvdata(pdev, drm); 274 275 ret = map_regs(v3d, &v3d->hub_regs, "hub"); 276 if (ret) 277 return ret; 278 279 ret = map_regs(v3d, &v3d->core_regs[0], "core0"); 280 if (ret) 281 return ret; 282 283 mmu_debug = V3D_READ(V3D_MMU_DEBUG_INFO); 284 mask = DMA_BIT_MASK(30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_PA_WIDTH)); 285 ret = dma_set_mask_and_coherent(dev, mask); 286 if (ret) 287 return ret; 288 289 v3d->va_width = 30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_VA_WIDTH); 290 291 ident1 = V3D_READ(V3D_HUB_IDENT1); 292 v3d->ver = (V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER) * 10 + 293 V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV)); 294 v3d->cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES); 295 WARN_ON(v3d->cores > 1); /* multicore not yet implemented */ 296 297 v3d->reset = devm_reset_control_get_exclusive(dev, NULL); 298 if (IS_ERR(v3d->reset)) { 299 ret = PTR_ERR(v3d->reset); 300 301 if (ret == -EPROBE_DEFER) 302 return ret; 303 304 v3d->reset = NULL; 305 ret = map_regs(v3d, &v3d->bridge_regs, "bridge"); 306 if (ret) { 307 dev_err(dev, 308 "Failed to get reset control or bridge regs\n"); 309 return ret; 310 } 311 } 312 313 if (v3d->ver < 41) { 314 ret = map_regs(v3d, &v3d->gca_regs, "gca"); 315 if (ret) 316 return ret; 317 } 318 319 v3d->mmu_scratch = dma_alloc_wc(dev, 4096, &v3d->mmu_scratch_paddr, 320 GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO); 321 if (!v3d->mmu_scratch) { 322 dev_err(dev, "Failed to allocate MMU scratch page\n"); 323 return -ENOMEM; 324 } 325 326 ret = v3d_gem_init(drm); 327 if (ret) 328 goto dma_free; 329 330 ret = v3d_irq_init(v3d); 331 if (ret) 332 goto gem_destroy; 333 334 ret = drm_dev_register(drm, 0); 335 if (ret) 336 goto irq_disable; 337 338 ret = v3d_sysfs_init(dev); 339 if (ret) 340 goto drm_unregister; 341 342 return 0; 343 344 drm_unregister: 345 drm_dev_unregister(drm); 346 irq_disable: 347 v3d_irq_disable(v3d); 348 gem_destroy: 349 v3d_gem_destroy(drm); 350 dma_free: 351 dma_free_wc(dev, 4096, v3d->mmu_scratch, v3d->mmu_scratch_paddr); 352 return ret; 353 } 354 355 static void v3d_platform_drm_remove(struct platform_device *pdev) 356 { 357 struct drm_device *drm = platform_get_drvdata(pdev); 358 struct v3d_dev *v3d = to_v3d_dev(drm); 359 struct device *dev = &pdev->dev; 360 361 v3d_sysfs_destroy(dev); 362 363 drm_dev_unregister(drm); 364 365 v3d_gem_destroy(drm); 366 367 dma_free_wc(v3d->drm.dev, 4096, v3d->mmu_scratch, 368 v3d->mmu_scratch_paddr); 369 } 370 371 static struct platform_driver v3d_platform_driver = { 372 .probe = v3d_platform_drm_probe, 373 .remove_new = v3d_platform_drm_remove, 374 .driver = { 375 .name = "v3d", 376 .of_match_table = v3d_of_match, 377 }, 378 }; 379 380 module_platform_driver(v3d_platform_driver); 381 382 MODULE_ALIAS("platform:v3d-drm"); 383 MODULE_DESCRIPTION("Broadcom V3D DRM Driver"); 384 MODULE_AUTHOR("Eric Anholt <eric@anholt.net>"); 385 MODULE_LICENSE("GPL v2"); 386