1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2014-2018 Broadcom */ 3 4 #include <linux/circ_buf.h> 5 #include <linux/ctype.h> 6 #include <linux/debugfs.h> 7 #include <linux/seq_file.h> 8 #include <linux/string_helpers.h> 9 10 #include <drm/drm_debugfs.h> 11 #include <drm/drm_print.h> 12 13 #include "v3d_drv.h" 14 #include "v3d_regs.h" 15 16 #define REGDEF(min_ver, max_ver, reg) { min_ver, max_ver, reg, #reg } 17 struct v3d_reg_def { 18 u32 min_ver; 19 u32 max_ver; 20 u32 reg; 21 const char *name; 22 }; 23 24 static const struct v3d_reg_def v3d_hub_reg_defs[] = { 25 REGDEF(V3D_GEN_33, V3D_GEN_42, V3D_HUB_AXICFG), 26 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_UIFCFG), 27 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_IDENT0), 28 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_IDENT1), 29 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_IDENT2), 30 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_IDENT3), 31 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_INT_STS), 32 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_INT_MSK_STS), 33 34 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_MMU_CTL), 35 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_MMU_VIO_ADDR), 36 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_MMU_VIO_ID), 37 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_MMU_DEBUG_INFO), 38 39 REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_GMP_STATUS(71)), 40 REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_GMP_CFG(71)), 41 REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_GMP_VIO_ADDR(71)), 42 }; 43 44 static const struct v3d_reg_def v3d_gca_reg_defs[] = { 45 REGDEF(V3D_GEN_33, V3D_GEN_33, V3D_GCA_SAFE_SHUTDOWN), 46 REGDEF(V3D_GEN_33, V3D_GEN_33, V3D_GCA_SAFE_SHUTDOWN_ACK), 47 }; 48 49 static const struct v3d_reg_def v3d_core_reg_defs[] = { 50 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_IDENT0), 51 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_IDENT1), 52 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_IDENT2), 53 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_MISCCFG), 54 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_INT_STS), 55 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_INT_MSK_STS), 56 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT0CS), 57 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT0CA), 58 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT0EA), 59 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT1CS), 60 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT1CA), 61 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT1EA), 62 63 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_PTB_BPCA), 64 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_PTB_BPCS), 65 66 REGDEF(V3D_GEN_33, V3D_GEN_42, V3D_GMP_STATUS(33)), 67 REGDEF(V3D_GEN_33, V3D_GEN_42, V3D_GMP_CFG(33)), 68 REGDEF(V3D_GEN_33, V3D_GEN_42, V3D_GMP_VIO_ADDR(33)), 69 70 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_ERR_FDBGO), 71 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_ERR_FDBGB), 72 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_ERR_FDBGS), 73 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_ERR_STAT), 74 }; 75 76 static const struct v3d_reg_def v3d_csd_reg_defs[] = { 77 REGDEF(V3D_GEN_41, V3D_GEN_71, V3D_CSD_STATUS), 78 REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG0(41)), 79 REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG1(41)), 80 REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG2(41)), 81 REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG3(41)), 82 REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG4(41)), 83 REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG5(41)), 84 REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG6(41)), 85 REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG0(71)), 86 REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG1(71)), 87 REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG2(71)), 88 REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG3(71)), 89 REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG4(71)), 90 REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG5(71)), 91 REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG6(71)), 92 REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_V7_CSD_CURRENT_CFG7), 93 }; 94 95 static int v3d_v3d_debugfs_regs(struct seq_file *m, void *unused) 96 { 97 struct drm_debugfs_entry *entry = m->private; 98 struct drm_device *dev = entry->dev; 99 struct v3d_dev *v3d = to_v3d_dev(dev); 100 int i, core; 101 102 for (i = 0; i < ARRAY_SIZE(v3d_hub_reg_defs); i++) { 103 const struct v3d_reg_def *def = &v3d_hub_reg_defs[i]; 104 105 if (v3d->ver >= def->min_ver && v3d->ver <= def->max_ver) { 106 seq_printf(m, "%s (0x%04x): 0x%08x\n", 107 def->name, def->reg, V3D_READ(def->reg)); 108 } 109 } 110 111 for (i = 0; i < ARRAY_SIZE(v3d_gca_reg_defs); i++) { 112 const struct v3d_reg_def *def = &v3d_gca_reg_defs[i]; 113 114 if (v3d->ver >= def->min_ver && v3d->ver <= def->max_ver) { 115 seq_printf(m, "%s (0x%04x): 0x%08x\n", 116 def->name, def->reg, V3D_GCA_READ(def->reg)); 117 } 118 } 119 120 for (core = 0; core < v3d->cores; core++) { 121 for (i = 0; i < ARRAY_SIZE(v3d_core_reg_defs); i++) { 122 const struct v3d_reg_def *def = &v3d_core_reg_defs[i]; 123 124 if (v3d->ver >= def->min_ver && v3d->ver <= def->max_ver) { 125 seq_printf(m, "core %d %s (0x%04x): 0x%08x\n", 126 core, def->name, def->reg, 127 V3D_CORE_READ(core, def->reg)); 128 } 129 } 130 131 for (i = 0; i < ARRAY_SIZE(v3d_csd_reg_defs); i++) { 132 const struct v3d_reg_def *def = &v3d_csd_reg_defs[i]; 133 134 if (v3d->ver >= def->min_ver && v3d->ver <= def->max_ver) { 135 seq_printf(m, "core %d %s (0x%04x): 0x%08x\n", 136 core, def->name, def->reg, 137 V3D_CORE_READ(core, def->reg)); 138 } 139 } 140 } 141 142 return 0; 143 } 144 145 static int v3d_v3d_debugfs_ident(struct seq_file *m, void *unused) 146 { 147 struct drm_debugfs_entry *entry = m->private; 148 struct drm_device *dev = entry->dev; 149 struct v3d_dev *v3d = to_v3d_dev(dev); 150 u32 ident0, ident1, ident2, ident3, cores; 151 int core; 152 153 ident0 = V3D_READ(V3D_HUB_IDENT0); 154 ident1 = V3D_READ(V3D_HUB_IDENT1); 155 ident2 = V3D_READ(V3D_HUB_IDENT2); 156 ident3 = V3D_READ(V3D_HUB_IDENT3); 157 cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES); 158 159 seq_printf(m, "Revision: %d.%d.%d.%d\n", 160 V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER), 161 V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV), 162 V3D_GET_FIELD(ident3, V3D_HUB_IDENT3_IPREV), 163 V3D_GET_FIELD(ident3, V3D_HUB_IDENT3_IPIDX)); 164 seq_printf(m, "MMU: %s\n", 165 str_yes_no(ident2 & V3D_HUB_IDENT2_WITH_MMU)); 166 seq_printf(m, "TFU: %s\n", 167 str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_TFU)); 168 if (v3d->ver <= V3D_GEN_42) { 169 seq_printf(m, "TSY: %s\n", 170 str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_TSY)); 171 } 172 seq_printf(m, "MSO: %s\n", 173 str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_MSO)); 174 seq_printf(m, "L3C: %s (%dkb)\n", 175 str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_L3C), 176 V3D_GET_FIELD(ident2, V3D_HUB_IDENT2_L3C_NKB)); 177 178 for (core = 0; core < cores; core++) { 179 u32 misccfg; 180 u32 nslc, ntmu, qups; 181 182 ident0 = V3D_CORE_READ(core, V3D_CTL_IDENT0); 183 ident1 = V3D_CORE_READ(core, V3D_CTL_IDENT1); 184 ident2 = V3D_CORE_READ(core, V3D_CTL_IDENT2); 185 misccfg = V3D_CORE_READ(core, V3D_CTL_MISCCFG); 186 187 nslc = V3D_GET_FIELD(ident1, V3D_IDENT1_NSLC); 188 ntmu = V3D_GET_FIELD(ident1, V3D_IDENT1_NTMU); 189 qups = V3D_GET_FIELD(ident1, V3D_IDENT1_QUPS); 190 191 seq_printf(m, "Core %d:\n", core); 192 seq_printf(m, " Revision: %d.%d\n", 193 V3D_GET_FIELD(ident0, V3D_IDENT0_VER), 194 V3D_GET_FIELD(ident1, V3D_IDENT1_REV)); 195 seq_printf(m, " Slices: %d\n", nslc); 196 seq_printf(m, " TMUs: %d\n", nslc * ntmu); 197 seq_printf(m, " QPUs: %d\n", nslc * qups); 198 seq_printf(m, " Semaphores: %d\n", 199 V3D_GET_FIELD(ident1, V3D_IDENT1_NSEM)); 200 if (v3d->ver <= V3D_GEN_42) { 201 seq_printf(m, " BCG int: %d\n", 202 (ident2 & V3D_IDENT2_BCG_INT) != 0); 203 } 204 if (v3d->ver < V3D_GEN_41) { 205 seq_printf(m, " Override TMU: %d\n", 206 (misccfg & V3D_MISCCFG_OVRTMUOUT) != 0); 207 } 208 } 209 210 return 0; 211 } 212 213 static int v3d_debugfs_bo_stats(struct seq_file *m, void *unused) 214 { 215 struct drm_debugfs_entry *entry = m->private; 216 struct drm_device *dev = entry->dev; 217 struct v3d_dev *v3d = to_v3d_dev(dev); 218 219 mutex_lock(&v3d->bo_lock); 220 seq_printf(m, "allocated bos: %d\n", 221 v3d->bo_stats.num_allocated); 222 seq_printf(m, "allocated bo size (kb): %ld\n", 223 (long)v3d->bo_stats.pages_allocated << (V3D_MMU_PAGE_SHIFT - 10)); 224 mutex_unlock(&v3d->bo_lock); 225 226 return 0; 227 } 228 229 static int v3d_measure_clock(struct seq_file *m, void *unused) 230 { 231 struct drm_debugfs_entry *entry = m->private; 232 struct drm_device *dev = entry->dev; 233 struct v3d_dev *v3d = to_v3d_dev(dev); 234 uint32_t cycles; 235 int core = 0; 236 int measure_ms = 1000; 237 238 if (v3d->ver >= V3D_GEN_41) { 239 int cycle_count_reg = V3D_PCTR_CYCLE_COUNT(v3d->ver); 240 V3D_CORE_WRITE(core, V3D_V4_PCTR_0_SRC_0_3, 241 V3D_SET_FIELD_VER(cycle_count_reg, 242 V3D_PCTR_S0, v3d->ver)); 243 V3D_CORE_WRITE(core, V3D_V4_PCTR_0_CLR, 1); 244 V3D_CORE_WRITE(core, V3D_V4_PCTR_0_EN, 1); 245 } else { 246 V3D_CORE_WRITE(core, V3D_V3_PCTR_0_PCTRS0, 247 V3D_PCTR_CYCLE_COUNT(v3d->ver)); 248 V3D_CORE_WRITE(core, V3D_V3_PCTR_0_CLR, 1); 249 V3D_CORE_WRITE(core, V3D_V3_PCTR_0_EN, 250 V3D_V3_PCTR_0_EN_ENABLE | 251 1); 252 } 253 msleep(measure_ms); 254 cycles = V3D_CORE_READ(core, V3D_PCTR_0_PCTR0); 255 256 seq_printf(m, "cycles: %d (%d.%d Mhz)\n", 257 cycles, 258 cycles / (measure_ms * 1000), 259 (cycles / (measure_ms * 100)) % 10); 260 261 return 0; 262 } 263 264 static int v3d_debugfs_mm(struct seq_file *m, void *unused) 265 { 266 struct drm_printer p = drm_seq_file_printer(m); 267 struct drm_debugfs_entry *entry = m->private; 268 struct drm_device *dev = entry->dev; 269 struct v3d_dev *v3d = to_v3d_dev(dev); 270 271 spin_lock(&v3d->mm_lock); 272 drm_mm_print(&v3d->mm, &p); 273 spin_unlock(&v3d->mm_lock); 274 275 return 0; 276 } 277 278 static const struct drm_debugfs_info v3d_debugfs_list[] = { 279 {"v3d_ident", v3d_v3d_debugfs_ident, 0}, 280 {"v3d_regs", v3d_v3d_debugfs_regs, 0}, 281 {"measure_clock", v3d_measure_clock, 0}, 282 {"bo_stats", v3d_debugfs_bo_stats, 0}, 283 {"v3d_mm", v3d_debugfs_mm, 0}, 284 }; 285 286 void 287 v3d_debugfs_init(struct drm_minor *minor) 288 { 289 drm_debugfs_add_files(minor->dev, v3d_debugfs_list, ARRAY_SIZE(v3d_debugfs_list)); 290 } 291