1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2014-2018 Broadcom */ 3 4 #include <linux/circ_buf.h> 5 #include <linux/ctype.h> 6 #include <linux/debugfs.h> 7 #include <linux/seq_file.h> 8 #include <linux/string_helpers.h> 9 10 #include <drm/drm_debugfs.h> 11 #include <drm/drm_print.h> 12 13 #include "v3d_drv.h" 14 #include "v3d_regs.h" 15 16 #define REGDEF(min_ver, max_ver, reg) { min_ver, max_ver, reg, #reg } 17 struct v3d_reg_def { 18 u32 min_ver; 19 u32 max_ver; 20 u32 reg; 21 const char *name; 22 }; 23 24 static const struct v3d_reg_def v3d_hub_reg_defs[] = { 25 REGDEF(V3D_GEN_33, V3D_GEN_42, V3D_HUB_AXICFG), 26 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_UIFCFG), 27 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_IDENT0), 28 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_IDENT1), 29 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_IDENT2), 30 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_IDENT3), 31 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_INT_STS), 32 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_INT_MSK_STS), 33 34 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_MMU_CTL), 35 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_MMU_VIO_ADDR), 36 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_MMU_VIO_ID), 37 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_MMU_DEBUG_INFO), 38 39 REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_GMP_STATUS(71)), 40 REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_GMP_CFG(71)), 41 REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_GMP_VIO_ADDR(71)), 42 }; 43 44 static const struct v3d_reg_def v3d_gca_reg_defs[] = { 45 REGDEF(V3D_GEN_33, V3D_GEN_33, V3D_GCA_SAFE_SHUTDOWN), 46 REGDEF(V3D_GEN_33, V3D_GEN_33, V3D_GCA_SAFE_SHUTDOWN_ACK), 47 }; 48 49 static const struct v3d_reg_def v3d_core_reg_defs[] = { 50 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_IDENT0), 51 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_IDENT1), 52 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_IDENT2), 53 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_MISCCFG), 54 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_INT_STS), 55 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_INT_MSK_STS), 56 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT0CS), 57 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT0CA), 58 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT0EA), 59 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT1CS), 60 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT1CA), 61 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT1EA), 62 63 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_PTB_BPCA), 64 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_PTB_BPCS), 65 66 REGDEF(V3D_GEN_33, V3D_GEN_42, V3D_GMP_STATUS(33)), 67 REGDEF(V3D_GEN_33, V3D_GEN_42, V3D_GMP_CFG(33)), 68 REGDEF(V3D_GEN_33, V3D_GEN_42, V3D_GMP_VIO_ADDR(33)), 69 70 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_ERR_FDBGO), 71 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_ERR_FDBGB), 72 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_ERR_FDBGS), 73 REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_ERR_STAT), 74 }; 75 76 static const struct v3d_reg_def v3d_csd_reg_defs[] = { 77 REGDEF(V3D_GEN_41, V3D_GEN_71, V3D_CSD_STATUS), 78 REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG0(41)), 79 REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG1(41)), 80 REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG2(41)), 81 REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG3(41)), 82 REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG4(41)), 83 REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG5(41)), 84 REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG6(41)), 85 REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG0(71)), 86 REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG1(71)), 87 REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG2(71)), 88 REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG3(71)), 89 REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG4(71)), 90 REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG5(71)), 91 REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG6(71)), 92 REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_V7_CSD_CURRENT_CFG7), 93 }; 94 95 static int v3d_v3d_debugfs_regs(struct seq_file *m, void *unused) 96 { 97 struct drm_debugfs_entry *entry = m->private; 98 struct drm_device *dev = entry->dev; 99 struct v3d_dev *v3d = to_v3d_dev(dev); 100 int i, core, ret; 101 102 ret = v3d_pm_runtime_get(v3d); 103 if (ret) 104 return ret; 105 106 for (i = 0; i < ARRAY_SIZE(v3d_hub_reg_defs); i++) { 107 const struct v3d_reg_def *def = &v3d_hub_reg_defs[i]; 108 109 if (v3d->ver >= def->min_ver && v3d->ver <= def->max_ver) { 110 seq_printf(m, "%s (0x%04x): 0x%08x\n", 111 def->name, def->reg, V3D_READ(def->reg)); 112 } 113 } 114 115 for (i = 0; i < ARRAY_SIZE(v3d_gca_reg_defs); i++) { 116 const struct v3d_reg_def *def = &v3d_gca_reg_defs[i]; 117 118 if (v3d->ver >= def->min_ver && v3d->ver <= def->max_ver) { 119 seq_printf(m, "%s (0x%04x): 0x%08x\n", 120 def->name, def->reg, V3D_GCA_READ(def->reg)); 121 } 122 } 123 124 for (core = 0; core < v3d->cores; core++) { 125 for (i = 0; i < ARRAY_SIZE(v3d_core_reg_defs); i++) { 126 const struct v3d_reg_def *def = &v3d_core_reg_defs[i]; 127 128 if (v3d->ver >= def->min_ver && v3d->ver <= def->max_ver) { 129 seq_printf(m, "core %d %s (0x%04x): 0x%08x\n", 130 core, def->name, def->reg, 131 V3D_CORE_READ(core, def->reg)); 132 } 133 } 134 135 for (i = 0; i < ARRAY_SIZE(v3d_csd_reg_defs); i++) { 136 const struct v3d_reg_def *def = &v3d_csd_reg_defs[i]; 137 138 if (v3d->ver >= def->min_ver && v3d->ver <= def->max_ver) { 139 seq_printf(m, "core %d %s (0x%04x): 0x%08x\n", 140 core, def->name, def->reg, 141 V3D_CORE_READ(core, def->reg)); 142 } 143 } 144 } 145 146 v3d_pm_runtime_put(v3d); 147 148 return 0; 149 } 150 151 static int v3d_v3d_debugfs_ident(struct seq_file *m, void *unused) 152 { 153 struct drm_debugfs_entry *entry = m->private; 154 struct drm_device *dev = entry->dev; 155 struct v3d_dev *v3d = to_v3d_dev(dev); 156 u32 ident0, ident1, ident2, ident3, cores; 157 int core, ret; 158 159 ret = v3d_pm_runtime_get(v3d); 160 if (ret) 161 return ret; 162 163 ident0 = V3D_READ(V3D_HUB_IDENT0); 164 ident1 = V3D_READ(V3D_HUB_IDENT1); 165 ident2 = V3D_READ(V3D_HUB_IDENT2); 166 ident3 = V3D_READ(V3D_HUB_IDENT3); 167 cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES); 168 169 seq_printf(m, "Revision: %d.%d.%d.%d\n", 170 V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER), 171 V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV), 172 V3D_GET_FIELD(ident3, V3D_HUB_IDENT3_IPREV), 173 V3D_GET_FIELD(ident3, V3D_HUB_IDENT3_IPIDX)); 174 seq_printf(m, "MMU: %s\n", 175 str_yes_no(ident2 & V3D_HUB_IDENT2_WITH_MMU)); 176 seq_printf(m, "TFU: %s\n", 177 str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_TFU)); 178 if (v3d->ver <= V3D_GEN_42) { 179 seq_printf(m, "TSY: %s\n", 180 str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_TSY)); 181 } 182 seq_printf(m, "MSO: %s\n", 183 str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_MSO)); 184 seq_printf(m, "L3C: %s (%dkb)\n", 185 str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_L3C), 186 V3D_GET_FIELD(ident2, V3D_HUB_IDENT2_L3C_NKB)); 187 188 for (core = 0; core < cores; core++) { 189 u32 misccfg; 190 u32 nslc, ntmu, qups; 191 192 ident0 = V3D_CORE_READ(core, V3D_CTL_IDENT0); 193 ident1 = V3D_CORE_READ(core, V3D_CTL_IDENT1); 194 ident2 = V3D_CORE_READ(core, V3D_CTL_IDENT2); 195 misccfg = V3D_CORE_READ(core, V3D_CTL_MISCCFG); 196 197 nslc = V3D_GET_FIELD(ident1, V3D_IDENT1_NSLC); 198 ntmu = V3D_GET_FIELD(ident1, V3D_IDENT1_NTMU); 199 qups = V3D_GET_FIELD(ident1, V3D_IDENT1_QUPS); 200 201 seq_printf(m, "Core %d:\n", core); 202 seq_printf(m, " Revision: %d.%d\n", 203 V3D_GET_FIELD(ident0, V3D_IDENT0_VER), 204 V3D_GET_FIELD(ident1, V3D_IDENT1_REV)); 205 seq_printf(m, " Slices: %d\n", nslc); 206 seq_printf(m, " TMUs: %d\n", nslc * ntmu); 207 seq_printf(m, " QPUs: %d\n", nslc * qups); 208 seq_printf(m, " Semaphores: %d\n", 209 V3D_GET_FIELD(ident1, V3D_IDENT1_NSEM)); 210 if (v3d->ver <= V3D_GEN_42) { 211 seq_printf(m, " BCG int: %d\n", 212 (ident2 & V3D_IDENT2_BCG_INT) != 0); 213 } 214 if (v3d->ver < V3D_GEN_41) { 215 seq_printf(m, " Override TMU: %d\n", 216 (misccfg & V3D_MISCCFG_OVRTMUOUT) != 0); 217 } 218 } 219 220 v3d_pm_runtime_put(v3d); 221 222 return 0; 223 } 224 225 static int v3d_debugfs_bo_stats(struct seq_file *m, void *unused) 226 { 227 struct drm_debugfs_entry *entry = m->private; 228 struct drm_device *dev = entry->dev; 229 struct v3d_dev *v3d = to_v3d_dev(dev); 230 231 mutex_lock(&v3d->bo_lock); 232 seq_printf(m, "allocated bos: %d\n", 233 v3d->bo_stats.num_allocated); 234 seq_printf(m, "allocated bo size (kb): %ld\n", 235 (long)v3d->bo_stats.pages_allocated << (V3D_MMU_PAGE_SHIFT - 10)); 236 mutex_unlock(&v3d->bo_lock); 237 238 return 0; 239 } 240 241 static int v3d_measure_clock(struct seq_file *m, void *unused) 242 { 243 struct drm_debugfs_entry *entry = m->private; 244 struct drm_device *dev = entry->dev; 245 struct v3d_dev *v3d = to_v3d_dev(dev); 246 uint32_t cycles; 247 int core = 0; 248 int measure_ms = 1000; 249 int ret; 250 251 ret = v3d_pm_runtime_get(v3d); 252 if (ret) 253 return ret; 254 255 if (v3d->ver >= V3D_GEN_41) { 256 int cycle_count_reg = V3D_PCTR_CYCLE_COUNT(v3d->ver); 257 V3D_CORE_WRITE(core, V3D_V4_PCTR_0_SRC_0_3, 258 V3D_SET_FIELD_VER(cycle_count_reg, 259 V3D_PCTR_S0, v3d->ver)); 260 V3D_CORE_WRITE(core, V3D_V4_PCTR_0_CLR, 1); 261 V3D_CORE_WRITE(core, V3D_V4_PCTR_0_EN, 1); 262 } else { 263 V3D_CORE_WRITE(core, V3D_V3_PCTR_0_PCTRS0, 264 V3D_PCTR_CYCLE_COUNT(v3d->ver)); 265 V3D_CORE_WRITE(core, V3D_V3_PCTR_0_CLR, 1); 266 V3D_CORE_WRITE(core, V3D_V3_PCTR_0_EN, 267 V3D_V3_PCTR_0_EN_ENABLE | 268 1); 269 } 270 msleep(measure_ms); 271 cycles = V3D_CORE_READ(core, V3D_PCTR_0_PCTR0); 272 273 v3d_pm_runtime_put(v3d); 274 275 seq_printf(m, "cycles: %d (%d.%d Mhz)\n", 276 cycles, 277 cycles / (measure_ms * 1000), 278 (cycles / (measure_ms * 100)) % 10); 279 280 return 0; 281 } 282 283 static int v3d_debugfs_mm(struct seq_file *m, void *unused) 284 { 285 struct drm_printer p = drm_seq_file_printer(m); 286 struct drm_debugfs_entry *entry = m->private; 287 struct drm_device *dev = entry->dev; 288 struct v3d_dev *v3d = to_v3d_dev(dev); 289 290 spin_lock(&v3d->mm_lock); 291 drm_mm_print(&v3d->mm, &p); 292 spin_unlock(&v3d->mm_lock); 293 294 return 0; 295 } 296 297 static const struct drm_debugfs_info v3d_debugfs_list[] = { 298 {"v3d_ident", v3d_v3d_debugfs_ident, 0}, 299 {"v3d_regs", v3d_v3d_debugfs_regs, 0}, 300 {"measure_clock", v3d_measure_clock, 0}, 301 {"bo_stats", v3d_debugfs_bo_stats, 0}, 302 {"v3d_mm", v3d_debugfs_mm, 0}, 303 }; 304 305 void 306 v3d_debugfs_init(struct drm_minor *minor) 307 { 308 drm_debugfs_add_files(minor->dev, v3d_debugfs_list, ARRAY_SIZE(v3d_debugfs_list)); 309 } 310