1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012 Red Hat 4 * 5 * based in parts on udlfb.c: 6 * Copyright (C) 2009 Roberto De Ioris <roberto@unbit.it> 7 * Copyright (C) 2009 Jaya Kumar <jayakumar.lkml@gmail.com> 8 * Copyright (C) 2009 Bernie Thompson <bernie@plugable.com> 9 */ 10 11 #include <linux/bitfield.h> 12 13 #include <drm/drm_atomic.h> 14 #include <drm/drm_atomic_helper.h> 15 #include <drm/drm_crtc_helper.h> 16 #include <drm/drm_damage_helper.h> 17 #include <drm/drm_drv.h> 18 #include <drm/drm_edid.h> 19 #include <drm/drm_fourcc.h> 20 #include <drm/drm_gem_atomic_helper.h> 21 #include <drm/drm_gem_framebuffer_helper.h> 22 #include <drm/drm_gem_shmem_helper.h> 23 #include <drm/drm_modeset_helper_vtables.h> 24 #include <drm/drm_probe_helper.h> 25 #include <drm/drm_vblank.h> 26 27 #include "udl_drv.h" 28 #include "udl_edid.h" 29 #include "udl_proto.h" 30 31 /* 32 * All DisplayLink bulk operations start with 0xaf (UDL_MSG_BULK), followed by 33 * a specific command code. All operations are written to a command buffer, which 34 * the driver sends to the device. 35 */ 36 static char *udl_set_register(char *buf, u8 reg, u8 val) 37 { 38 *buf++ = UDL_MSG_BULK; 39 *buf++ = UDL_CMD_WRITEREG; 40 *buf++ = reg; 41 *buf++ = val; 42 43 return buf; 44 } 45 46 static char *udl_vidreg_lock(char *buf) 47 { 48 return udl_set_register(buf, UDL_REG_VIDREG, UDL_VIDREG_LOCK); 49 } 50 51 static char *udl_vidreg_unlock(char *buf) 52 { 53 return udl_set_register(buf, UDL_REG_VIDREG, UDL_VIDREG_UNLOCK); 54 } 55 56 static char *udl_set_blank_mode(char *buf, u8 mode) 57 { 58 return udl_set_register(buf, UDL_REG_BLANKMODE, mode); 59 } 60 61 static char *udl_set_color_depth(char *buf, u8 selection) 62 { 63 return udl_set_register(buf, UDL_REG_COLORDEPTH, selection); 64 } 65 66 static char *udl_set_base16bpp(char *buf, u32 base) 67 { 68 /* the base pointer is 24 bits wide, 0x20 is hi byte. */ 69 u8 reg20 = FIELD_GET(UDL_BASE_ADDR2_MASK, base); 70 u8 reg21 = FIELD_GET(UDL_BASE_ADDR1_MASK, base); 71 u8 reg22 = FIELD_GET(UDL_BASE_ADDR0_MASK, base); 72 73 buf = udl_set_register(buf, UDL_REG_BASE16BPP_ADDR2, reg20); 74 buf = udl_set_register(buf, UDL_REG_BASE16BPP_ADDR1, reg21); 75 buf = udl_set_register(buf, UDL_REG_BASE16BPP_ADDR0, reg22); 76 77 return buf; 78 } 79 80 /* 81 * DisplayLink HW has separate 16bpp and 8bpp framebuffers. 82 * In 24bpp modes, the low 323 RGB bits go in the 8bpp framebuffer 83 */ 84 static char *udl_set_base8bpp(char *buf, u32 base) 85 { 86 /* the base pointer is 24 bits wide, 0x26 is hi byte. */ 87 u8 reg26 = FIELD_GET(UDL_BASE_ADDR2_MASK, base); 88 u8 reg27 = FIELD_GET(UDL_BASE_ADDR1_MASK, base); 89 u8 reg28 = FIELD_GET(UDL_BASE_ADDR0_MASK, base); 90 91 buf = udl_set_register(buf, UDL_REG_BASE8BPP_ADDR2, reg26); 92 buf = udl_set_register(buf, UDL_REG_BASE8BPP_ADDR1, reg27); 93 buf = udl_set_register(buf, UDL_REG_BASE8BPP_ADDR0, reg28); 94 95 return buf; 96 } 97 98 static char *udl_set_register_16(char *wrptr, u8 reg, u16 value) 99 { 100 wrptr = udl_set_register(wrptr, reg, value >> 8); 101 return udl_set_register(wrptr, reg+1, value); 102 } 103 104 /* 105 * This is kind of weird because the controller takes some 106 * register values in a different byte order than other registers. 107 */ 108 static char *udl_set_register_16be(char *wrptr, u8 reg, u16 value) 109 { 110 wrptr = udl_set_register(wrptr, reg, value); 111 return udl_set_register(wrptr, reg+1, value >> 8); 112 } 113 114 /* 115 * LFSR is linear feedback shift register. The reason we have this is 116 * because the display controller needs to minimize the clock depth of 117 * various counters used in the display path. So this code reverses the 118 * provided value into the lfsr16 value by counting backwards to get 119 * the value that needs to be set in the hardware comparator to get the 120 * same actual count. This makes sense once you read above a couple of 121 * times and think about it from a hardware perspective. 122 */ 123 static u16 udl_lfsr16(u16 actual_count) 124 { 125 u32 lv = 0xFFFF; /* This is the lfsr value that the hw starts with */ 126 127 while (actual_count--) { 128 lv = ((lv << 1) | 129 (((lv >> 15) ^ (lv >> 4) ^ (lv >> 2) ^ (lv >> 1)) & 1)) 130 & 0xFFFF; 131 } 132 133 return (u16) lv; 134 } 135 136 /* 137 * This does LFSR conversion on the value that is to be written. 138 * See LFSR explanation above for more detail. 139 */ 140 static char *udl_set_register_lfsr16(char *wrptr, u8 reg, u16 value) 141 { 142 return udl_set_register_16(wrptr, reg, udl_lfsr16(value)); 143 } 144 145 /* 146 * Takes a DRM display mode and converts it into the DisplayLink 147 * equivalent register commands. 148 */ 149 static char *udl_set_display_mode(char *buf, struct drm_display_mode *mode) 150 { 151 u16 reg01 = mode->crtc_htotal - mode->crtc_hsync_start; 152 u16 reg03 = reg01 + mode->crtc_hdisplay; 153 u16 reg05 = mode->crtc_vtotal - mode->crtc_vsync_start; 154 u16 reg07 = reg05 + mode->crtc_vdisplay; 155 u16 reg09 = mode->crtc_htotal - 1; 156 u16 reg0b = 1; /* libdlo hardcodes hsync start to 1 */ 157 u16 reg0d = mode->crtc_hsync_end - mode->crtc_hsync_start + 1; 158 u16 reg0f = mode->hdisplay; 159 u16 reg11 = mode->crtc_vtotal; 160 u16 reg13 = 0; /* libdlo hardcodes vsync start to 0 */ 161 u16 reg15 = mode->crtc_vsync_end - mode->crtc_vsync_start; 162 u16 reg17 = mode->crtc_vdisplay; 163 u16 reg1b = mode->clock / 5; 164 165 buf = udl_set_register_lfsr16(buf, UDL_REG_XDISPLAYSTART, reg01); 166 buf = udl_set_register_lfsr16(buf, UDL_REG_XDISPLAYEND, reg03); 167 buf = udl_set_register_lfsr16(buf, UDL_REG_YDISPLAYSTART, reg05); 168 buf = udl_set_register_lfsr16(buf, UDL_REG_YDISPLAYEND, reg07); 169 buf = udl_set_register_lfsr16(buf, UDL_REG_XENDCOUNT, reg09); 170 buf = udl_set_register_lfsr16(buf, UDL_REG_HSYNCSTART, reg0b); 171 buf = udl_set_register_lfsr16(buf, UDL_REG_HSYNCEND, reg0d); 172 buf = udl_set_register_16(buf, UDL_REG_HPIXELS, reg0f); 173 buf = udl_set_register_lfsr16(buf, UDL_REG_YENDCOUNT, reg11); 174 buf = udl_set_register_lfsr16(buf, UDL_REG_VSYNCSTART, reg13); 175 buf = udl_set_register_lfsr16(buf, UDL_REG_VSYNCEND, reg15); 176 buf = udl_set_register_16(buf, UDL_REG_VPIXELS, reg17); 177 buf = udl_set_register_16be(buf, UDL_REG_PIXELCLOCK5KHZ, reg1b); 178 179 return buf; 180 } 181 182 static char *udl_dummy_render(char *wrptr) 183 { 184 *wrptr++ = UDL_MSG_BULK; 185 *wrptr++ = UDL_CMD_WRITECOPY16; 186 *wrptr++ = 0x00; /* from addr */ 187 *wrptr++ = 0x00; 188 *wrptr++ = 0x00; 189 *wrptr++ = 0x01; /* one pixel */ 190 *wrptr++ = 0x00; /* to address */ 191 *wrptr++ = 0x00; 192 *wrptr++ = 0x00; 193 return wrptr; 194 } 195 196 static long udl_log_cpp(unsigned int cpp) 197 { 198 if (WARN_ON(!is_power_of_2(cpp))) 199 return -EINVAL; 200 return __ffs(cpp); 201 } 202 203 static int udl_handle_damage(struct drm_framebuffer *fb, 204 const struct iosys_map *map, 205 const struct drm_rect *clip) 206 { 207 struct drm_device *dev = fb->dev; 208 struct udl_device *udl = to_udl(dev); 209 void *vaddr = map->vaddr; /* TODO: Use mapping abstraction properly */ 210 int i, ret; 211 char *cmd; 212 struct urb *urb; 213 int log_bpp; 214 215 ret = udl_log_cpp(fb->format->cpp[0]); 216 if (ret < 0) 217 return ret; 218 log_bpp = ret; 219 220 urb = udl_get_urb(udl); 221 if (!urb) 222 return -ENOMEM; 223 cmd = urb->transfer_buffer; 224 225 for (i = clip->y1; i < clip->y2; i++) { 226 const int line_offset = fb->pitches[0] * i; 227 const int byte_offset = line_offset + (clip->x1 << log_bpp); 228 const int dev_byte_offset = (fb->width * i + clip->x1) << log_bpp; 229 const int byte_width = drm_rect_width(clip) << log_bpp; 230 ret = udl_render_hline(udl, log_bpp, &urb, (char *)vaddr, 231 &cmd, byte_offset, dev_byte_offset, 232 byte_width); 233 if (ret) 234 return ret; 235 } 236 237 if (cmd > (char *)urb->transfer_buffer) { 238 /* Send partial buffer remaining before exiting */ 239 int len; 240 if (cmd < (char *)urb->transfer_buffer + urb->transfer_buffer_length) 241 *cmd++ = UDL_MSG_BULK; 242 len = cmd - (char *)urb->transfer_buffer; 243 ret = udl_submit_urb(udl, urb, len); 244 } else { 245 udl_urb_completion(urb); 246 } 247 248 return 0; 249 } 250 251 /* 252 * Primary plane 253 */ 254 255 static const uint32_t udl_primary_plane_formats[] = { 256 DRM_FORMAT_RGB565, 257 DRM_FORMAT_XRGB8888, 258 }; 259 260 static const uint64_t udl_primary_plane_fmtmods[] = { 261 DRM_FORMAT_MOD_LINEAR, 262 DRM_FORMAT_MOD_INVALID 263 }; 264 265 static int udl_primary_plane_helper_atomic_check(struct drm_plane *plane, 266 struct drm_atomic_state *state) 267 { 268 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); 269 struct drm_crtc *new_crtc = new_plane_state->crtc; 270 struct drm_crtc_state *new_crtc_state = NULL; 271 272 if (new_crtc) 273 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc); 274 275 return drm_atomic_helper_check_plane_state(new_plane_state, new_crtc_state, 276 DRM_PLANE_NO_SCALING, 277 DRM_PLANE_NO_SCALING, 278 false, false); 279 } 280 281 static void udl_primary_plane_helper_atomic_update(struct drm_plane *plane, 282 struct drm_atomic_state *state) 283 { 284 struct drm_device *dev = plane->dev; 285 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); 286 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state); 287 struct drm_framebuffer *fb = plane_state->fb; 288 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane); 289 struct drm_atomic_helper_damage_iter iter; 290 struct drm_rect damage; 291 int ret, idx; 292 293 if (!fb) 294 return; /* no framebuffer; plane is disabled */ 295 296 ret = drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE); 297 if (ret) 298 return; 299 300 if (!drm_dev_enter(dev, &idx)) 301 goto out_drm_gem_fb_end_cpu_access; 302 303 drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state); 304 drm_atomic_for_each_plane_damage(&iter, &damage) { 305 udl_handle_damage(fb, &shadow_plane_state->data[0], &damage); 306 } 307 308 drm_dev_exit(idx); 309 310 out_drm_gem_fb_end_cpu_access: 311 drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE); 312 } 313 314 static const struct drm_plane_helper_funcs udl_primary_plane_helper_funcs = { 315 DRM_GEM_SHADOW_PLANE_HELPER_FUNCS, 316 .atomic_check = udl_primary_plane_helper_atomic_check, 317 .atomic_update = udl_primary_plane_helper_atomic_update, 318 }; 319 320 static const struct drm_plane_funcs udl_primary_plane_funcs = { 321 .update_plane = drm_atomic_helper_update_plane, 322 .disable_plane = drm_atomic_helper_disable_plane, 323 .destroy = drm_plane_cleanup, 324 DRM_GEM_SHADOW_PLANE_FUNCS, 325 }; 326 327 /* 328 * CRTC 329 */ 330 331 static void udl_crtc_helper_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *state) 332 { 333 struct drm_device *dev = crtc->dev; 334 struct udl_device *udl = to_udl(dev); 335 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 336 struct drm_display_mode *mode = &crtc_state->mode; 337 struct urb *urb; 338 char *buf; 339 int idx; 340 341 if (!drm_dev_enter(dev, &idx)) 342 return; 343 344 urb = udl_get_urb(udl); 345 if (!urb) 346 goto out; 347 348 buf = (char *)urb->transfer_buffer; 349 buf = udl_vidreg_lock(buf); 350 buf = udl_set_color_depth(buf, UDL_COLORDEPTH_16BPP); 351 /* set base for 16bpp segment to 0 */ 352 buf = udl_set_base16bpp(buf, 0); 353 /* set base for 8bpp segment to end of fb */ 354 buf = udl_set_base8bpp(buf, 2 * mode->vdisplay * mode->hdisplay); 355 buf = udl_set_display_mode(buf, mode); 356 buf = udl_set_blank_mode(buf, UDL_BLANKMODE_ON); 357 buf = udl_vidreg_unlock(buf); 358 buf = udl_dummy_render(buf); 359 360 udl_submit_urb(udl, urb, buf - (char *)urb->transfer_buffer); 361 362 out: 363 drm_dev_exit(idx); 364 } 365 366 static void udl_crtc_helper_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *state) 367 { 368 struct drm_device *dev = crtc->dev; 369 struct udl_device *udl = to_udl(dev); 370 struct urb *urb; 371 char *buf; 372 int idx; 373 374 if (!drm_dev_enter(dev, &idx)) 375 return; 376 377 urb = udl_get_urb(udl); 378 if (!urb) 379 goto out; 380 381 buf = (char *)urb->transfer_buffer; 382 buf = udl_vidreg_lock(buf); 383 buf = udl_set_blank_mode(buf, UDL_BLANKMODE_POWERDOWN); 384 buf = udl_vidreg_unlock(buf); 385 buf = udl_dummy_render(buf); 386 387 udl_submit_urb(udl, urb, buf - (char *)urb->transfer_buffer); 388 389 out: 390 drm_dev_exit(idx); 391 } 392 393 static const struct drm_crtc_helper_funcs udl_crtc_helper_funcs = { 394 .atomic_check = drm_crtc_helper_atomic_check, 395 .atomic_enable = udl_crtc_helper_atomic_enable, 396 .atomic_disable = udl_crtc_helper_atomic_disable, 397 }; 398 399 static const struct drm_crtc_funcs udl_crtc_funcs = { 400 .reset = drm_atomic_helper_crtc_reset, 401 .destroy = drm_crtc_cleanup, 402 .set_config = drm_atomic_helper_set_config, 403 .page_flip = drm_atomic_helper_page_flip, 404 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 405 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 406 }; 407 408 /* 409 * Encoder 410 */ 411 412 static const struct drm_encoder_funcs udl_encoder_funcs = { 413 .destroy = drm_encoder_cleanup, 414 }; 415 416 /* 417 * Connector 418 */ 419 420 static int udl_connector_helper_get_modes(struct drm_connector *connector) 421 { 422 const struct drm_edid *drm_edid; 423 int count; 424 425 drm_edid = udl_edid_read(connector); 426 drm_edid_connector_update(connector, drm_edid); 427 count = drm_edid_connector_add_modes(connector); 428 drm_edid_free(drm_edid); 429 430 return count; 431 } 432 433 static int udl_connector_helper_detect_ctx(struct drm_connector *connector, 434 struct drm_modeset_acquire_ctx *ctx, 435 bool force) 436 { 437 struct udl_device *udl = to_udl(connector->dev); 438 439 if (udl_probe_edid(udl)) 440 return connector_status_connected; 441 442 return connector_status_disconnected; 443 } 444 445 static const struct drm_connector_helper_funcs udl_connector_helper_funcs = { 446 .get_modes = udl_connector_helper_get_modes, 447 .detect_ctx = udl_connector_helper_detect_ctx, 448 }; 449 450 static const struct drm_connector_funcs udl_connector_funcs = { 451 .reset = drm_atomic_helper_connector_reset, 452 .fill_modes = drm_helper_probe_single_connector_modes, 453 .destroy = drm_connector_cleanup, 454 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 455 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 456 }; 457 458 /* 459 * Modesetting 460 */ 461 462 static enum drm_mode_status udl_mode_config_mode_valid(struct drm_device *dev, 463 const struct drm_display_mode *mode) 464 { 465 struct udl_device *udl = to_udl(dev); 466 467 if (udl->sku_pixel_limit) { 468 if (mode->vdisplay * mode->hdisplay > udl->sku_pixel_limit) 469 return MODE_MEM; 470 } 471 472 return MODE_OK; 473 } 474 475 static const struct drm_mode_config_funcs udl_mode_config_funcs = { 476 .fb_create = drm_gem_fb_create_with_dirty, 477 .mode_valid = udl_mode_config_mode_valid, 478 .atomic_check = drm_atomic_helper_check, 479 .atomic_commit = drm_atomic_helper_commit, 480 }; 481 482 int udl_modeset_init(struct udl_device *udl) 483 { 484 struct drm_device *dev = &udl->drm; 485 struct drm_plane *primary_plane; 486 struct drm_crtc *crtc; 487 struct drm_encoder *encoder; 488 struct drm_connector *connector; 489 int ret; 490 491 ret = drmm_mode_config_init(dev); 492 if (ret) 493 return ret; 494 495 dev->mode_config.min_width = 640; 496 dev->mode_config.min_height = 480; 497 dev->mode_config.max_width = 2048; 498 dev->mode_config.max_height = 2048; 499 dev->mode_config.preferred_depth = 16; 500 dev->mode_config.funcs = &udl_mode_config_funcs; 501 502 primary_plane = &udl->primary_plane; 503 ret = drm_universal_plane_init(dev, primary_plane, 0, 504 &udl_primary_plane_funcs, 505 udl_primary_plane_formats, 506 ARRAY_SIZE(udl_primary_plane_formats), 507 udl_primary_plane_fmtmods, 508 DRM_PLANE_TYPE_PRIMARY, NULL); 509 if (ret) 510 return ret; 511 drm_plane_helper_add(primary_plane, &udl_primary_plane_helper_funcs); 512 drm_plane_enable_fb_damage_clips(primary_plane); 513 514 crtc = &udl->crtc; 515 ret = drm_crtc_init_with_planes(dev, crtc, primary_plane, NULL, 516 &udl_crtc_funcs, NULL); 517 if (ret) 518 return ret; 519 drm_crtc_helper_add(crtc, &udl_crtc_helper_funcs); 520 521 encoder = &udl->encoder; 522 ret = drm_encoder_init(dev, encoder, &udl_encoder_funcs, DRM_MODE_ENCODER_DAC, NULL); 523 if (ret) 524 return ret; 525 encoder->possible_crtcs = drm_crtc_mask(crtc); 526 527 connector = &udl->connector; 528 ret = drm_connector_init(dev, connector, &udl_connector_funcs, DRM_MODE_CONNECTOR_VGA); 529 if (ret) 530 return ret; 531 drm_connector_helper_add(connector, &udl_connector_helper_funcs); 532 533 connector->polled = DRM_CONNECTOR_POLL_CONNECT | 534 DRM_CONNECTOR_POLL_DISCONNECT; 535 536 ret = drm_connector_attach_encoder(connector, encoder); 537 if (ret) 538 return ret; 539 540 drm_mode_config_reset(dev); 541 drmm_kms_helper_poll_init(dev); 542 543 return 0; 544 } 545