1 // SPDX-License-Identifier: GPL-2.0 or MIT 2 3 // We don't expect that all the registers and fields will be used, even in the 4 // future. 5 // 6 // Nevertheless, it is useful to have most of them defined, like the C driver 7 // does. 8 #![allow(dead_code)] 9 10 use kernel::{ 11 bits::bit_u32, 12 device::{ 13 Bound, 14 Device, // 15 }, 16 devres::Devres, 17 io::Io, 18 prelude::*, // 19 }; 20 21 use crate::driver::IoMem; 22 23 /// Represents a register in the Register Set 24 /// 25 /// TODO: Replace this with the Nova `register!()` macro when it is available. 26 /// In particular, this will automatically give us 64bit register reads and 27 /// writes. 28 pub(crate) struct Register<const OFFSET: usize>; 29 30 impl<const OFFSET: usize> Register<OFFSET> { 31 #[inline] 32 pub(crate) fn read(&self, dev: &Device<Bound>, iomem: &Devres<IoMem>) -> Result<u32> { 33 let value = (*iomem).access(dev)?.read32(OFFSET); 34 Ok(value) 35 } 36 37 #[inline] 38 pub(crate) fn write(&self, dev: &Device<Bound>, iomem: &Devres<IoMem>, value: u32) -> Result { 39 (*iomem).access(dev)?.write32(value, OFFSET); 40 Ok(()) 41 } 42 } 43 44 pub(crate) const GPU_ID: Register<0x0> = Register; 45 pub(crate) const GPU_L2_FEATURES: Register<0x4> = Register; 46 pub(crate) const GPU_CORE_FEATURES: Register<0x8> = Register; 47 pub(crate) const GPU_CSF_ID: Register<0x1c> = Register; 48 pub(crate) const GPU_REVID: Register<0x280> = Register; 49 pub(crate) const GPU_TILER_FEATURES: Register<0xc> = Register; 50 pub(crate) const GPU_MEM_FEATURES: Register<0x10> = Register; 51 pub(crate) const GPU_MMU_FEATURES: Register<0x14> = Register; 52 pub(crate) const GPU_AS_PRESENT: Register<0x18> = Register; 53 pub(crate) const GPU_IRQ_RAWSTAT: Register<0x20> = Register; 54 55 pub(crate) const GPU_IRQ_RAWSTAT_FAULT: u32 = bit_u32(0); 56 pub(crate) const GPU_IRQ_RAWSTAT_PROTECTED_FAULT: u32 = bit_u32(1); 57 pub(crate) const GPU_IRQ_RAWSTAT_RESET_COMPLETED: u32 = bit_u32(8); 58 pub(crate) const GPU_IRQ_RAWSTAT_POWER_CHANGED_SINGLE: u32 = bit_u32(9); 59 pub(crate) const GPU_IRQ_RAWSTAT_POWER_CHANGED_ALL: u32 = bit_u32(10); 60 pub(crate) const GPU_IRQ_RAWSTAT_CLEAN_CACHES_COMPLETED: u32 = bit_u32(17); 61 pub(crate) const GPU_IRQ_RAWSTAT_DOORBELL_STATUS: u32 = bit_u32(18); 62 pub(crate) const GPU_IRQ_RAWSTAT_MCU_STATUS: u32 = bit_u32(19); 63 64 pub(crate) const GPU_IRQ_CLEAR: Register<0x24> = Register; 65 pub(crate) const GPU_IRQ_MASK: Register<0x28> = Register; 66 pub(crate) const GPU_IRQ_STAT: Register<0x2c> = Register; 67 pub(crate) const GPU_CMD: Register<0x30> = Register; 68 pub(crate) const GPU_CMD_SOFT_RESET: u32 = 1 | (1 << 8); 69 pub(crate) const GPU_CMD_HARD_RESET: u32 = 1 | (2 << 8); 70 pub(crate) const GPU_THREAD_FEATURES: Register<0xac> = Register; 71 pub(crate) const GPU_THREAD_MAX_THREADS: Register<0xa0> = Register; 72 pub(crate) const GPU_THREAD_MAX_WORKGROUP_SIZE: Register<0xa4> = Register; 73 pub(crate) const GPU_THREAD_MAX_BARRIER_SIZE: Register<0xa8> = Register; 74 pub(crate) const GPU_TEXTURE_FEATURES0: Register<0xb0> = Register; 75 pub(crate) const GPU_SHADER_PRESENT_LO: Register<0x100> = Register; 76 pub(crate) const GPU_SHADER_PRESENT_HI: Register<0x104> = Register; 77 pub(crate) const GPU_TILER_PRESENT_LO: Register<0x110> = Register; 78 pub(crate) const GPU_TILER_PRESENT_HI: Register<0x114> = Register; 79 pub(crate) const GPU_L2_PRESENT_LO: Register<0x120> = Register; 80 pub(crate) const GPU_L2_PRESENT_HI: Register<0x124> = Register; 81 pub(crate) const L2_READY_LO: Register<0x160> = Register; 82 pub(crate) const L2_READY_HI: Register<0x164> = Register; 83 pub(crate) const L2_PWRON_LO: Register<0x1a0> = Register; 84 pub(crate) const L2_PWRON_HI: Register<0x1a4> = Register; 85 pub(crate) const L2_PWRTRANS_LO: Register<0x220> = Register; 86 pub(crate) const L2_PWRTRANS_HI: Register<0x204> = Register; 87 pub(crate) const L2_PWRACTIVE_LO: Register<0x260> = Register; 88 pub(crate) const L2_PWRACTIVE_HI: Register<0x264> = Register; 89 90 pub(crate) const MCU_CONTROL: Register<0x700> = Register; 91 pub(crate) const MCU_CONTROL_ENABLE: u32 = 1; 92 pub(crate) const MCU_CONTROL_AUTO: u32 = 2; 93 pub(crate) const MCU_CONTROL_DISABLE: u32 = 0; 94 95 pub(crate) const MCU_STATUS: Register<0x704> = Register; 96 pub(crate) const MCU_STATUS_DISABLED: u32 = 0; 97 pub(crate) const MCU_STATUS_ENABLED: u32 = 1; 98 pub(crate) const MCU_STATUS_HALT: u32 = 2; 99 pub(crate) const MCU_STATUS_FATAL: u32 = 3; 100 101 pub(crate) const GPU_COHERENCY_FEATURES: Register<0x300> = Register; 102 103 pub(crate) const JOB_IRQ_RAWSTAT: Register<0x1000> = Register; 104 pub(crate) const JOB_IRQ_CLEAR: Register<0x1004> = Register; 105 pub(crate) const JOB_IRQ_MASK: Register<0x1008> = Register; 106 pub(crate) const JOB_IRQ_STAT: Register<0x100c> = Register; 107 108 pub(crate) const JOB_IRQ_GLOBAL_IF: u32 = bit_u32(31); 109 110 pub(crate) const MMU_IRQ_RAWSTAT: Register<0x2000> = Register; 111 pub(crate) const MMU_IRQ_CLEAR: Register<0x2004> = Register; 112 pub(crate) const MMU_IRQ_MASK: Register<0x2008> = Register; 113 pub(crate) const MMU_IRQ_STAT: Register<0x200c> = Register; 114