1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org> 4 * Parts of this file were based on sources as follows: 5 * 6 * Copyright (C) 2006-2008 Intel Corporation 7 * Copyright (C) 2007 Amos Lee <amos_lee@storlinksemi.com> 8 * Copyright (C) 2007 Dave Airlie <airlied@linux.ie> 9 * Copyright (C) 2011 Texas Instruments 10 * Copyright (C) 2017 Eric Anholt 11 */ 12 13 #include <linux/clk.h> 14 #include <linux/dma-buf.h> 15 #include <linux/of_graph.h> 16 #include <linux/delay.h> 17 18 #include <drm/drm_fb_dma_helper.h> 19 #include <drm/drm_fourcc.h> 20 #include <drm/drm_framebuffer.h> 21 #include <drm/drm_gem_atomic_helper.h> 22 #include <drm/drm_gem_dma_helper.h> 23 #include <drm/drm_panel.h> 24 #include <drm/drm_print.h> 25 #include <drm/drm_vblank.h> 26 27 #include "tve200_drm.h" 28 29 irqreturn_t tve200_irq(int irq, void *data) 30 { 31 struct tve200_drm_dev_private *priv = data; 32 u32 stat; 33 u32 val; 34 35 stat = readl(priv->regs + TVE200_INT_STAT); 36 37 if (!stat) 38 return IRQ_NONE; 39 40 /* 41 * Vblank IRQ 42 * 43 * The hardware is a bit tilted: the line stays high after clearing 44 * the vblank IRQ, firing many more interrupts. We counter this 45 * by toggling the IRQ back and forth from firing at vblank and 46 * firing at start of active image, which works around the problem 47 * since those occur strictly in sequence, and we get two IRQs for each 48 * frame, one at start of Vblank (that we make call into the CRTC) and 49 * another one at the start of the image (that we discard). 50 */ 51 if (stat & TVE200_INT_V_STATUS) { 52 val = readl(priv->regs + TVE200_CTRL); 53 /* We have an actual start of vsync */ 54 if (!(val & TVE200_VSTSTYPE_BITS)) { 55 drm_crtc_handle_vblank(&priv->pipe.crtc); 56 /* Toggle trigger to start of active image */ 57 val |= TVE200_VSTSTYPE_VAI; 58 } else { 59 /* Toggle trigger back to start of vsync */ 60 val &= ~TVE200_VSTSTYPE_BITS; 61 } 62 writel(val, priv->regs + TVE200_CTRL); 63 } else 64 dev_err(priv->drm->dev, "stray IRQ %08x\n", stat); 65 66 /* Clear the interrupt once done */ 67 writel(stat, priv->regs + TVE200_INT_CLR); 68 69 return IRQ_HANDLED; 70 } 71 72 static int tve200_display_check(struct drm_simple_display_pipe *pipe, 73 struct drm_plane_state *pstate, 74 struct drm_crtc_state *cstate) 75 { 76 const struct drm_display_mode *mode = &cstate->mode; 77 struct drm_framebuffer *old_fb = pipe->plane.state->fb; 78 struct drm_framebuffer *fb = pstate->fb; 79 80 /* 81 * We support these specific resolutions and nothing else. 82 */ 83 if (!(mode->hdisplay == 352 && mode->vdisplay == 240) && /* SIF(525) */ 84 !(mode->hdisplay == 352 && mode->vdisplay == 288) && /* CIF(625) */ 85 !(mode->hdisplay == 640 && mode->vdisplay == 480) && /* VGA */ 86 !(mode->hdisplay == 720 && mode->vdisplay == 480) && /* D1 */ 87 !(mode->hdisplay == 720 && mode->vdisplay == 576)) { /* D1 */ 88 DRM_DEBUG_KMS("unsupported display mode (%u x %u)\n", 89 mode->hdisplay, mode->vdisplay); 90 return -EINVAL; 91 } 92 93 if (fb) { 94 u32 offset = drm_fb_dma_get_gem_addr(fb, pstate, 0); 95 96 /* FB base address must be dword aligned. */ 97 if (offset & 3) { 98 DRM_DEBUG_KMS("FB not 32-bit aligned\n"); 99 return -EINVAL; 100 } 101 102 /* 103 * There's no pitch register, the mode's hdisplay 104 * controls this. 105 */ 106 if (fb->pitches[0] != mode->hdisplay * fb->format->cpp[0]) { 107 DRM_DEBUG_KMS("can't handle pitches\n"); 108 return -EINVAL; 109 } 110 111 /* 112 * We can't change the FB format in a flicker-free 113 * manner (and only update it during CRTC enable). 114 */ 115 if (old_fb && old_fb->format != fb->format) 116 cstate->mode_changed = true; 117 } 118 119 return 0; 120 } 121 122 static void tve200_display_enable(struct drm_simple_display_pipe *pipe, 123 struct drm_crtc_state *cstate, 124 struct drm_plane_state *plane_state) 125 { 126 struct drm_crtc *crtc = &pipe->crtc; 127 struct drm_plane *plane = &pipe->plane; 128 struct drm_device *drm = crtc->dev; 129 struct tve200_drm_dev_private *priv = drm->dev_private; 130 const struct drm_display_mode *mode = &cstate->mode; 131 struct drm_framebuffer *fb = plane->state->fb; 132 struct drm_connector *connector = priv->connector; 133 u32 format = fb->format->format; 134 u32 ctrl1 = 0; 135 int retries; 136 137 clk_prepare_enable(priv->clk); 138 139 /* Reset the TVE200 and wait for it to come back online */ 140 writel(TVE200_CTRL_4_RESET, priv->regs + TVE200_CTRL_4); 141 for (retries = 0; retries < 5; retries++) { 142 usleep_range(30000, 50000); 143 if (readl(priv->regs + TVE200_CTRL_4) & TVE200_CTRL_4_RESET) 144 continue; 145 else 146 break; 147 } 148 if (retries == 5 && 149 readl(priv->regs + TVE200_CTRL_4) & TVE200_CTRL_4_RESET) { 150 dev_err(drm->dev, "can't get hardware out of reset\n"); 151 return; 152 } 153 154 /* Function 1 */ 155 ctrl1 |= TVE200_CTRL_CSMODE; 156 /* Interlace mode for CCIR656: parameterize? */ 157 ctrl1 |= TVE200_CTRL_NONINTERLACE; 158 /* 32 words per burst */ 159 ctrl1 |= TVE200_CTRL_BURST_32_WORDS; 160 /* 16 retries */ 161 ctrl1 |= TVE200_CTRL_RETRYCNT_16; 162 /* NTSC mode: parametrize? */ 163 ctrl1 |= TVE200_CTRL_NTSC; 164 165 /* Vsync IRQ at start of Vsync at first */ 166 ctrl1 |= TVE200_VSTSTYPE_VSYNC; 167 168 if (connector->display_info.bus_flags & 169 DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) 170 ctrl1 |= TVE200_CTRL_TVCLKP; 171 172 if ((mode->hdisplay == 352 && mode->vdisplay == 240) || /* SIF(525) */ 173 (mode->hdisplay == 352 && mode->vdisplay == 288)) { /* CIF(625) */ 174 ctrl1 |= TVE200_CTRL_IPRESOL_CIF; 175 dev_info(drm->dev, "CIF mode\n"); 176 } else if (mode->hdisplay == 640 && mode->vdisplay == 480) { 177 ctrl1 |= TVE200_CTRL_IPRESOL_VGA; 178 dev_info(drm->dev, "VGA mode\n"); 179 } else if ((mode->hdisplay == 720 && mode->vdisplay == 480) || 180 (mode->hdisplay == 720 && mode->vdisplay == 576)) { 181 ctrl1 |= TVE200_CTRL_IPRESOL_D1; 182 dev_info(drm->dev, "D1 mode\n"); 183 } 184 185 if (format & DRM_FORMAT_BIG_ENDIAN) { 186 ctrl1 |= TVE200_CTRL_BBBP; 187 format &= ~DRM_FORMAT_BIG_ENDIAN; 188 } 189 190 switch (format) { 191 case DRM_FORMAT_XRGB8888: 192 ctrl1 |= TVE200_IPDMOD_RGB888; 193 break; 194 case DRM_FORMAT_RGB565: 195 ctrl1 |= TVE200_IPDMOD_RGB565; 196 break; 197 case DRM_FORMAT_XRGB1555: 198 ctrl1 |= TVE200_IPDMOD_RGB555; 199 break; 200 case DRM_FORMAT_XBGR8888: 201 ctrl1 |= TVE200_IPDMOD_RGB888 | TVE200_BGR; 202 break; 203 case DRM_FORMAT_BGR565: 204 ctrl1 |= TVE200_IPDMOD_RGB565 | TVE200_BGR; 205 break; 206 case DRM_FORMAT_XBGR1555: 207 ctrl1 |= TVE200_IPDMOD_RGB555 | TVE200_BGR; 208 break; 209 case DRM_FORMAT_YUYV: 210 ctrl1 |= TVE200_IPDMOD_YUV422; 211 ctrl1 |= TVE200_CTRL_YCBCRODR_CR0Y1CB0Y0; 212 break; 213 case DRM_FORMAT_YVYU: 214 ctrl1 |= TVE200_IPDMOD_YUV422; 215 ctrl1 |= TVE200_CTRL_YCBCRODR_CB0Y1CR0Y0; 216 break; 217 case DRM_FORMAT_UYVY: 218 ctrl1 |= TVE200_IPDMOD_YUV422; 219 ctrl1 |= TVE200_CTRL_YCBCRODR_Y1CR0Y0CB0; 220 break; 221 case DRM_FORMAT_VYUY: 222 ctrl1 |= TVE200_IPDMOD_YUV422; 223 ctrl1 |= TVE200_CTRL_YCBCRODR_Y1CB0Y0CR0; 224 break; 225 case DRM_FORMAT_YUV420: 226 ctrl1 |= TVE200_CTRL_YUV420; 227 ctrl1 |= TVE200_IPDMOD_YUV420; 228 break; 229 default: 230 dev_err(drm->dev, "Unknown FB format 0x%08x\n", 231 fb->format->format); 232 break; 233 } 234 235 ctrl1 |= TVE200_TVEEN; 236 237 /* Turn it on */ 238 writel(ctrl1, priv->regs + TVE200_CTRL); 239 240 drm_crtc_vblank_on(crtc); 241 } 242 243 static void tve200_display_disable(struct drm_simple_display_pipe *pipe) 244 { 245 struct drm_crtc *crtc = &pipe->crtc; 246 struct drm_device *drm = crtc->dev; 247 struct tve200_drm_dev_private *priv = drm->dev_private; 248 249 drm_crtc_vblank_off(crtc); 250 251 /* Disable put into reset and Power Down */ 252 writel(0, priv->regs + TVE200_CTRL); 253 writel(TVE200_CTRL_4_RESET, priv->regs + TVE200_CTRL_4); 254 255 clk_disable_unprepare(priv->clk); 256 } 257 258 static void tve200_display_update(struct drm_simple_display_pipe *pipe, 259 struct drm_plane_state *old_pstate) 260 { 261 struct drm_crtc *crtc = &pipe->crtc; 262 struct drm_device *drm = crtc->dev; 263 struct tve200_drm_dev_private *priv = drm->dev_private; 264 struct drm_pending_vblank_event *event = crtc->state->event; 265 struct drm_plane *plane = &pipe->plane; 266 struct drm_plane_state *pstate = plane->state; 267 struct drm_framebuffer *fb = pstate->fb; 268 269 if (fb) { 270 /* For RGB, the Y component is used as base address */ 271 writel(drm_fb_dma_get_gem_addr(fb, pstate, 0), 272 priv->regs + TVE200_Y_FRAME_BASE_ADDR); 273 274 /* For three plane YUV we need two more addresses */ 275 if (fb->format->format == DRM_FORMAT_YUV420) { 276 writel(drm_fb_dma_get_gem_addr(fb, pstate, 1), 277 priv->regs + TVE200_U_FRAME_BASE_ADDR); 278 writel(drm_fb_dma_get_gem_addr(fb, pstate, 2), 279 priv->regs + TVE200_V_FRAME_BASE_ADDR); 280 } 281 } 282 283 if (event) { 284 crtc->state->event = NULL; 285 286 spin_lock_irq(&crtc->dev->event_lock); 287 if (crtc->state->active && drm_crtc_vblank_get(crtc) == 0) 288 drm_crtc_arm_vblank_event(crtc, event); 289 else 290 drm_crtc_send_vblank_event(crtc, event); 291 spin_unlock_irq(&crtc->dev->event_lock); 292 } 293 } 294 295 static int tve200_display_enable_vblank(struct drm_simple_display_pipe *pipe) 296 { 297 struct drm_crtc *crtc = &pipe->crtc; 298 struct drm_device *drm = crtc->dev; 299 struct tve200_drm_dev_private *priv = drm->dev_private; 300 301 /* Clear any IRQs and enable */ 302 writel(0xFF, priv->regs + TVE200_INT_CLR); 303 writel(TVE200_INT_V_STATUS, priv->regs + TVE200_INT_EN); 304 return 0; 305 } 306 307 static void tve200_display_disable_vblank(struct drm_simple_display_pipe *pipe) 308 { 309 struct drm_crtc *crtc = &pipe->crtc; 310 struct drm_device *drm = crtc->dev; 311 struct tve200_drm_dev_private *priv = drm->dev_private; 312 313 writel(0, priv->regs + TVE200_INT_EN); 314 } 315 316 static const struct drm_simple_display_pipe_funcs tve200_display_funcs = { 317 .check = tve200_display_check, 318 .enable = tve200_display_enable, 319 .disable = tve200_display_disable, 320 .update = tve200_display_update, 321 .enable_vblank = tve200_display_enable_vblank, 322 .disable_vblank = tve200_display_disable_vblank, 323 }; 324 325 int tve200_display_init(struct drm_device *drm) 326 { 327 struct tve200_drm_dev_private *priv = drm->dev_private; 328 int ret; 329 static const u32 formats[] = { 330 DRM_FORMAT_XRGB8888, 331 DRM_FORMAT_XBGR8888, 332 DRM_FORMAT_RGB565, 333 DRM_FORMAT_BGR565, 334 DRM_FORMAT_XRGB1555, 335 DRM_FORMAT_XBGR1555, 336 /* 337 * The controller actually supports any YCbCr ordering, 338 * for packed YCbCr. This just lists the orderings that 339 * DRM supports. 340 */ 341 DRM_FORMAT_YUYV, 342 DRM_FORMAT_YVYU, 343 DRM_FORMAT_UYVY, 344 DRM_FORMAT_VYUY, 345 /* This uses three planes */ 346 DRM_FORMAT_YUV420, 347 }; 348 349 ret = drm_simple_display_pipe_init(drm, &priv->pipe, 350 &tve200_display_funcs, 351 formats, ARRAY_SIZE(formats), 352 NULL, 353 priv->connector); 354 if (ret) 355 return ret; 356 357 return 0; 358 } 359