1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright 2012-2019 Red Hat 4 * 5 * This file is subject to the terms and conditions of the GNU General 6 * Public License version 2. See the file COPYING in the main 7 * directory of this archive for more details. 8 * 9 * Authors: Matthew Garrett 10 * Dave Airlie 11 * Gerd Hoffmann 12 * 13 * Portions of this code derived from cirrusfb.c: 14 * drivers/video/cirrusfb.c - driver for Cirrus Logic chipsets 15 * 16 * Copyright 1999-2001 Jeff Garzik <jgarzik@pobox.com> 17 */ 18 19 #include <linux/aperture.h> 20 #include <linux/iosys-map.h> 21 #include <linux/module.h> 22 #include <linux/pci.h> 23 24 #include <video/cirrus.h> 25 #include <video/vga.h> 26 27 #include <drm/drm_atomic.h> 28 #include <drm/drm_atomic_helper.h> 29 #include <drm/drm_atomic_state_helper.h> 30 #include <drm/drm_client_setup.h> 31 #include <drm/drm_connector.h> 32 #include <drm/drm_damage_helper.h> 33 #include <drm/drm_drv.h> 34 #include <drm/drm_edid.h> 35 #include <drm/drm_fbdev_shmem.h> 36 #include <drm/drm_file.h> 37 #include <drm/drm_format_helper.h> 38 #include <drm/drm_fourcc.h> 39 #include <drm/drm_framebuffer.h> 40 #include <drm/drm_gem_atomic_helper.h> 41 #include <drm/drm_gem_framebuffer_helper.h> 42 #include <drm/drm_gem_shmem_helper.h> 43 #include <drm/drm_ioctl.h> 44 #include <drm/drm_managed.h> 45 #include <drm/drm_modeset_helper_vtables.h> 46 #include <drm/drm_module.h> 47 #include <drm/drm_probe_helper.h> 48 49 #define DRIVER_NAME "cirrus" 50 #define DRIVER_DESC "qemu cirrus vga" 51 #define DRIVER_DATE "2019" 52 #define DRIVER_MAJOR 2 53 #define DRIVER_MINOR 0 54 55 #define CIRRUS_MAX_PITCH (0x1FF << 3) /* (4096 - 1) & ~111b bytes */ 56 #define CIRRUS_VRAM_SIZE (4 * 1024 * 1024) /* 4 MB */ 57 58 struct cirrus_device { 59 struct drm_device dev; 60 61 /* modesetting pipeline */ 62 struct drm_plane primary_plane; 63 struct drm_crtc crtc; 64 struct drm_encoder encoder; 65 struct drm_connector connector; 66 67 /* HW resources */ 68 void __iomem *vram; 69 void __iomem *mmio; 70 }; 71 72 #define to_cirrus(_dev) container_of(_dev, struct cirrus_device, dev) 73 74 struct cirrus_primary_plane_state { 75 struct drm_shadow_plane_state base; 76 77 /* HW scanout buffer */ 78 const struct drm_format_info *format; 79 unsigned int pitch; 80 }; 81 82 static inline struct cirrus_primary_plane_state * 83 to_cirrus_primary_plane_state(struct drm_plane_state *plane_state) 84 { 85 return container_of(plane_state, struct cirrus_primary_plane_state, base.base); 86 }; 87 88 /* ------------------------------------------------------------------ */ 89 /* 90 * The meat of this driver. The core passes us a mode and we have to program 91 * it. The modesetting here is the bare minimum required to satisfy the qemu 92 * emulation of this hardware, and running this against a real device is 93 * likely to result in an inadequately programmed mode. We've already had 94 * the opportunity to modify the mode, so whatever we receive here should 95 * be something that can be correctly programmed and displayed 96 */ 97 98 #define SEQ_INDEX 4 99 #define SEQ_DATA 5 100 101 static u8 rreg_seq(struct cirrus_device *cirrus, u8 reg) 102 { 103 iowrite8(reg, cirrus->mmio + SEQ_INDEX); 104 return ioread8(cirrus->mmio + SEQ_DATA); 105 } 106 107 static void wreg_seq(struct cirrus_device *cirrus, u8 reg, u8 val) 108 { 109 iowrite8(reg, cirrus->mmio + SEQ_INDEX); 110 iowrite8(val, cirrus->mmio + SEQ_DATA); 111 } 112 113 #define CRT_INDEX 0x14 114 #define CRT_DATA 0x15 115 116 static u8 rreg_crt(struct cirrus_device *cirrus, u8 reg) 117 { 118 iowrite8(reg, cirrus->mmio + CRT_INDEX); 119 return ioread8(cirrus->mmio + CRT_DATA); 120 } 121 122 static void wreg_crt(struct cirrus_device *cirrus, u8 reg, u8 val) 123 { 124 iowrite8(reg, cirrus->mmio + CRT_INDEX); 125 iowrite8(val, cirrus->mmio + CRT_DATA); 126 } 127 128 #define GFX_INDEX 0xe 129 #define GFX_DATA 0xf 130 131 static void wreg_gfx(struct cirrus_device *cirrus, u8 reg, u8 val) 132 { 133 iowrite8(reg, cirrus->mmio + GFX_INDEX); 134 iowrite8(val, cirrus->mmio + GFX_DATA); 135 } 136 137 #define VGA_DAC_MASK 0x06 138 139 static void wreg_hdr(struct cirrus_device *cirrus, u8 val) 140 { 141 ioread8(cirrus->mmio + VGA_DAC_MASK); 142 ioread8(cirrus->mmio + VGA_DAC_MASK); 143 ioread8(cirrus->mmio + VGA_DAC_MASK); 144 ioread8(cirrus->mmio + VGA_DAC_MASK); 145 iowrite8(val, cirrus->mmio + VGA_DAC_MASK); 146 } 147 148 static const struct drm_format_info *cirrus_convert_to(struct drm_framebuffer *fb) 149 { 150 if (fb->format->format == DRM_FORMAT_XRGB8888 && fb->pitches[0] > CIRRUS_MAX_PITCH) { 151 if (fb->width * 3 <= CIRRUS_MAX_PITCH) 152 /* convert from XR24 to RG24 */ 153 return drm_format_info(DRM_FORMAT_RGB888); 154 else 155 /* convert from XR24 to RG16 */ 156 return drm_format_info(DRM_FORMAT_RGB565); 157 } 158 return NULL; 159 } 160 161 static const struct drm_format_info *cirrus_format(struct drm_framebuffer *fb) 162 { 163 const struct drm_format_info *format = cirrus_convert_to(fb); 164 165 if (format) 166 return format; 167 return fb->format; 168 } 169 170 static int cirrus_pitch(struct drm_framebuffer *fb) 171 { 172 const struct drm_format_info *format = cirrus_convert_to(fb); 173 174 if (format) 175 return drm_format_info_min_pitch(format, 0, fb->width); 176 return fb->pitches[0]; 177 } 178 179 static void cirrus_set_start_address(struct cirrus_device *cirrus, u32 offset) 180 { 181 u32 addr; 182 u8 tmp; 183 184 addr = offset >> 2; 185 wreg_crt(cirrus, 0x0c, (u8)((addr >> 8) & 0xff)); 186 wreg_crt(cirrus, 0x0d, (u8)(addr & 0xff)); 187 188 tmp = rreg_crt(cirrus, 0x1b); 189 tmp &= 0xf2; 190 tmp |= (addr >> 16) & 0x01; 191 tmp |= (addr >> 15) & 0x0c; 192 wreg_crt(cirrus, 0x1b, tmp); 193 194 tmp = rreg_crt(cirrus, 0x1d); 195 tmp &= 0x7f; 196 tmp |= (addr >> 12) & 0x80; 197 wreg_crt(cirrus, 0x1d, tmp); 198 } 199 200 static void cirrus_mode_set(struct cirrus_device *cirrus, 201 struct drm_display_mode *mode) 202 { 203 int hsyncstart, hsyncend, htotal, hdispend; 204 int vtotal, vdispend; 205 int tmp; 206 207 htotal = mode->htotal / 8; 208 hsyncend = mode->hsync_end / 8; 209 hsyncstart = mode->hsync_start / 8; 210 hdispend = mode->hdisplay / 8; 211 212 vtotal = mode->vtotal; 213 vdispend = mode->vdisplay; 214 215 vdispend -= 1; 216 vtotal -= 2; 217 218 htotal -= 5; 219 hdispend -= 1; 220 hsyncstart += 1; 221 hsyncend += 1; 222 223 wreg_crt(cirrus, VGA_CRTC_V_SYNC_END, 0x20); 224 wreg_crt(cirrus, VGA_CRTC_H_TOTAL, htotal); 225 wreg_crt(cirrus, VGA_CRTC_H_DISP, hdispend); 226 wreg_crt(cirrus, VGA_CRTC_H_SYNC_START, hsyncstart); 227 wreg_crt(cirrus, VGA_CRTC_H_SYNC_END, hsyncend); 228 wreg_crt(cirrus, VGA_CRTC_V_TOTAL, vtotal & 0xff); 229 wreg_crt(cirrus, VGA_CRTC_V_DISP_END, vdispend & 0xff); 230 231 tmp = 0x40; 232 if ((vdispend + 1) & 512) 233 tmp |= 0x20; 234 wreg_crt(cirrus, VGA_CRTC_MAX_SCAN, tmp); 235 236 /* 237 * Overflow bits for values that don't fit in the standard registers 238 */ 239 tmp = 0x10; 240 if (vtotal & 0x100) 241 tmp |= 0x01; 242 if (vdispend & 0x100) 243 tmp |= 0x02; 244 if ((vdispend + 1) & 0x100) 245 tmp |= 0x08; 246 if (vtotal & 0x200) 247 tmp |= 0x20; 248 if (vdispend & 0x200) 249 tmp |= 0x40; 250 wreg_crt(cirrus, VGA_CRTC_OVERFLOW, tmp); 251 252 tmp = 0; 253 254 /* More overflow bits */ 255 256 if ((htotal + 5) & 0x40) 257 tmp |= 0x10; 258 if ((htotal + 5) & 0x80) 259 tmp |= 0x20; 260 if (vtotal & 0x100) 261 tmp |= 0x40; 262 if (vtotal & 0x200) 263 tmp |= 0x80; 264 265 wreg_crt(cirrus, CL_CRT1A, tmp); 266 267 /* Disable Hercules/CGA compatibility */ 268 wreg_crt(cirrus, VGA_CRTC_MODE, 0x03); 269 } 270 271 static void cirrus_format_set(struct cirrus_device *cirrus, 272 const struct drm_format_info *format) 273 { 274 u8 sr07, hdr; 275 276 sr07 = rreg_seq(cirrus, 0x07); 277 sr07 &= 0xe0; 278 279 switch (format->format) { 280 case DRM_FORMAT_C8: 281 sr07 |= 0x11; 282 hdr = 0x00; 283 break; 284 case DRM_FORMAT_RGB565: 285 sr07 |= 0x17; 286 hdr = 0xc1; 287 break; 288 case DRM_FORMAT_RGB888: 289 sr07 |= 0x15; 290 hdr = 0xc5; 291 break; 292 case DRM_FORMAT_XRGB8888: 293 sr07 |= 0x19; 294 hdr = 0xc5; 295 break; 296 default: 297 return; 298 } 299 300 wreg_seq(cirrus, 0x7, sr07); 301 302 /* Enable high-colour modes */ 303 wreg_gfx(cirrus, VGA_GFX_MODE, 0x40); 304 305 /* And set graphics mode */ 306 wreg_gfx(cirrus, VGA_GFX_MISC, 0x01); 307 308 wreg_hdr(cirrus, hdr); 309 } 310 311 static void cirrus_pitch_set(struct cirrus_device *cirrus, unsigned int pitch) 312 { 313 u8 cr13, cr1b; 314 315 /* Program the pitch */ 316 cr13 = pitch / 8; 317 wreg_crt(cirrus, VGA_CRTC_OFFSET, cr13); 318 319 /* Enable extended blanking and pitch bits, and enable full memory */ 320 cr1b = 0x22; 321 cr1b |= (pitch >> 7) & 0x10; 322 cr1b |= (pitch >> 6) & 0x40; 323 wreg_crt(cirrus, 0x1b, cr1b); 324 325 cirrus_set_start_address(cirrus, 0); 326 } 327 328 /* ------------------------------------------------------------------ */ 329 /* cirrus display pipe */ 330 331 static const uint32_t cirrus_primary_plane_formats[] = { 332 DRM_FORMAT_RGB565, 333 DRM_FORMAT_RGB888, 334 DRM_FORMAT_XRGB8888, 335 }; 336 337 static const uint64_t cirrus_primary_plane_format_modifiers[] = { 338 DRM_FORMAT_MOD_LINEAR, 339 DRM_FORMAT_MOD_INVALID 340 }; 341 342 static int cirrus_primary_plane_helper_atomic_check(struct drm_plane *plane, 343 struct drm_atomic_state *state) 344 { 345 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); 346 struct cirrus_primary_plane_state *new_primary_plane_state = 347 to_cirrus_primary_plane_state(new_plane_state); 348 struct drm_framebuffer *fb = new_plane_state->fb; 349 struct drm_crtc *new_crtc = new_plane_state->crtc; 350 struct drm_crtc_state *new_crtc_state = NULL; 351 int ret; 352 unsigned int pitch; 353 354 if (new_crtc) 355 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc); 356 357 ret = drm_atomic_helper_check_plane_state(new_plane_state, new_crtc_state, 358 DRM_PLANE_NO_SCALING, 359 DRM_PLANE_NO_SCALING, 360 false, false); 361 if (ret) 362 return ret; 363 else if (!new_plane_state->visible) 364 return 0; 365 366 pitch = cirrus_pitch(fb); 367 368 /* validate size constraints */ 369 if (pitch > CIRRUS_MAX_PITCH) 370 return -EINVAL; 371 else if (pitch * fb->height > CIRRUS_VRAM_SIZE) 372 return -EINVAL; 373 374 new_primary_plane_state->format = cirrus_format(fb); 375 new_primary_plane_state->pitch = pitch; 376 377 return 0; 378 } 379 380 static void cirrus_primary_plane_helper_atomic_update(struct drm_plane *plane, 381 struct drm_atomic_state *state) 382 { 383 struct cirrus_device *cirrus = to_cirrus(plane->dev); 384 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); 385 struct cirrus_primary_plane_state *primary_plane_state = 386 to_cirrus_primary_plane_state(plane_state); 387 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state); 388 struct drm_framebuffer *fb = plane_state->fb; 389 const struct drm_format_info *format = primary_plane_state->format; 390 unsigned int pitch = primary_plane_state->pitch; 391 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane); 392 struct cirrus_primary_plane_state *old_primary_plane_state = 393 to_cirrus_primary_plane_state(old_plane_state); 394 struct iosys_map vaddr = IOSYS_MAP_INIT_VADDR_IOMEM(cirrus->vram); 395 struct drm_atomic_helper_damage_iter iter; 396 struct drm_rect damage; 397 int idx; 398 399 if (!fb) 400 return; 401 402 if (!drm_dev_enter(&cirrus->dev, &idx)) 403 return; 404 405 if (old_primary_plane_state->format != format) 406 cirrus_format_set(cirrus, format); 407 if (old_primary_plane_state->pitch != pitch) 408 cirrus_pitch_set(cirrus, pitch); 409 410 drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state); 411 drm_atomic_for_each_plane_damage(&iter, &damage) { 412 unsigned int offset = drm_fb_clip_offset(pitch, format, &damage); 413 struct iosys_map dst = IOSYS_MAP_INIT_OFFSET(&vaddr, offset); 414 415 drm_fb_blit(&dst, &pitch, format->format, shadow_plane_state->data, fb, 416 &damage, &shadow_plane_state->fmtcnv_state); 417 } 418 419 drm_dev_exit(idx); 420 } 421 422 static const struct drm_plane_helper_funcs cirrus_primary_plane_helper_funcs = { 423 DRM_GEM_SHADOW_PLANE_HELPER_FUNCS, 424 .atomic_check = cirrus_primary_plane_helper_atomic_check, 425 .atomic_update = cirrus_primary_plane_helper_atomic_update, 426 }; 427 428 static struct drm_plane_state * 429 cirrus_primary_plane_atomic_duplicate_state(struct drm_plane *plane) 430 { 431 struct drm_plane_state *plane_state = plane->state; 432 struct cirrus_primary_plane_state *primary_plane_state = 433 to_cirrus_primary_plane_state(plane_state); 434 struct cirrus_primary_plane_state *new_primary_plane_state; 435 struct drm_shadow_plane_state *new_shadow_plane_state; 436 437 if (!plane_state) 438 return NULL; 439 440 new_primary_plane_state = kzalloc(sizeof(*new_primary_plane_state), GFP_KERNEL); 441 if (!new_primary_plane_state) 442 return NULL; 443 new_shadow_plane_state = &new_primary_plane_state->base; 444 445 __drm_gem_duplicate_shadow_plane_state(plane, new_shadow_plane_state); 446 new_primary_plane_state->format = primary_plane_state->format; 447 new_primary_plane_state->pitch = primary_plane_state->pitch; 448 449 return &new_shadow_plane_state->base; 450 } 451 452 static void cirrus_primary_plane_atomic_destroy_state(struct drm_plane *plane, 453 struct drm_plane_state *plane_state) 454 { 455 struct cirrus_primary_plane_state *primary_plane_state = 456 to_cirrus_primary_plane_state(plane_state); 457 458 __drm_gem_destroy_shadow_plane_state(&primary_plane_state->base); 459 kfree(primary_plane_state); 460 } 461 462 static void cirrus_reset_primary_plane(struct drm_plane *plane) 463 { 464 struct cirrus_primary_plane_state *primary_plane_state; 465 466 if (plane->state) { 467 cirrus_primary_plane_atomic_destroy_state(plane, plane->state); 468 plane->state = NULL; /* must be set to NULL here */ 469 } 470 471 primary_plane_state = kzalloc(sizeof(*primary_plane_state), GFP_KERNEL); 472 if (!primary_plane_state) 473 return; 474 __drm_gem_reset_shadow_plane(plane, &primary_plane_state->base); 475 } 476 477 static const struct drm_plane_funcs cirrus_primary_plane_funcs = { 478 .update_plane = drm_atomic_helper_update_plane, 479 .disable_plane = drm_atomic_helper_disable_plane, 480 .destroy = drm_plane_cleanup, 481 .reset = cirrus_reset_primary_plane, 482 .atomic_duplicate_state = cirrus_primary_plane_atomic_duplicate_state, 483 .atomic_destroy_state = cirrus_primary_plane_atomic_destroy_state, 484 }; 485 486 static int cirrus_crtc_helper_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state) 487 { 488 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 489 int ret; 490 491 if (!crtc_state->enable) 492 return 0; 493 494 ret = drm_atomic_helper_check_crtc_primary_plane(crtc_state); 495 if (ret) 496 return ret; 497 498 return 0; 499 } 500 501 static void cirrus_crtc_helper_atomic_enable(struct drm_crtc *crtc, 502 struct drm_atomic_state *state) 503 { 504 struct cirrus_device *cirrus = to_cirrus(crtc->dev); 505 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 506 int idx; 507 508 if (!drm_dev_enter(&cirrus->dev, &idx)) 509 return; 510 511 cirrus_mode_set(cirrus, &crtc_state->mode); 512 513 #ifdef CONFIG_HAS_IOPORT 514 /* Unblank (needed on S3 resume, vgabios doesn't do it then) */ 515 outb(VGA_AR_ENABLE_DISPLAY, VGA_ATT_W); 516 #endif 517 518 drm_dev_exit(idx); 519 } 520 521 static const struct drm_crtc_helper_funcs cirrus_crtc_helper_funcs = { 522 .atomic_check = cirrus_crtc_helper_atomic_check, 523 .atomic_enable = cirrus_crtc_helper_atomic_enable, 524 }; 525 526 static const struct drm_crtc_funcs cirrus_crtc_funcs = { 527 .reset = drm_atomic_helper_crtc_reset, 528 .destroy = drm_crtc_cleanup, 529 .set_config = drm_atomic_helper_set_config, 530 .page_flip = drm_atomic_helper_page_flip, 531 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 532 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 533 }; 534 535 static const struct drm_encoder_funcs cirrus_encoder_funcs = { 536 .destroy = drm_encoder_cleanup, 537 }; 538 539 static int cirrus_connector_helper_get_modes(struct drm_connector *connector) 540 { 541 int count; 542 543 count = drm_add_modes_noedid(connector, 544 connector->dev->mode_config.max_width, 545 connector->dev->mode_config.max_height); 546 drm_set_preferred_mode(connector, 1024, 768); 547 return count; 548 } 549 550 static const struct drm_connector_helper_funcs cirrus_connector_helper_funcs = { 551 .get_modes = cirrus_connector_helper_get_modes, 552 }; 553 554 static const struct drm_connector_funcs cirrus_connector_funcs = { 555 .fill_modes = drm_helper_probe_single_connector_modes, 556 .destroy = drm_connector_cleanup, 557 .reset = drm_atomic_helper_connector_reset, 558 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 559 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 560 }; 561 562 static int cirrus_pipe_init(struct cirrus_device *cirrus) 563 { 564 struct drm_device *dev = &cirrus->dev; 565 struct drm_plane *primary_plane; 566 struct drm_crtc *crtc; 567 struct drm_encoder *encoder; 568 struct drm_connector *connector; 569 int ret; 570 571 primary_plane = &cirrus->primary_plane; 572 ret = drm_universal_plane_init(dev, primary_plane, 0, 573 &cirrus_primary_plane_funcs, 574 cirrus_primary_plane_formats, 575 ARRAY_SIZE(cirrus_primary_plane_formats), 576 cirrus_primary_plane_format_modifiers, 577 DRM_PLANE_TYPE_PRIMARY, NULL); 578 if (ret) 579 return ret; 580 drm_plane_helper_add(primary_plane, &cirrus_primary_plane_helper_funcs); 581 drm_plane_enable_fb_damage_clips(primary_plane); 582 583 crtc = &cirrus->crtc; 584 ret = drm_crtc_init_with_planes(dev, crtc, primary_plane, NULL, 585 &cirrus_crtc_funcs, NULL); 586 if (ret) 587 return ret; 588 drm_crtc_helper_add(crtc, &cirrus_crtc_helper_funcs); 589 590 encoder = &cirrus->encoder; 591 ret = drm_encoder_init(dev, encoder, &cirrus_encoder_funcs, 592 DRM_MODE_ENCODER_DAC, NULL); 593 if (ret) 594 return ret; 595 encoder->possible_crtcs = drm_crtc_mask(crtc); 596 597 connector = &cirrus->connector; 598 ret = drm_connector_init(dev, connector, &cirrus_connector_funcs, 599 DRM_MODE_CONNECTOR_VGA); 600 if (ret) 601 return ret; 602 drm_connector_helper_add(connector, &cirrus_connector_helper_funcs); 603 604 ret = drm_connector_attach_encoder(connector, encoder); 605 if (ret) 606 return ret; 607 608 return 0; 609 } 610 611 /* ------------------------------------------------------------------ */ 612 /* cirrus framebuffers & mode config */ 613 614 static enum drm_mode_status cirrus_mode_config_mode_valid(struct drm_device *dev, 615 const struct drm_display_mode *mode) 616 { 617 const struct drm_format_info *format = drm_format_info(DRM_FORMAT_XRGB8888); 618 uint64_t pitch = drm_format_info_min_pitch(format, 0, mode->hdisplay); 619 620 if (pitch * mode->vdisplay > CIRRUS_VRAM_SIZE) 621 return MODE_MEM; 622 623 return MODE_OK; 624 } 625 626 static const struct drm_mode_config_funcs cirrus_mode_config_funcs = { 627 .fb_create = drm_gem_fb_create_with_dirty, 628 .mode_valid = cirrus_mode_config_mode_valid, 629 .atomic_check = drm_atomic_helper_check, 630 .atomic_commit = drm_atomic_helper_commit, 631 }; 632 633 static int cirrus_mode_config_init(struct cirrus_device *cirrus) 634 { 635 struct drm_device *dev = &cirrus->dev; 636 int ret; 637 638 ret = drmm_mode_config_init(dev); 639 if (ret) 640 return ret; 641 642 dev->mode_config.min_width = 0; 643 dev->mode_config.min_height = 0; 644 dev->mode_config.max_width = CIRRUS_MAX_PITCH / 2; 645 dev->mode_config.max_height = 1024; 646 dev->mode_config.preferred_depth = 16; 647 dev->mode_config.prefer_shadow = 0; 648 dev->mode_config.funcs = &cirrus_mode_config_funcs; 649 650 return 0; 651 } 652 653 /* ------------------------------------------------------------------ */ 654 655 DEFINE_DRM_GEM_FOPS(cirrus_fops); 656 657 static const struct drm_driver cirrus_driver = { 658 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, 659 660 .name = DRIVER_NAME, 661 .desc = DRIVER_DESC, 662 .date = DRIVER_DATE, 663 .major = DRIVER_MAJOR, 664 .minor = DRIVER_MINOR, 665 666 .fops = &cirrus_fops, 667 DRM_GEM_SHMEM_DRIVER_OPS, 668 DRM_FBDEV_SHMEM_DRIVER_OPS, 669 }; 670 671 static int cirrus_pci_probe(struct pci_dev *pdev, 672 const struct pci_device_id *ent) 673 { 674 struct drm_device *dev; 675 struct cirrus_device *cirrus; 676 int ret; 677 678 ret = aperture_remove_conflicting_pci_devices(pdev, cirrus_driver.name); 679 if (ret) 680 return ret; 681 682 ret = pcim_enable_device(pdev); 683 if (ret) 684 return ret; 685 686 ret = pci_request_regions(pdev, DRIVER_NAME); 687 if (ret) 688 return ret; 689 690 ret = -ENOMEM; 691 cirrus = devm_drm_dev_alloc(&pdev->dev, &cirrus_driver, 692 struct cirrus_device, dev); 693 if (IS_ERR(cirrus)) 694 return PTR_ERR(cirrus); 695 696 dev = &cirrus->dev; 697 698 cirrus->vram = devm_ioremap(&pdev->dev, pci_resource_start(pdev, 0), 699 pci_resource_len(pdev, 0)); 700 if (cirrus->vram == NULL) 701 return -ENOMEM; 702 703 cirrus->mmio = devm_ioremap(&pdev->dev, pci_resource_start(pdev, 1), 704 pci_resource_len(pdev, 1)); 705 if (cirrus->mmio == NULL) 706 return -ENOMEM; 707 708 ret = cirrus_mode_config_init(cirrus); 709 if (ret) 710 return ret; 711 712 ret = cirrus_pipe_init(cirrus); 713 if (ret < 0) 714 return ret; 715 716 drm_mode_config_reset(dev); 717 718 pci_set_drvdata(pdev, dev); 719 ret = drm_dev_register(dev, 0); 720 if (ret) 721 return ret; 722 723 drm_client_setup(dev, NULL); 724 return 0; 725 } 726 727 static void cirrus_pci_remove(struct pci_dev *pdev) 728 { 729 struct drm_device *dev = pci_get_drvdata(pdev); 730 731 drm_dev_unplug(dev); 732 drm_atomic_helper_shutdown(dev); 733 } 734 735 static void cirrus_pci_shutdown(struct pci_dev *pdev) 736 { 737 drm_atomic_helper_shutdown(pci_get_drvdata(pdev)); 738 } 739 740 static const struct pci_device_id pciidlist[] = { 741 { 742 .vendor = PCI_VENDOR_ID_CIRRUS, 743 .device = PCI_DEVICE_ID_CIRRUS_5446, 744 /* only bind to the cirrus chip in qemu */ 745 .subvendor = PCI_SUBVENDOR_ID_REDHAT_QUMRANET, 746 .subdevice = PCI_SUBDEVICE_ID_QEMU, 747 }, { 748 .vendor = PCI_VENDOR_ID_CIRRUS, 749 .device = PCI_DEVICE_ID_CIRRUS_5446, 750 .subvendor = PCI_VENDOR_ID_XEN, 751 .subdevice = 0x0001, 752 }, 753 { /* end if list */ } 754 }; 755 756 static struct pci_driver cirrus_pci_driver = { 757 .name = DRIVER_NAME, 758 .id_table = pciidlist, 759 .probe = cirrus_pci_probe, 760 .remove = cirrus_pci_remove, 761 .shutdown = cirrus_pci_shutdown, 762 }; 763 764 drm_module_pci_driver(cirrus_pci_driver) 765 766 MODULE_DEVICE_TABLE(pci, pciidlist); 767 MODULE_DESCRIPTION("Cirrus driver for QEMU emulated device"); 768 MODULE_LICENSE("GPL"); 769