1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright 2012-2019 Red Hat 4 * 5 * This file is subject to the terms and conditions of the GNU General 6 * Public License version 2. See the file COPYING in the main 7 * directory of this archive for more details. 8 * 9 * Authors: Matthew Garrett 10 * Dave Airlie 11 * Gerd Hoffmann 12 * 13 * Portions of this code derived from cirrusfb.c: 14 * drivers/video/cirrusfb.c - driver for Cirrus Logic chipsets 15 * 16 * Copyright 1999-2001 Jeff Garzik <jgarzik@pobox.com> 17 */ 18 19 #include <linux/aperture.h> 20 #include <linux/iosys-map.h> 21 #include <linux/module.h> 22 #include <linux/pci.h> 23 24 #include <video/cirrus.h> 25 #include <video/vga.h> 26 27 #include <drm/clients/drm_client_setup.h> 28 #include <drm/drm_atomic.h> 29 #include <drm/drm_atomic_helper.h> 30 #include <drm/drm_atomic_state_helper.h> 31 #include <drm/drm_connector.h> 32 #include <drm/drm_damage_helper.h> 33 #include <drm/drm_drv.h> 34 #include <drm/drm_edid.h> 35 #include <drm/drm_fbdev_shmem.h> 36 #include <drm/drm_file.h> 37 #include <drm/drm_format_helper.h> 38 #include <drm/drm_fourcc.h> 39 #include <drm/drm_framebuffer.h> 40 #include <drm/drm_gem_atomic_helper.h> 41 #include <drm/drm_gem_framebuffer_helper.h> 42 #include <drm/drm_gem_shmem_helper.h> 43 #include <drm/drm_ioctl.h> 44 #include <drm/drm_managed.h> 45 #include <drm/drm_modeset_helper_vtables.h> 46 #include <drm/drm_module.h> 47 #include <drm/drm_probe_helper.h> 48 #include <drm/drm_vblank.h> 49 #include <drm/drm_vblank_helper.h> 50 51 #define DRIVER_NAME "cirrus-qemu" 52 #define DRIVER_DESC "qemu cirrus vga" 53 #define DRIVER_MAJOR 2 54 #define DRIVER_MINOR 0 55 56 #define CIRRUS_MAX_PITCH (0x1FF << 3) /* (4096 - 1) & ~111b bytes */ 57 #define CIRRUS_VRAM_SIZE (4 * 1024 * 1024) /* 4 MB */ 58 59 struct cirrus_device { 60 struct drm_device dev; 61 62 /* modesetting pipeline */ 63 struct drm_plane primary_plane; 64 struct drm_crtc crtc; 65 struct drm_encoder encoder; 66 struct drm_connector connector; 67 68 /* HW resources */ 69 void __iomem *vram; 70 void __iomem *mmio; 71 }; 72 73 #define to_cirrus(_dev) container_of(_dev, struct cirrus_device, dev) 74 75 /* ------------------------------------------------------------------ */ 76 /* 77 * The meat of this driver. The core passes us a mode and we have to program 78 * it. The modesetting here is the bare minimum required to satisfy the qemu 79 * emulation of this hardware, and running this against a real device is 80 * likely to result in an inadequately programmed mode. We've already had 81 * the opportunity to modify the mode, so whatever we receive here should 82 * be something that can be correctly programmed and displayed 83 */ 84 85 #define SEQ_INDEX 4 86 #define SEQ_DATA 5 87 88 static u8 rreg_seq(struct cirrus_device *cirrus, u8 reg) 89 { 90 iowrite8(reg, cirrus->mmio + SEQ_INDEX); 91 return ioread8(cirrus->mmio + SEQ_DATA); 92 } 93 94 static void wreg_seq(struct cirrus_device *cirrus, u8 reg, u8 val) 95 { 96 iowrite8(reg, cirrus->mmio + SEQ_INDEX); 97 iowrite8(val, cirrus->mmio + SEQ_DATA); 98 } 99 100 #define CRT_INDEX 0x14 101 #define CRT_DATA 0x15 102 103 static u8 rreg_crt(struct cirrus_device *cirrus, u8 reg) 104 { 105 iowrite8(reg, cirrus->mmio + CRT_INDEX); 106 return ioread8(cirrus->mmio + CRT_DATA); 107 } 108 109 static void wreg_crt(struct cirrus_device *cirrus, u8 reg, u8 val) 110 { 111 iowrite8(reg, cirrus->mmio + CRT_INDEX); 112 iowrite8(val, cirrus->mmio + CRT_DATA); 113 } 114 115 #define GFX_INDEX 0xe 116 #define GFX_DATA 0xf 117 118 static void wreg_gfx(struct cirrus_device *cirrus, u8 reg, u8 val) 119 { 120 iowrite8(reg, cirrus->mmio + GFX_INDEX); 121 iowrite8(val, cirrus->mmio + GFX_DATA); 122 } 123 124 #define VGA_DAC_MASK 0x06 125 126 static void wreg_hdr(struct cirrus_device *cirrus, u8 val) 127 { 128 ioread8(cirrus->mmio + VGA_DAC_MASK); 129 ioread8(cirrus->mmio + VGA_DAC_MASK); 130 ioread8(cirrus->mmio + VGA_DAC_MASK); 131 ioread8(cirrus->mmio + VGA_DAC_MASK); 132 iowrite8(val, cirrus->mmio + VGA_DAC_MASK); 133 } 134 135 static void cirrus_set_start_address(struct cirrus_device *cirrus, u32 offset) 136 { 137 u32 addr; 138 u8 tmp; 139 140 addr = offset >> 2; 141 wreg_crt(cirrus, 0x0c, (u8)((addr >> 8) & 0xff)); 142 wreg_crt(cirrus, 0x0d, (u8)(addr & 0xff)); 143 144 tmp = rreg_crt(cirrus, 0x1b); 145 tmp &= 0xf2; 146 tmp |= (addr >> 16) & 0x01; 147 tmp |= (addr >> 15) & 0x0c; 148 wreg_crt(cirrus, 0x1b, tmp); 149 150 tmp = rreg_crt(cirrus, 0x1d); 151 tmp &= 0x7f; 152 tmp |= (addr >> 12) & 0x80; 153 wreg_crt(cirrus, 0x1d, tmp); 154 } 155 156 static void cirrus_mode_set(struct cirrus_device *cirrus, 157 struct drm_display_mode *mode) 158 { 159 int hsyncstart, hsyncend, htotal, hdispend; 160 int vtotal, vdispend; 161 int tmp; 162 163 htotal = mode->htotal / 8; 164 hsyncend = mode->hsync_end / 8; 165 hsyncstart = mode->hsync_start / 8; 166 hdispend = mode->hdisplay / 8; 167 168 vtotal = mode->vtotal; 169 vdispend = mode->vdisplay; 170 171 vdispend -= 1; 172 vtotal -= 2; 173 174 htotal -= 5; 175 hdispend -= 1; 176 hsyncstart += 1; 177 hsyncend += 1; 178 179 wreg_crt(cirrus, VGA_CRTC_V_SYNC_END, 0x20); 180 wreg_crt(cirrus, VGA_CRTC_H_TOTAL, htotal); 181 wreg_crt(cirrus, VGA_CRTC_H_DISP, hdispend); 182 wreg_crt(cirrus, VGA_CRTC_H_SYNC_START, hsyncstart); 183 wreg_crt(cirrus, VGA_CRTC_H_SYNC_END, hsyncend); 184 wreg_crt(cirrus, VGA_CRTC_V_TOTAL, vtotal & 0xff); 185 wreg_crt(cirrus, VGA_CRTC_V_DISP_END, vdispend & 0xff); 186 187 tmp = 0x40; 188 if ((vdispend + 1) & 512) 189 tmp |= 0x20; 190 wreg_crt(cirrus, VGA_CRTC_MAX_SCAN, tmp); 191 192 /* 193 * Overflow bits for values that don't fit in the standard registers 194 */ 195 tmp = 0x10; 196 if (vtotal & 0x100) 197 tmp |= 0x01; 198 if (vdispend & 0x100) 199 tmp |= 0x02; 200 if ((vdispend + 1) & 0x100) 201 tmp |= 0x08; 202 if (vtotal & 0x200) 203 tmp |= 0x20; 204 if (vdispend & 0x200) 205 tmp |= 0x40; 206 wreg_crt(cirrus, VGA_CRTC_OVERFLOW, tmp); 207 208 tmp = 0; 209 210 /* More overflow bits */ 211 212 if ((htotal + 5) & 0x40) 213 tmp |= 0x10; 214 if ((htotal + 5) & 0x80) 215 tmp |= 0x20; 216 if (vtotal & 0x100) 217 tmp |= 0x40; 218 if (vtotal & 0x200) 219 tmp |= 0x80; 220 221 wreg_crt(cirrus, CL_CRT1A, tmp); 222 223 /* Disable Hercules/CGA compatibility */ 224 wreg_crt(cirrus, VGA_CRTC_MODE, 0x03); 225 } 226 227 static void cirrus_format_set(struct cirrus_device *cirrus, 228 const struct drm_format_info *format) 229 { 230 u8 sr07, hdr; 231 232 sr07 = rreg_seq(cirrus, 0x07); 233 sr07 &= 0xe0; 234 235 switch (format->format) { 236 case DRM_FORMAT_C8: 237 sr07 |= 0x11; 238 hdr = 0x00; 239 break; 240 case DRM_FORMAT_RGB565: 241 sr07 |= 0x17; 242 hdr = 0xc1; 243 break; 244 case DRM_FORMAT_RGB888: 245 sr07 |= 0x15; 246 hdr = 0xc5; 247 break; 248 case DRM_FORMAT_XRGB8888: 249 sr07 |= 0x19; 250 hdr = 0xc5; 251 break; 252 default: 253 return; 254 } 255 256 wreg_seq(cirrus, 0x7, sr07); 257 258 /* Enable high-colour modes */ 259 wreg_gfx(cirrus, VGA_GFX_MODE, 0x40); 260 261 /* And set graphics mode */ 262 wreg_gfx(cirrus, VGA_GFX_MISC, 0x01); 263 264 wreg_hdr(cirrus, hdr); 265 } 266 267 static void cirrus_pitch_set(struct cirrus_device *cirrus, unsigned int pitch) 268 { 269 u8 cr13, cr1b; 270 271 /* Program the pitch */ 272 cr13 = pitch / 8; 273 wreg_crt(cirrus, VGA_CRTC_OFFSET, cr13); 274 275 /* Enable extended blanking and pitch bits, and enable full memory */ 276 cr1b = 0x22; 277 cr1b |= (pitch >> 7) & 0x10; 278 wreg_crt(cirrus, 0x1b, cr1b); 279 280 cirrus_set_start_address(cirrus, 0); 281 } 282 283 /* ------------------------------------------------------------------ */ 284 /* cirrus display pipe */ 285 286 static const uint32_t cirrus_primary_plane_formats[] = { 287 DRM_FORMAT_RGB565, 288 DRM_FORMAT_RGB888, 289 DRM_FORMAT_XRGB8888, 290 }; 291 292 static const uint64_t cirrus_primary_plane_format_modifiers[] = { 293 DRM_FORMAT_MOD_LINEAR, 294 DRM_FORMAT_MOD_INVALID 295 }; 296 297 static int cirrus_primary_plane_helper_atomic_check(struct drm_plane *plane, 298 struct drm_atomic_state *state) 299 { 300 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); 301 struct drm_framebuffer *fb = new_plane_state->fb; 302 struct drm_crtc *new_crtc = new_plane_state->crtc; 303 struct drm_crtc_state *new_crtc_state = NULL; 304 int ret; 305 306 if (new_crtc) 307 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc); 308 309 ret = drm_atomic_helper_check_plane_state(new_plane_state, new_crtc_state, 310 DRM_PLANE_NO_SCALING, 311 DRM_PLANE_NO_SCALING, 312 false, false); 313 if (ret) 314 return ret; 315 else if (!new_plane_state->visible) 316 return 0; 317 318 /* validate size constraints */ 319 if (fb->pitches[0] > CIRRUS_MAX_PITCH) 320 return -EINVAL; 321 else if (fb->pitches[0] > CIRRUS_VRAM_SIZE / fb->height) 322 return -EINVAL; 323 324 return 0; 325 } 326 327 static void cirrus_primary_plane_helper_atomic_update(struct drm_plane *plane, 328 struct drm_atomic_state *state) 329 { 330 struct cirrus_device *cirrus = to_cirrus(plane->dev); 331 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); 332 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state); 333 struct drm_framebuffer *fb = plane_state->fb; 334 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane); 335 struct drm_framebuffer *old_fb = old_plane_state->fb; 336 struct iosys_map vaddr = IOSYS_MAP_INIT_VADDR_IOMEM(cirrus->vram); 337 struct drm_atomic_helper_damage_iter iter; 338 struct drm_rect damage; 339 int idx; 340 341 if (!fb) 342 return; 343 344 if (!drm_dev_enter(&cirrus->dev, &idx)) 345 return; 346 347 if (!old_fb || old_fb->format != fb->format) 348 cirrus_format_set(cirrus, fb->format); 349 if (!old_fb || old_fb->pitches[0] != fb->pitches[0]) 350 cirrus_pitch_set(cirrus, fb->pitches[0]); 351 352 drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state); 353 drm_atomic_for_each_plane_damage(&iter, &damage) { 354 unsigned int offset = drm_fb_clip_offset(fb->pitches[0], fb->format, &damage); 355 struct iosys_map dst = IOSYS_MAP_INIT_OFFSET(&vaddr, offset); 356 357 drm_fb_memcpy(&dst, fb->pitches, shadow_plane_state->data, fb, &damage); 358 } 359 360 drm_dev_exit(idx); 361 } 362 363 static const struct drm_plane_helper_funcs cirrus_primary_plane_helper_funcs = { 364 DRM_GEM_SHADOW_PLANE_HELPER_FUNCS, 365 .atomic_check = cirrus_primary_plane_helper_atomic_check, 366 .atomic_update = cirrus_primary_plane_helper_atomic_update, 367 }; 368 369 static const struct drm_plane_funcs cirrus_primary_plane_funcs = { 370 .update_plane = drm_atomic_helper_update_plane, 371 .disable_plane = drm_atomic_helper_disable_plane, 372 .destroy = drm_plane_cleanup, 373 DRM_GEM_SHADOW_PLANE_FUNCS, 374 }; 375 376 static int cirrus_crtc_helper_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state) 377 { 378 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 379 int ret; 380 381 if (!crtc_state->enable) 382 return 0; 383 384 ret = drm_atomic_helper_check_crtc_primary_plane(crtc_state); 385 if (ret) 386 return ret; 387 388 return 0; 389 } 390 391 static void cirrus_crtc_helper_atomic_enable(struct drm_crtc *crtc, 392 struct drm_atomic_state *state) 393 { 394 struct cirrus_device *cirrus = to_cirrus(crtc->dev); 395 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 396 int idx; 397 398 if (!drm_dev_enter(&cirrus->dev, &idx)) 399 return; 400 401 cirrus_mode_set(cirrus, &crtc_state->mode); 402 403 #ifdef CONFIG_HAS_IOPORT 404 /* Unblank (needed on S3 resume, vgabios doesn't do it then) */ 405 outb(VGA_AR_ENABLE_DISPLAY, VGA_ATT_W); 406 #endif 407 408 drm_dev_exit(idx); 409 410 drm_crtc_vblank_on(crtc); 411 } 412 413 static const struct drm_crtc_helper_funcs cirrus_crtc_helper_funcs = { 414 .atomic_check = cirrus_crtc_helper_atomic_check, 415 .atomic_flush = drm_crtc_vblank_atomic_flush, 416 .atomic_enable = cirrus_crtc_helper_atomic_enable, 417 .atomic_disable = drm_crtc_vblank_atomic_disable, 418 }; 419 420 static const struct drm_crtc_funcs cirrus_crtc_funcs = { 421 .reset = drm_atomic_helper_crtc_reset, 422 .destroy = drm_crtc_cleanup, 423 .set_config = drm_atomic_helper_set_config, 424 .page_flip = drm_atomic_helper_page_flip, 425 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 426 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 427 DRM_CRTC_VBLANK_TIMER_FUNCS, 428 }; 429 430 static const struct drm_encoder_funcs cirrus_encoder_funcs = { 431 .destroy = drm_encoder_cleanup, 432 }; 433 434 static int cirrus_connector_helper_get_modes(struct drm_connector *connector) 435 { 436 int count; 437 438 count = drm_add_modes_noedid(connector, 439 connector->dev->mode_config.max_width, 440 connector->dev->mode_config.max_height); 441 drm_set_preferred_mode(connector, 1024, 768); 442 return count; 443 } 444 445 static const struct drm_connector_helper_funcs cirrus_connector_helper_funcs = { 446 .get_modes = cirrus_connector_helper_get_modes, 447 }; 448 449 static const struct drm_connector_funcs cirrus_connector_funcs = { 450 .fill_modes = drm_helper_probe_single_connector_modes, 451 .destroy = drm_connector_cleanup, 452 .reset = drm_atomic_helper_connector_reset, 453 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 454 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 455 }; 456 457 static int cirrus_pipe_init(struct cirrus_device *cirrus) 458 { 459 struct drm_device *dev = &cirrus->dev; 460 struct drm_plane *primary_plane; 461 struct drm_crtc *crtc; 462 struct drm_encoder *encoder; 463 struct drm_connector *connector; 464 int ret; 465 466 primary_plane = &cirrus->primary_plane; 467 ret = drm_universal_plane_init(dev, primary_plane, 0, 468 &cirrus_primary_plane_funcs, 469 cirrus_primary_plane_formats, 470 ARRAY_SIZE(cirrus_primary_plane_formats), 471 cirrus_primary_plane_format_modifiers, 472 DRM_PLANE_TYPE_PRIMARY, NULL); 473 if (ret) 474 return ret; 475 drm_plane_helper_add(primary_plane, &cirrus_primary_plane_helper_funcs); 476 drm_plane_enable_fb_damage_clips(primary_plane); 477 478 crtc = &cirrus->crtc; 479 ret = drm_crtc_init_with_planes(dev, crtc, primary_plane, NULL, 480 &cirrus_crtc_funcs, NULL); 481 if (ret) 482 return ret; 483 drm_crtc_helper_add(crtc, &cirrus_crtc_helper_funcs); 484 485 encoder = &cirrus->encoder; 486 ret = drm_encoder_init(dev, encoder, &cirrus_encoder_funcs, 487 DRM_MODE_ENCODER_VIRTUAL, NULL); 488 if (ret) 489 return ret; 490 encoder->possible_crtcs = drm_crtc_mask(crtc); 491 492 connector = &cirrus->connector; 493 ret = drm_connector_init(dev, connector, &cirrus_connector_funcs, 494 DRM_MODE_CONNECTOR_VIRTUAL); 495 if (ret) 496 return ret; 497 drm_connector_helper_add(connector, &cirrus_connector_helper_funcs); 498 499 ret = drm_connector_attach_encoder(connector, encoder); 500 if (ret) 501 return ret; 502 503 ret = drm_vblank_init(dev, 1); 504 if (ret) 505 return ret; 506 507 return 0; 508 } 509 510 /* ------------------------------------------------------------------ */ 511 /* cirrus framebuffers & mode config */ 512 513 static enum drm_mode_status cirrus_mode_config_mode_valid(struct drm_device *dev, 514 const struct drm_display_mode *mode) 515 { 516 const struct drm_format_info *format = drm_format_info(DRM_FORMAT_XRGB8888); 517 u64 pitch; 518 519 if (drm_WARN_ON_ONCE(dev, !format)) 520 return MODE_ERROR; /* driver bug */ 521 522 pitch = drm_format_info_min_pitch(format, 0, mode->hdisplay); 523 if (!pitch) 524 return MODE_BAD_WIDTH; 525 if (pitch > CIRRUS_MAX_PITCH) 526 return MODE_BAD_WIDTH; /* maximum programmable pitch */ 527 if (pitch > CIRRUS_VRAM_SIZE / mode->vdisplay) 528 return MODE_MEM; 529 530 return MODE_OK; 531 } 532 533 static const struct drm_mode_config_funcs cirrus_mode_config_funcs = { 534 .fb_create = drm_gem_fb_create_with_dirty, 535 .mode_valid = cirrus_mode_config_mode_valid, 536 .atomic_check = drm_atomic_helper_check, 537 .atomic_commit = drm_atomic_helper_commit, 538 }; 539 540 static int cirrus_mode_config_init(struct cirrus_device *cirrus) 541 { 542 struct drm_device *dev = &cirrus->dev; 543 int ret; 544 545 ret = drmm_mode_config_init(dev); 546 if (ret) 547 return ret; 548 549 dev->mode_config.min_width = 0; 550 dev->mode_config.min_height = 0; 551 dev->mode_config.max_width = CIRRUS_MAX_PITCH / 2; 552 dev->mode_config.max_height = 1024; 553 dev->mode_config.preferred_depth = 16; 554 dev->mode_config.prefer_shadow = 0; 555 dev->mode_config.funcs = &cirrus_mode_config_funcs; 556 557 return 0; 558 } 559 560 /* ------------------------------------------------------------------ */ 561 562 DEFINE_DRM_GEM_FOPS(cirrus_fops); 563 564 static const struct drm_driver cirrus_driver = { 565 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, 566 567 .name = DRIVER_NAME, 568 .desc = DRIVER_DESC, 569 .major = DRIVER_MAJOR, 570 .minor = DRIVER_MINOR, 571 572 .fops = &cirrus_fops, 573 DRM_GEM_SHMEM_DRIVER_OPS, 574 DRM_FBDEV_SHMEM_DRIVER_OPS, 575 }; 576 577 static int cirrus_pci_probe(struct pci_dev *pdev, 578 const struct pci_device_id *ent) 579 { 580 struct drm_device *dev; 581 struct cirrus_device *cirrus; 582 int ret; 583 584 ret = aperture_remove_conflicting_pci_devices(pdev, cirrus_driver.name); 585 if (ret) 586 return ret; 587 588 ret = pcim_enable_device(pdev); 589 if (ret) 590 return ret; 591 592 ret = pcim_request_all_regions(pdev, DRIVER_NAME); 593 if (ret) 594 return ret; 595 596 ret = -ENOMEM; 597 cirrus = devm_drm_dev_alloc(&pdev->dev, &cirrus_driver, 598 struct cirrus_device, dev); 599 if (IS_ERR(cirrus)) 600 return PTR_ERR(cirrus); 601 602 dev = &cirrus->dev; 603 604 cirrus->vram = devm_ioremap(&pdev->dev, pci_resource_start(pdev, 0), 605 pci_resource_len(pdev, 0)); 606 if (cirrus->vram == NULL) 607 return -ENOMEM; 608 609 cirrus->mmio = devm_ioremap(&pdev->dev, pci_resource_start(pdev, 1), 610 pci_resource_len(pdev, 1)); 611 if (cirrus->mmio == NULL) 612 return -ENOMEM; 613 614 ret = cirrus_mode_config_init(cirrus); 615 if (ret) 616 return ret; 617 618 ret = cirrus_pipe_init(cirrus); 619 if (ret < 0) 620 return ret; 621 622 drm_mode_config_reset(dev); 623 624 pci_set_drvdata(pdev, dev); 625 ret = drm_dev_register(dev, 0); 626 if (ret) 627 return ret; 628 629 drm_client_setup(dev, NULL); 630 return 0; 631 } 632 633 static void cirrus_pci_remove(struct pci_dev *pdev) 634 { 635 struct drm_device *dev = pci_get_drvdata(pdev); 636 637 drm_dev_unplug(dev); 638 drm_atomic_helper_shutdown(dev); 639 } 640 641 static void cirrus_pci_shutdown(struct pci_dev *pdev) 642 { 643 drm_atomic_helper_shutdown(pci_get_drvdata(pdev)); 644 } 645 646 static const struct pci_device_id pciidlist[] = { 647 { 648 .vendor = PCI_VENDOR_ID_CIRRUS, 649 .device = PCI_DEVICE_ID_CIRRUS_5446, 650 /* only bind to the cirrus chip in qemu */ 651 .subvendor = PCI_SUBVENDOR_ID_REDHAT_QUMRANET, 652 .subdevice = PCI_SUBDEVICE_ID_QEMU, 653 }, { 654 .vendor = PCI_VENDOR_ID_CIRRUS, 655 .device = PCI_DEVICE_ID_CIRRUS_5446, 656 .subvendor = PCI_VENDOR_ID_XEN, 657 .subdevice = 0x0001, 658 }, 659 { /* end if list */ } 660 }; 661 662 static struct pci_driver cirrus_pci_driver = { 663 .name = DRIVER_NAME, 664 .id_table = pciidlist, 665 .probe = cirrus_pci_probe, 666 .remove = cirrus_pci_remove, 667 .shutdown = cirrus_pci_shutdown, 668 }; 669 670 drm_module_pci_driver(cirrus_pci_driver) 671 672 MODULE_DEVICE_TABLE(pci, pciidlist); 673 MODULE_DESCRIPTION("Cirrus driver for QEMU emulated device"); 674 MODULE_LICENSE("GPL"); 675