1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright 2012-2019 Red Hat 4 * 5 * This file is subject to the terms and conditions of the GNU General 6 * Public License version 2. See the file COPYING in the main 7 * directory of this archive for more details. 8 * 9 * Authors: Matthew Garrett 10 * Dave Airlie 11 * Gerd Hoffmann 12 * 13 * Portions of this code derived from cirrusfb.c: 14 * drivers/video/cirrusfb.c - driver for Cirrus Logic chipsets 15 * 16 * Copyright 1999-2001 Jeff Garzik <jgarzik@pobox.com> 17 */ 18 19 #include <linux/aperture.h> 20 #include <linux/iosys-map.h> 21 #include <linux/module.h> 22 #include <linux/pci.h> 23 24 #include <video/cirrus.h> 25 #include <video/vga.h> 26 27 #include <drm/clients/drm_client_setup.h> 28 #include <drm/drm_atomic.h> 29 #include <drm/drm_atomic_helper.h> 30 #include <drm/drm_atomic_state_helper.h> 31 #include <drm/drm_connector.h> 32 #include <drm/drm_damage_helper.h> 33 #include <drm/drm_drv.h> 34 #include <drm/drm_edid.h> 35 #include <drm/drm_fbdev_shmem.h> 36 #include <drm/drm_file.h> 37 #include <drm/drm_format_helper.h> 38 #include <drm/drm_fourcc.h> 39 #include <drm/drm_framebuffer.h> 40 #include <drm/drm_gem_atomic_helper.h> 41 #include <drm/drm_gem_framebuffer_helper.h> 42 #include <drm/drm_gem_shmem_helper.h> 43 #include <drm/drm_ioctl.h> 44 #include <drm/drm_managed.h> 45 #include <drm/drm_modeset_helper_vtables.h> 46 #include <drm/drm_module.h> 47 #include <drm/drm_probe_helper.h> 48 49 #define DRIVER_NAME "cirrus-qemu" 50 #define DRIVER_DESC "qemu cirrus vga" 51 #define DRIVER_MAJOR 2 52 #define DRIVER_MINOR 0 53 54 #define CIRRUS_MAX_PITCH (0x1FF << 3) /* (4096 - 1) & ~111b bytes */ 55 #define CIRRUS_VRAM_SIZE (4 * 1024 * 1024) /* 4 MB */ 56 57 struct cirrus_device { 58 struct drm_device dev; 59 60 /* modesetting pipeline */ 61 struct drm_plane primary_plane; 62 struct drm_crtc crtc; 63 struct drm_encoder encoder; 64 struct drm_connector connector; 65 66 /* HW resources */ 67 void __iomem *vram; 68 void __iomem *mmio; 69 }; 70 71 #define to_cirrus(_dev) container_of(_dev, struct cirrus_device, dev) 72 73 /* ------------------------------------------------------------------ */ 74 /* 75 * The meat of this driver. The core passes us a mode and we have to program 76 * it. The modesetting here is the bare minimum required to satisfy the qemu 77 * emulation of this hardware, and running this against a real device is 78 * likely to result in an inadequately programmed mode. We've already had 79 * the opportunity to modify the mode, so whatever we receive here should 80 * be something that can be correctly programmed and displayed 81 */ 82 83 #define SEQ_INDEX 4 84 #define SEQ_DATA 5 85 86 static u8 rreg_seq(struct cirrus_device *cirrus, u8 reg) 87 { 88 iowrite8(reg, cirrus->mmio + SEQ_INDEX); 89 return ioread8(cirrus->mmio + SEQ_DATA); 90 } 91 92 static void wreg_seq(struct cirrus_device *cirrus, u8 reg, u8 val) 93 { 94 iowrite8(reg, cirrus->mmio + SEQ_INDEX); 95 iowrite8(val, cirrus->mmio + SEQ_DATA); 96 } 97 98 #define CRT_INDEX 0x14 99 #define CRT_DATA 0x15 100 101 static u8 rreg_crt(struct cirrus_device *cirrus, u8 reg) 102 { 103 iowrite8(reg, cirrus->mmio + CRT_INDEX); 104 return ioread8(cirrus->mmio + CRT_DATA); 105 } 106 107 static void wreg_crt(struct cirrus_device *cirrus, u8 reg, u8 val) 108 { 109 iowrite8(reg, cirrus->mmio + CRT_INDEX); 110 iowrite8(val, cirrus->mmio + CRT_DATA); 111 } 112 113 #define GFX_INDEX 0xe 114 #define GFX_DATA 0xf 115 116 static void wreg_gfx(struct cirrus_device *cirrus, u8 reg, u8 val) 117 { 118 iowrite8(reg, cirrus->mmio + GFX_INDEX); 119 iowrite8(val, cirrus->mmio + GFX_DATA); 120 } 121 122 #define VGA_DAC_MASK 0x06 123 124 static void wreg_hdr(struct cirrus_device *cirrus, u8 val) 125 { 126 ioread8(cirrus->mmio + VGA_DAC_MASK); 127 ioread8(cirrus->mmio + VGA_DAC_MASK); 128 ioread8(cirrus->mmio + VGA_DAC_MASK); 129 ioread8(cirrus->mmio + VGA_DAC_MASK); 130 iowrite8(val, cirrus->mmio + VGA_DAC_MASK); 131 } 132 133 static void cirrus_set_start_address(struct cirrus_device *cirrus, u32 offset) 134 { 135 u32 addr; 136 u8 tmp; 137 138 addr = offset >> 2; 139 wreg_crt(cirrus, 0x0c, (u8)((addr >> 8) & 0xff)); 140 wreg_crt(cirrus, 0x0d, (u8)(addr & 0xff)); 141 142 tmp = rreg_crt(cirrus, 0x1b); 143 tmp &= 0xf2; 144 tmp |= (addr >> 16) & 0x01; 145 tmp |= (addr >> 15) & 0x0c; 146 wreg_crt(cirrus, 0x1b, tmp); 147 148 tmp = rreg_crt(cirrus, 0x1d); 149 tmp &= 0x7f; 150 tmp |= (addr >> 12) & 0x80; 151 wreg_crt(cirrus, 0x1d, tmp); 152 } 153 154 static void cirrus_mode_set(struct cirrus_device *cirrus, 155 struct drm_display_mode *mode) 156 { 157 int hsyncstart, hsyncend, htotal, hdispend; 158 int vtotal, vdispend; 159 int tmp; 160 161 htotal = mode->htotal / 8; 162 hsyncend = mode->hsync_end / 8; 163 hsyncstart = mode->hsync_start / 8; 164 hdispend = mode->hdisplay / 8; 165 166 vtotal = mode->vtotal; 167 vdispend = mode->vdisplay; 168 169 vdispend -= 1; 170 vtotal -= 2; 171 172 htotal -= 5; 173 hdispend -= 1; 174 hsyncstart += 1; 175 hsyncend += 1; 176 177 wreg_crt(cirrus, VGA_CRTC_V_SYNC_END, 0x20); 178 wreg_crt(cirrus, VGA_CRTC_H_TOTAL, htotal); 179 wreg_crt(cirrus, VGA_CRTC_H_DISP, hdispend); 180 wreg_crt(cirrus, VGA_CRTC_H_SYNC_START, hsyncstart); 181 wreg_crt(cirrus, VGA_CRTC_H_SYNC_END, hsyncend); 182 wreg_crt(cirrus, VGA_CRTC_V_TOTAL, vtotal & 0xff); 183 wreg_crt(cirrus, VGA_CRTC_V_DISP_END, vdispend & 0xff); 184 185 tmp = 0x40; 186 if ((vdispend + 1) & 512) 187 tmp |= 0x20; 188 wreg_crt(cirrus, VGA_CRTC_MAX_SCAN, tmp); 189 190 /* 191 * Overflow bits for values that don't fit in the standard registers 192 */ 193 tmp = 0x10; 194 if (vtotal & 0x100) 195 tmp |= 0x01; 196 if (vdispend & 0x100) 197 tmp |= 0x02; 198 if ((vdispend + 1) & 0x100) 199 tmp |= 0x08; 200 if (vtotal & 0x200) 201 tmp |= 0x20; 202 if (vdispend & 0x200) 203 tmp |= 0x40; 204 wreg_crt(cirrus, VGA_CRTC_OVERFLOW, tmp); 205 206 tmp = 0; 207 208 /* More overflow bits */ 209 210 if ((htotal + 5) & 0x40) 211 tmp |= 0x10; 212 if ((htotal + 5) & 0x80) 213 tmp |= 0x20; 214 if (vtotal & 0x100) 215 tmp |= 0x40; 216 if (vtotal & 0x200) 217 tmp |= 0x80; 218 219 wreg_crt(cirrus, CL_CRT1A, tmp); 220 221 /* Disable Hercules/CGA compatibility */ 222 wreg_crt(cirrus, VGA_CRTC_MODE, 0x03); 223 } 224 225 static void cirrus_format_set(struct cirrus_device *cirrus, 226 const struct drm_format_info *format) 227 { 228 u8 sr07, hdr; 229 230 sr07 = rreg_seq(cirrus, 0x07); 231 sr07 &= 0xe0; 232 233 switch (format->format) { 234 case DRM_FORMAT_C8: 235 sr07 |= 0x11; 236 hdr = 0x00; 237 break; 238 case DRM_FORMAT_RGB565: 239 sr07 |= 0x17; 240 hdr = 0xc1; 241 break; 242 case DRM_FORMAT_RGB888: 243 sr07 |= 0x15; 244 hdr = 0xc5; 245 break; 246 case DRM_FORMAT_XRGB8888: 247 sr07 |= 0x19; 248 hdr = 0xc5; 249 break; 250 default: 251 return; 252 } 253 254 wreg_seq(cirrus, 0x7, sr07); 255 256 /* Enable high-colour modes */ 257 wreg_gfx(cirrus, VGA_GFX_MODE, 0x40); 258 259 /* And set graphics mode */ 260 wreg_gfx(cirrus, VGA_GFX_MISC, 0x01); 261 262 wreg_hdr(cirrus, hdr); 263 } 264 265 static void cirrus_pitch_set(struct cirrus_device *cirrus, unsigned int pitch) 266 { 267 u8 cr13, cr1b; 268 269 /* Program the pitch */ 270 cr13 = pitch / 8; 271 wreg_crt(cirrus, VGA_CRTC_OFFSET, cr13); 272 273 /* Enable extended blanking and pitch bits, and enable full memory */ 274 cr1b = 0x22; 275 cr1b |= (pitch >> 7) & 0x10; 276 wreg_crt(cirrus, 0x1b, cr1b); 277 278 cirrus_set_start_address(cirrus, 0); 279 } 280 281 /* ------------------------------------------------------------------ */ 282 /* cirrus display pipe */ 283 284 static const uint32_t cirrus_primary_plane_formats[] = { 285 DRM_FORMAT_RGB565, 286 DRM_FORMAT_RGB888, 287 DRM_FORMAT_XRGB8888, 288 }; 289 290 static const uint64_t cirrus_primary_plane_format_modifiers[] = { 291 DRM_FORMAT_MOD_LINEAR, 292 DRM_FORMAT_MOD_INVALID 293 }; 294 295 static int cirrus_primary_plane_helper_atomic_check(struct drm_plane *plane, 296 struct drm_atomic_state *state) 297 { 298 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); 299 struct drm_framebuffer *fb = new_plane_state->fb; 300 struct drm_crtc *new_crtc = new_plane_state->crtc; 301 struct drm_crtc_state *new_crtc_state = NULL; 302 int ret; 303 304 if (new_crtc) 305 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc); 306 307 ret = drm_atomic_helper_check_plane_state(new_plane_state, new_crtc_state, 308 DRM_PLANE_NO_SCALING, 309 DRM_PLANE_NO_SCALING, 310 false, false); 311 if (ret) 312 return ret; 313 else if (!new_plane_state->visible) 314 return 0; 315 316 /* validate size constraints */ 317 if (fb->pitches[0] > CIRRUS_MAX_PITCH) 318 return -EINVAL; 319 else if (fb->pitches[0] > CIRRUS_VRAM_SIZE / fb->height) 320 return -EINVAL; 321 322 return 0; 323 } 324 325 static void cirrus_primary_plane_helper_atomic_update(struct drm_plane *plane, 326 struct drm_atomic_state *state) 327 { 328 struct cirrus_device *cirrus = to_cirrus(plane->dev); 329 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); 330 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state); 331 struct drm_framebuffer *fb = plane_state->fb; 332 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane); 333 struct drm_framebuffer *old_fb = old_plane_state->fb; 334 struct iosys_map vaddr = IOSYS_MAP_INIT_VADDR_IOMEM(cirrus->vram); 335 struct drm_atomic_helper_damage_iter iter; 336 struct drm_rect damage; 337 int idx; 338 339 if (!fb) 340 return; 341 342 if (!drm_dev_enter(&cirrus->dev, &idx)) 343 return; 344 345 if (!old_fb || old_fb->format != fb->format) 346 cirrus_format_set(cirrus, fb->format); 347 if (!old_fb || old_fb->pitches[0] != fb->pitches[0]) 348 cirrus_pitch_set(cirrus, fb->pitches[0]); 349 350 drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state); 351 drm_atomic_for_each_plane_damage(&iter, &damage) { 352 unsigned int offset = drm_fb_clip_offset(fb->pitches[0], fb->format, &damage); 353 struct iosys_map dst = IOSYS_MAP_INIT_OFFSET(&vaddr, offset); 354 355 drm_fb_memcpy(&dst, fb->pitches, shadow_plane_state->data, fb, &damage); 356 } 357 358 drm_dev_exit(idx); 359 } 360 361 static const struct drm_plane_helper_funcs cirrus_primary_plane_helper_funcs = { 362 DRM_GEM_SHADOW_PLANE_HELPER_FUNCS, 363 .atomic_check = cirrus_primary_plane_helper_atomic_check, 364 .atomic_update = cirrus_primary_plane_helper_atomic_update, 365 }; 366 367 static const struct drm_plane_funcs cirrus_primary_plane_funcs = { 368 .update_plane = drm_atomic_helper_update_plane, 369 .disable_plane = drm_atomic_helper_disable_plane, 370 .destroy = drm_plane_cleanup, 371 DRM_GEM_SHADOW_PLANE_FUNCS, 372 }; 373 374 static int cirrus_crtc_helper_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state) 375 { 376 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 377 int ret; 378 379 if (!crtc_state->enable) 380 return 0; 381 382 ret = drm_atomic_helper_check_crtc_primary_plane(crtc_state); 383 if (ret) 384 return ret; 385 386 return 0; 387 } 388 389 static void cirrus_crtc_helper_atomic_enable(struct drm_crtc *crtc, 390 struct drm_atomic_state *state) 391 { 392 struct cirrus_device *cirrus = to_cirrus(crtc->dev); 393 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 394 int idx; 395 396 if (!drm_dev_enter(&cirrus->dev, &idx)) 397 return; 398 399 cirrus_mode_set(cirrus, &crtc_state->mode); 400 401 #ifdef CONFIG_HAS_IOPORT 402 /* Unblank (needed on S3 resume, vgabios doesn't do it then) */ 403 outb(VGA_AR_ENABLE_DISPLAY, VGA_ATT_W); 404 #endif 405 406 drm_dev_exit(idx); 407 } 408 409 static const struct drm_crtc_helper_funcs cirrus_crtc_helper_funcs = { 410 .atomic_check = cirrus_crtc_helper_atomic_check, 411 .atomic_enable = cirrus_crtc_helper_atomic_enable, 412 }; 413 414 static const struct drm_crtc_funcs cirrus_crtc_funcs = { 415 .reset = drm_atomic_helper_crtc_reset, 416 .destroy = drm_crtc_cleanup, 417 .set_config = drm_atomic_helper_set_config, 418 .page_flip = drm_atomic_helper_page_flip, 419 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 420 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 421 }; 422 423 static const struct drm_encoder_funcs cirrus_encoder_funcs = { 424 .destroy = drm_encoder_cleanup, 425 }; 426 427 static int cirrus_connector_helper_get_modes(struct drm_connector *connector) 428 { 429 int count; 430 431 count = drm_add_modes_noedid(connector, 432 connector->dev->mode_config.max_width, 433 connector->dev->mode_config.max_height); 434 drm_set_preferred_mode(connector, 1024, 768); 435 return count; 436 } 437 438 static const struct drm_connector_helper_funcs cirrus_connector_helper_funcs = { 439 .get_modes = cirrus_connector_helper_get_modes, 440 }; 441 442 static const struct drm_connector_funcs cirrus_connector_funcs = { 443 .fill_modes = drm_helper_probe_single_connector_modes, 444 .destroy = drm_connector_cleanup, 445 .reset = drm_atomic_helper_connector_reset, 446 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 447 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 448 }; 449 450 static int cirrus_pipe_init(struct cirrus_device *cirrus) 451 { 452 struct drm_device *dev = &cirrus->dev; 453 struct drm_plane *primary_plane; 454 struct drm_crtc *crtc; 455 struct drm_encoder *encoder; 456 struct drm_connector *connector; 457 int ret; 458 459 primary_plane = &cirrus->primary_plane; 460 ret = drm_universal_plane_init(dev, primary_plane, 0, 461 &cirrus_primary_plane_funcs, 462 cirrus_primary_plane_formats, 463 ARRAY_SIZE(cirrus_primary_plane_formats), 464 cirrus_primary_plane_format_modifiers, 465 DRM_PLANE_TYPE_PRIMARY, NULL); 466 if (ret) 467 return ret; 468 drm_plane_helper_add(primary_plane, &cirrus_primary_plane_helper_funcs); 469 drm_plane_enable_fb_damage_clips(primary_plane); 470 471 crtc = &cirrus->crtc; 472 ret = drm_crtc_init_with_planes(dev, crtc, primary_plane, NULL, 473 &cirrus_crtc_funcs, NULL); 474 if (ret) 475 return ret; 476 drm_crtc_helper_add(crtc, &cirrus_crtc_helper_funcs); 477 478 encoder = &cirrus->encoder; 479 ret = drm_encoder_init(dev, encoder, &cirrus_encoder_funcs, 480 DRM_MODE_ENCODER_VIRTUAL, NULL); 481 if (ret) 482 return ret; 483 encoder->possible_crtcs = drm_crtc_mask(crtc); 484 485 connector = &cirrus->connector; 486 ret = drm_connector_init(dev, connector, &cirrus_connector_funcs, 487 DRM_MODE_CONNECTOR_VIRTUAL); 488 if (ret) 489 return ret; 490 drm_connector_helper_add(connector, &cirrus_connector_helper_funcs); 491 492 ret = drm_connector_attach_encoder(connector, encoder); 493 if (ret) 494 return ret; 495 496 return 0; 497 } 498 499 /* ------------------------------------------------------------------ */ 500 /* cirrus framebuffers & mode config */ 501 502 static enum drm_mode_status cirrus_mode_config_mode_valid(struct drm_device *dev, 503 const struct drm_display_mode *mode) 504 { 505 const struct drm_format_info *format = drm_format_info(DRM_FORMAT_XRGB8888); 506 u64 pitch; 507 508 if (drm_WARN_ON_ONCE(dev, !format)) 509 return MODE_ERROR; /* driver bug */ 510 511 pitch = drm_format_info_min_pitch(format, 0, mode->hdisplay); 512 if (!pitch) 513 return MODE_BAD_WIDTH; 514 if (pitch > CIRRUS_MAX_PITCH) 515 return MODE_BAD_WIDTH; /* maximum programmable pitch */ 516 if (pitch > CIRRUS_VRAM_SIZE / mode->vdisplay) 517 return MODE_MEM; 518 519 return MODE_OK; 520 } 521 522 static const struct drm_mode_config_funcs cirrus_mode_config_funcs = { 523 .fb_create = drm_gem_fb_create_with_dirty, 524 .mode_valid = cirrus_mode_config_mode_valid, 525 .atomic_check = drm_atomic_helper_check, 526 .atomic_commit = drm_atomic_helper_commit, 527 }; 528 529 static int cirrus_mode_config_init(struct cirrus_device *cirrus) 530 { 531 struct drm_device *dev = &cirrus->dev; 532 int ret; 533 534 ret = drmm_mode_config_init(dev); 535 if (ret) 536 return ret; 537 538 dev->mode_config.min_width = 0; 539 dev->mode_config.min_height = 0; 540 dev->mode_config.max_width = CIRRUS_MAX_PITCH / 2; 541 dev->mode_config.max_height = 1024; 542 dev->mode_config.preferred_depth = 16; 543 dev->mode_config.prefer_shadow = 0; 544 dev->mode_config.funcs = &cirrus_mode_config_funcs; 545 546 return 0; 547 } 548 549 /* ------------------------------------------------------------------ */ 550 551 DEFINE_DRM_GEM_FOPS(cirrus_fops); 552 553 static const struct drm_driver cirrus_driver = { 554 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, 555 556 .name = DRIVER_NAME, 557 .desc = DRIVER_DESC, 558 .major = DRIVER_MAJOR, 559 .minor = DRIVER_MINOR, 560 561 .fops = &cirrus_fops, 562 DRM_GEM_SHMEM_DRIVER_OPS, 563 DRM_FBDEV_SHMEM_DRIVER_OPS, 564 }; 565 566 static int cirrus_pci_probe(struct pci_dev *pdev, 567 const struct pci_device_id *ent) 568 { 569 struct drm_device *dev; 570 struct cirrus_device *cirrus; 571 int ret; 572 573 ret = aperture_remove_conflicting_pci_devices(pdev, cirrus_driver.name); 574 if (ret) 575 return ret; 576 577 ret = pcim_enable_device(pdev); 578 if (ret) 579 return ret; 580 581 ret = pcim_request_all_regions(pdev, DRIVER_NAME); 582 if (ret) 583 return ret; 584 585 ret = -ENOMEM; 586 cirrus = devm_drm_dev_alloc(&pdev->dev, &cirrus_driver, 587 struct cirrus_device, dev); 588 if (IS_ERR(cirrus)) 589 return PTR_ERR(cirrus); 590 591 dev = &cirrus->dev; 592 593 cirrus->vram = devm_ioremap(&pdev->dev, pci_resource_start(pdev, 0), 594 pci_resource_len(pdev, 0)); 595 if (cirrus->vram == NULL) 596 return -ENOMEM; 597 598 cirrus->mmio = devm_ioremap(&pdev->dev, pci_resource_start(pdev, 1), 599 pci_resource_len(pdev, 1)); 600 if (cirrus->mmio == NULL) 601 return -ENOMEM; 602 603 ret = cirrus_mode_config_init(cirrus); 604 if (ret) 605 return ret; 606 607 ret = cirrus_pipe_init(cirrus); 608 if (ret < 0) 609 return ret; 610 611 drm_mode_config_reset(dev); 612 613 pci_set_drvdata(pdev, dev); 614 ret = drm_dev_register(dev, 0); 615 if (ret) 616 return ret; 617 618 drm_client_setup(dev, NULL); 619 return 0; 620 } 621 622 static void cirrus_pci_remove(struct pci_dev *pdev) 623 { 624 struct drm_device *dev = pci_get_drvdata(pdev); 625 626 drm_dev_unplug(dev); 627 drm_atomic_helper_shutdown(dev); 628 } 629 630 static void cirrus_pci_shutdown(struct pci_dev *pdev) 631 { 632 drm_atomic_helper_shutdown(pci_get_drvdata(pdev)); 633 } 634 635 static const struct pci_device_id pciidlist[] = { 636 { 637 .vendor = PCI_VENDOR_ID_CIRRUS, 638 .device = PCI_DEVICE_ID_CIRRUS_5446, 639 /* only bind to the cirrus chip in qemu */ 640 .subvendor = PCI_SUBVENDOR_ID_REDHAT_QUMRANET, 641 .subdevice = PCI_SUBDEVICE_ID_QEMU, 642 }, { 643 .vendor = PCI_VENDOR_ID_CIRRUS, 644 .device = PCI_DEVICE_ID_CIRRUS_5446, 645 .subvendor = PCI_VENDOR_ID_XEN, 646 .subdevice = 0x0001, 647 }, 648 { /* end if list */ } 649 }; 650 651 static struct pci_driver cirrus_pci_driver = { 652 .name = DRIVER_NAME, 653 .id_table = pciidlist, 654 .probe = cirrus_pci_probe, 655 .remove = cirrus_pci_remove, 656 .shutdown = cirrus_pci_shutdown, 657 }; 658 659 drm_module_pci_driver(cirrus_pci_driver) 660 661 MODULE_DEVICE_TABLE(pci, pciidlist); 662 MODULE_DESCRIPTION("Cirrus driver for QEMU emulated device"); 663 MODULE_LICENSE("GPL"); 664