1 // SPDX-License-Identifier: GPL-2.0-or-later 2 3 #include <linux/bug.h> 4 #include <linux/aperture.h> 5 #include <linux/module.h> 6 #include <linux/pci.h> 7 8 #include <drm/clients/drm_client_setup.h> 9 #include <drm/drm_atomic.h> 10 #include <drm/drm_atomic_helper.h> 11 #include <drm/drm_damage_helper.h> 12 #include <drm/drm_drv.h> 13 #include <drm/drm_edid.h> 14 #include <drm/drm_fbdev_shmem.h> 15 #include <drm/drm_fourcc.h> 16 #include <drm/drm_framebuffer.h> 17 #include <drm/drm_gem_atomic_helper.h> 18 #include <drm/drm_gem_framebuffer_helper.h> 19 #include <drm/drm_gem_shmem_helper.h> 20 #include <drm/drm_managed.h> 21 #include <drm/drm_module.h> 22 #include <drm/drm_panic.h> 23 #include <drm/drm_plane_helper.h> 24 #include <drm/drm_probe_helper.h> 25 #include <drm/drm_vblank.h> 26 #include <drm/drm_vblank_helper.h> 27 28 #include <video/vga.h> 29 30 /* ---------------------------------------------------------------------- */ 31 32 #define VBE_DISPI_IOPORT_INDEX 0x01CE 33 #define VBE_DISPI_IOPORT_DATA 0x01CF 34 35 #define VBE_DISPI_INDEX_ID 0x0 36 #define VBE_DISPI_INDEX_XRES 0x1 37 #define VBE_DISPI_INDEX_YRES 0x2 38 #define VBE_DISPI_INDEX_BPP 0x3 39 #define VBE_DISPI_INDEX_ENABLE 0x4 40 #define VBE_DISPI_INDEX_BANK 0x5 41 #define VBE_DISPI_INDEX_VIRT_WIDTH 0x6 42 #define VBE_DISPI_INDEX_VIRT_HEIGHT 0x7 43 #define VBE_DISPI_INDEX_X_OFFSET 0x8 44 #define VBE_DISPI_INDEX_Y_OFFSET 0x9 45 #define VBE_DISPI_INDEX_VIDEO_MEMORY_64K 0xa 46 47 #define VBE_DISPI_ID0 0xB0C0 48 #define VBE_DISPI_ID1 0xB0C1 49 #define VBE_DISPI_ID2 0xB0C2 50 #define VBE_DISPI_ID3 0xB0C3 51 #define VBE_DISPI_ID4 0xB0C4 52 #define VBE_DISPI_ID5 0xB0C5 53 54 #define VBE_DISPI_DISABLED 0x00 55 #define VBE_DISPI_ENABLED 0x01 56 #define VBE_DISPI_GETCAPS 0x02 57 #define VBE_DISPI_8BIT_DAC 0x20 58 #define VBE_DISPI_LFB_ENABLED 0x40 59 #define VBE_DISPI_NOCLEARMEM 0x80 60 61 static int bochs_modeset = -1; 62 static int defx = 1024; 63 static int defy = 768; 64 65 module_param_named(modeset, bochs_modeset, int, 0444); 66 MODULE_PARM_DESC(modeset, "enable/disable kernel modesetting"); 67 68 module_param(defx, int, 0444); 69 module_param(defy, int, 0444); 70 MODULE_PARM_DESC(defx, "default x resolution"); 71 MODULE_PARM_DESC(defy, "default y resolution"); 72 73 /* ---------------------------------------------------------------------- */ 74 75 enum bochs_types { 76 BOCHS_QEMU_STDVGA, 77 BOCHS_SIMICS, 78 BOCHS_UNKNOWN, 79 }; 80 81 struct bochs_device { 82 struct drm_device dev; 83 84 /* hw */ 85 void __iomem *mmio; 86 int ioports; 87 void __iomem *fb_map; 88 unsigned long fb_base; 89 unsigned long fb_size; 90 unsigned long qext_size; 91 92 /* mode */ 93 u16 xres; 94 u16 yres; 95 u16 yres_virtual; 96 u32 stride; 97 u32 bpp; 98 99 /* drm */ 100 struct drm_plane primary_plane; 101 struct drm_crtc crtc; 102 struct drm_encoder encoder; 103 struct drm_connector connector; 104 }; 105 106 static struct bochs_device *to_bochs_device(const struct drm_device *dev) 107 { 108 return container_of(dev, struct bochs_device, dev); 109 } 110 111 /* ---------------------------------------------------------------------- */ 112 113 static __always_inline bool bochs_uses_mmio(struct bochs_device *bochs) 114 { 115 return !IS_ENABLED(CONFIG_HAS_IOPORT) || bochs->mmio; 116 } 117 118 static void bochs_vga_writeb(struct bochs_device *bochs, u16 ioport, u8 val) 119 { 120 if (WARN_ON(ioport < 0x3c0 || ioport > 0x3df)) 121 return; 122 123 if (bochs_uses_mmio(bochs)) { 124 int offset = ioport - 0x3c0 + 0x400; 125 126 writeb(val, bochs->mmio + offset); 127 } else { 128 outb(val, ioport); 129 } 130 } 131 132 static u8 bochs_vga_readb(struct bochs_device *bochs, u16 ioport) 133 { 134 if (WARN_ON(ioport < 0x3c0 || ioport > 0x3df)) 135 return 0xff; 136 137 if (bochs_uses_mmio(bochs)) { 138 int offset = ioport - 0x3c0 + 0x400; 139 140 return readb(bochs->mmio + offset); 141 } else { 142 return inb(ioport); 143 } 144 } 145 146 static u16 bochs_dispi_read(struct bochs_device *bochs, u16 reg) 147 { 148 u16 ret = 0; 149 150 if (bochs_uses_mmio(bochs)) { 151 int offset = 0x500 + (reg << 1); 152 153 ret = readw(bochs->mmio + offset); 154 } else { 155 outw(reg, VBE_DISPI_IOPORT_INDEX); 156 ret = inw(VBE_DISPI_IOPORT_DATA); 157 } 158 return ret; 159 } 160 161 static void bochs_dispi_write(struct bochs_device *bochs, u16 reg, u16 val) 162 { 163 if (bochs_uses_mmio(bochs)) { 164 int offset = 0x500 + (reg << 1); 165 166 writew(val, bochs->mmio + offset); 167 } else { 168 outw(reg, VBE_DISPI_IOPORT_INDEX); 169 outw(val, VBE_DISPI_IOPORT_DATA); 170 } 171 } 172 173 static void bochs_hw_set_big_endian(struct bochs_device *bochs) 174 { 175 if (bochs->qext_size < 8) 176 return; 177 178 writel(0xbebebebe, bochs->mmio + 0x604); 179 } 180 181 static void bochs_hw_set_little_endian(struct bochs_device *bochs) 182 { 183 if (bochs->qext_size < 8) 184 return; 185 186 writel(0x1e1e1e1e, bochs->mmio + 0x604); 187 } 188 189 #ifdef __BIG_ENDIAN 190 #define bochs_hw_set_native_endian(_b) bochs_hw_set_big_endian(_b) 191 #else 192 #define bochs_hw_set_native_endian(_b) bochs_hw_set_little_endian(_b) 193 #endif 194 195 static int bochs_get_edid_block(void *data, u8 *buf, unsigned int block, size_t len) 196 { 197 struct bochs_device *bochs = data; 198 size_t i, start = block * EDID_LENGTH; 199 200 if (!bochs->mmio) 201 return -1; 202 203 if (start + len > 0x400 /* vga register offset */) 204 return -1; 205 206 for (i = 0; i < len; i++) 207 buf[i] = readb(bochs->mmio + start + i); 208 209 return 0; 210 } 211 212 static const struct drm_edid *bochs_hw_read_edid(struct drm_connector *connector) 213 { 214 struct drm_device *dev = connector->dev; 215 struct bochs_device *bochs = to_bochs_device(dev); 216 u8 header[8]; 217 218 /* check header to detect whenever edid support is enabled in qemu */ 219 bochs_get_edid_block(bochs, header, 0, ARRAY_SIZE(header)); 220 if (drm_edid_header_is_valid(header) != 8) 221 return NULL; 222 223 drm_dbg(dev, "Found EDID data blob.\n"); 224 225 return drm_edid_read_custom(connector, bochs_get_edid_block, bochs); 226 } 227 228 static int bochs_hw_init(struct bochs_device *bochs) 229 { 230 struct drm_device *dev = &bochs->dev; 231 struct pci_dev *pdev = to_pci_dev(dev->dev); 232 unsigned long addr, size, mem, ioaddr, iosize; 233 u16 id; 234 235 if (pdev->resource[2].flags & IORESOURCE_MEM) { 236 ioaddr = pci_resource_start(pdev, 2); 237 iosize = pci_resource_len(pdev, 2); 238 /* mmio bar with vga and bochs registers present */ 239 if (!devm_request_mem_region(&pdev->dev, ioaddr, iosize, "bochs-drm")) { 240 DRM_ERROR("Cannot request mmio region\n"); 241 return -EBUSY; 242 } 243 bochs->mmio = devm_ioremap(&pdev->dev, ioaddr, iosize); 244 if (bochs->mmio == NULL) { 245 DRM_ERROR("Cannot map mmio region\n"); 246 return -ENOMEM; 247 } 248 } else if (IS_ENABLED(CONFIG_HAS_IOPORT)) { 249 ioaddr = VBE_DISPI_IOPORT_INDEX; 250 iosize = 2; 251 if (!devm_request_region(&pdev->dev, ioaddr, iosize, "bochs-drm")) { 252 DRM_ERROR("Cannot request ioports\n"); 253 return -EBUSY; 254 } 255 bochs->ioports = 1; 256 } else { 257 drm_err(dev, "I/O ports are not supported\n"); 258 return -EIO; 259 } 260 261 id = bochs_dispi_read(bochs, VBE_DISPI_INDEX_ID); 262 mem = bochs_dispi_read(bochs, VBE_DISPI_INDEX_VIDEO_MEMORY_64K) 263 * 64 * 1024; 264 if ((id & 0xfff0) != VBE_DISPI_ID0) { 265 DRM_ERROR("ID mismatch\n"); 266 return -ENODEV; 267 } 268 269 if ((pdev->resource[0].flags & IORESOURCE_MEM) == 0) 270 return -ENODEV; 271 addr = pci_resource_start(pdev, 0); 272 size = pci_resource_len(pdev, 0); 273 if (addr == 0) 274 return -ENODEV; 275 if (size != mem) { 276 DRM_ERROR("Size mismatch: pci=%ld, bochs=%ld\n", 277 size, mem); 278 size = min(size, mem); 279 } 280 281 if (!devm_request_mem_region(&pdev->dev, addr, size, "bochs-drm")) 282 DRM_WARN("Cannot request framebuffer, boot fb still active?\n"); 283 284 bochs->fb_map = devm_ioremap_wc(&pdev->dev, addr, size); 285 if (bochs->fb_map == NULL) { 286 DRM_ERROR("Cannot map framebuffer\n"); 287 return -ENOMEM; 288 } 289 bochs->fb_base = addr; 290 bochs->fb_size = size; 291 292 DRM_INFO("Found bochs VGA, ID 0x%x.\n", id); 293 DRM_INFO("Framebuffer size %ld kB @ 0x%lx, %s @ 0x%lx.\n", 294 size / 1024, addr, 295 bochs->ioports ? "ioports" : "mmio", 296 ioaddr); 297 298 if (bochs->mmio && pdev->revision >= 2) { 299 bochs->qext_size = readl(bochs->mmio + 0x600); 300 if (bochs->qext_size < 4 || bochs->qext_size > iosize) { 301 bochs->qext_size = 0; 302 goto noext; 303 } 304 DRM_DEBUG("Found qemu ext regs, size %ld\n", 305 bochs->qext_size); 306 bochs_hw_set_native_endian(bochs); 307 } 308 309 noext: 310 return 0; 311 } 312 313 static void bochs_hw_blank(struct bochs_device *bochs, bool blank) 314 { 315 DRM_DEBUG_DRIVER("hw_blank %d\n", blank); 316 /* enable color bit (so VGA_IS1_RC access works) */ 317 bochs_vga_writeb(bochs, VGA_MIS_W, VGA_MIS_COLOR); 318 /* discard ar_flip_flop */ 319 (void)bochs_vga_readb(bochs, VGA_IS1_RC); 320 /* blank or unblank; we need only update index and set 0x20 */ 321 bochs_vga_writeb(bochs, VGA_ATT_W, blank ? 0 : 0x20); 322 } 323 324 static void bochs_hw_setmode(struct bochs_device *bochs, struct drm_display_mode *mode) 325 { 326 int idx; 327 328 if (!drm_dev_enter(&bochs->dev, &idx)) 329 return; 330 331 bochs->xres = mode->hdisplay; 332 bochs->yres = mode->vdisplay; 333 bochs->bpp = 32; 334 bochs->stride = mode->hdisplay * (bochs->bpp / 8); 335 bochs->yres_virtual = bochs->fb_size / bochs->stride; 336 337 DRM_DEBUG_DRIVER("%dx%d @ %d bpp, vy %d\n", 338 bochs->xres, bochs->yres, bochs->bpp, 339 bochs->yres_virtual); 340 341 bochs_dispi_write(bochs, VBE_DISPI_INDEX_ENABLE, 0); 342 bochs_dispi_write(bochs, VBE_DISPI_INDEX_BPP, bochs->bpp); 343 bochs_dispi_write(bochs, VBE_DISPI_INDEX_XRES, bochs->xres); 344 bochs_dispi_write(bochs, VBE_DISPI_INDEX_YRES, bochs->yres); 345 bochs_dispi_write(bochs, VBE_DISPI_INDEX_BANK, 0); 346 bochs_dispi_write(bochs, VBE_DISPI_INDEX_VIRT_WIDTH, bochs->xres); 347 bochs_dispi_write(bochs, VBE_DISPI_INDEX_VIRT_HEIGHT, 348 bochs->yres_virtual); 349 bochs_dispi_write(bochs, VBE_DISPI_INDEX_X_OFFSET, 0); 350 bochs_dispi_write(bochs, VBE_DISPI_INDEX_Y_OFFSET, 0); 351 352 bochs_dispi_write(bochs, VBE_DISPI_INDEX_ENABLE, 353 VBE_DISPI_ENABLED | VBE_DISPI_LFB_ENABLED); 354 355 drm_dev_exit(idx); 356 } 357 358 static void bochs_hw_setformat(struct bochs_device *bochs, const struct drm_format_info *format) 359 { 360 int idx; 361 362 if (!drm_dev_enter(&bochs->dev, &idx)) 363 return; 364 365 DRM_DEBUG_DRIVER("format %c%c%c%c\n", 366 (format->format >> 0) & 0xff, 367 (format->format >> 8) & 0xff, 368 (format->format >> 16) & 0xff, 369 (format->format >> 24) & 0xff); 370 371 switch (format->format) { 372 case DRM_FORMAT_XRGB8888: 373 bochs_hw_set_little_endian(bochs); 374 break; 375 case DRM_FORMAT_BGRX8888: 376 bochs_hw_set_big_endian(bochs); 377 break; 378 default: 379 /* should not happen */ 380 DRM_ERROR("%s: Huh? Got framebuffer format 0x%x", 381 __func__, format->format); 382 break; 383 } 384 385 drm_dev_exit(idx); 386 } 387 388 static void bochs_hw_setbase(struct bochs_device *bochs, int x, int y, int stride, u64 addr) 389 { 390 unsigned long offset; 391 unsigned int vx, vy, vwidth, idx; 392 393 if (!drm_dev_enter(&bochs->dev, &idx)) 394 return; 395 396 bochs->stride = stride; 397 offset = (unsigned long)addr + 398 y * bochs->stride + 399 x * (bochs->bpp / 8); 400 vy = offset / bochs->stride; 401 vx = (offset % bochs->stride) * 8 / bochs->bpp; 402 vwidth = stride * 8 / bochs->bpp; 403 404 DRM_DEBUG_DRIVER("x %d, y %d, addr %llx -> offset %lx, vx %d, vy %d\n", 405 x, y, addr, offset, vx, vy); 406 bochs_dispi_write(bochs, VBE_DISPI_INDEX_VIRT_WIDTH, vwidth); 407 bochs_dispi_write(bochs, VBE_DISPI_INDEX_X_OFFSET, vx); 408 bochs_dispi_write(bochs, VBE_DISPI_INDEX_Y_OFFSET, vy); 409 410 drm_dev_exit(idx); 411 } 412 413 /* ---------------------------------------------------------------------- */ 414 415 static const uint32_t bochs_primary_plane_formats[] = { 416 DRM_FORMAT_XRGB8888, 417 DRM_FORMAT_BGRX8888, 418 }; 419 420 static int bochs_primary_plane_helper_atomic_check(struct drm_plane *plane, 421 struct drm_atomic_state *state) 422 { 423 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); 424 struct drm_crtc *new_crtc = new_plane_state->crtc; 425 struct drm_crtc_state *new_crtc_state = NULL; 426 int ret; 427 428 if (new_crtc) 429 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc); 430 431 ret = drm_atomic_helper_check_plane_state(new_plane_state, new_crtc_state, 432 DRM_PLANE_NO_SCALING, 433 DRM_PLANE_NO_SCALING, 434 false, false); 435 if (ret) 436 return ret; 437 else if (!new_plane_state->visible) 438 return 0; 439 440 return 0; 441 } 442 443 static void bochs_primary_plane_helper_atomic_update(struct drm_plane *plane, 444 struct drm_atomic_state *state) 445 { 446 struct drm_device *dev = plane->dev; 447 struct bochs_device *bochs = to_bochs_device(dev); 448 struct drm_plane_state *plane_state = plane->state; 449 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane); 450 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state); 451 struct drm_framebuffer *fb = plane_state->fb; 452 struct drm_atomic_helper_damage_iter iter; 453 struct drm_rect damage; 454 455 if (!fb || !bochs->stride) 456 return; 457 458 drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state); 459 drm_atomic_for_each_plane_damage(&iter, &damage) { 460 struct iosys_map dst = IOSYS_MAP_INIT_VADDR_IOMEM(bochs->fb_map); 461 462 iosys_map_incr(&dst, drm_fb_clip_offset(fb->pitches[0], fb->format, &damage)); 463 drm_fb_memcpy(&dst, fb->pitches, shadow_plane_state->data, fb, &damage); 464 } 465 466 /* Always scanout image at VRAM offset 0 */ 467 bochs_hw_setbase(bochs, 468 plane_state->crtc_x, 469 plane_state->crtc_y, 470 fb->pitches[0], 471 0); 472 bochs_hw_setformat(bochs, fb->format); 473 } 474 475 static int bochs_primary_plane_helper_get_scanout_buffer(struct drm_plane *plane, 476 struct drm_scanout_buffer *sb) 477 { 478 struct bochs_device *bochs = to_bochs_device(plane->dev); 479 struct iosys_map map = IOSYS_MAP_INIT_VADDR_IOMEM(bochs->fb_map); 480 481 if (plane->state && plane->state->fb) { 482 sb->format = plane->state->fb->format; 483 sb->width = plane->state->fb->width; 484 sb->height = plane->state->fb->height; 485 sb->pitch[0] = plane->state->fb->pitches[0]; 486 sb->map[0] = map; 487 return 0; 488 } 489 return -ENODEV; 490 } 491 492 static const struct drm_plane_helper_funcs bochs_primary_plane_helper_funcs = { 493 DRM_GEM_SHADOW_PLANE_HELPER_FUNCS, 494 .atomic_check = bochs_primary_plane_helper_atomic_check, 495 .atomic_update = bochs_primary_plane_helper_atomic_update, 496 .get_scanout_buffer = bochs_primary_plane_helper_get_scanout_buffer, 497 }; 498 499 static const struct drm_plane_funcs bochs_primary_plane_funcs = { 500 .update_plane = drm_atomic_helper_update_plane, 501 .disable_plane = drm_atomic_helper_disable_plane, 502 .destroy = drm_plane_cleanup, 503 DRM_GEM_SHADOW_PLANE_FUNCS 504 }; 505 506 static void bochs_crtc_helper_mode_set_nofb(struct drm_crtc *crtc) 507 { 508 struct bochs_device *bochs = to_bochs_device(crtc->dev); 509 struct drm_crtc_state *crtc_state = crtc->state; 510 511 bochs_hw_setmode(bochs, &crtc_state->mode); 512 } 513 514 static int bochs_crtc_helper_atomic_check(struct drm_crtc *crtc, 515 struct drm_atomic_state *state) 516 { 517 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 518 519 if (!crtc_state->enable) 520 return 0; 521 522 return drm_atomic_helper_check_crtc_primary_plane(crtc_state); 523 } 524 525 static void bochs_crtc_helper_atomic_enable(struct drm_crtc *crtc, 526 struct drm_atomic_state *state) 527 { 528 struct bochs_device *bochs = to_bochs_device(crtc->dev); 529 530 bochs_hw_blank(bochs, false); 531 drm_crtc_vblank_on(crtc); 532 } 533 534 static void bochs_crtc_helper_atomic_disable(struct drm_crtc *crtc, 535 struct drm_atomic_state *crtc_state) 536 { 537 struct bochs_device *bochs = to_bochs_device(crtc->dev); 538 539 drm_crtc_vblank_off(crtc); 540 bochs_hw_blank(bochs, true); 541 } 542 543 static const struct drm_crtc_helper_funcs bochs_crtc_helper_funcs = { 544 .mode_set_nofb = bochs_crtc_helper_mode_set_nofb, 545 .atomic_check = bochs_crtc_helper_atomic_check, 546 .atomic_flush = drm_crtc_vblank_atomic_flush, 547 .atomic_enable = bochs_crtc_helper_atomic_enable, 548 .atomic_disable = bochs_crtc_helper_atomic_disable, 549 }; 550 551 static const struct drm_crtc_funcs bochs_crtc_funcs = { 552 .reset = drm_atomic_helper_crtc_reset, 553 .destroy = drm_crtc_cleanup, 554 .set_config = drm_atomic_helper_set_config, 555 .page_flip = drm_atomic_helper_page_flip, 556 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 557 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 558 DRM_CRTC_VBLANK_TIMER_FUNCS, 559 }; 560 561 static const struct drm_encoder_funcs bochs_encoder_funcs = { 562 .destroy = drm_encoder_cleanup, 563 }; 564 565 static int bochs_connector_helper_get_modes(struct drm_connector *connector) 566 { 567 const struct drm_edid *edid; 568 int count; 569 570 edid = bochs_hw_read_edid(connector); 571 572 if (edid) { 573 drm_edid_connector_update(connector, edid); 574 count = drm_edid_connector_add_modes(connector); 575 drm_edid_free(edid); 576 } else { 577 drm_edid_connector_update(connector, NULL); 578 count = drm_add_modes_noedid(connector, 8192, 8192); 579 drm_set_preferred_mode(connector, defx, defy); 580 } 581 582 return count; 583 } 584 585 static const struct drm_connector_helper_funcs bochs_connector_helper_funcs = { 586 .get_modes = bochs_connector_helper_get_modes, 587 }; 588 589 static const struct drm_connector_funcs bochs_connector_funcs = { 590 .fill_modes = drm_helper_probe_single_connector_modes, 591 .destroy = drm_connector_cleanup, 592 .reset = drm_atomic_helper_connector_reset, 593 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 594 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 595 }; 596 597 static enum drm_mode_status bochs_mode_config_mode_valid(struct drm_device *dev, 598 const struct drm_display_mode *mode) 599 { 600 struct bochs_device *bochs = to_bochs_device(dev); 601 const struct drm_format_info *format = drm_format_info(DRM_FORMAT_XRGB8888); 602 u64 pitch; 603 604 if (drm_WARN_ON(dev, !format)) 605 return MODE_ERROR; 606 607 pitch = drm_format_info_min_pitch(format, 0, mode->hdisplay); 608 if (!pitch) 609 return MODE_BAD_WIDTH; 610 if (mode->vdisplay > DIV_ROUND_DOWN_ULL(bochs->fb_size, pitch)) 611 return MODE_MEM; 612 613 return MODE_OK; 614 } 615 616 static const struct drm_mode_config_funcs bochs_mode_config_funcs = { 617 .fb_create = drm_gem_fb_create_with_dirty, 618 .mode_valid = bochs_mode_config_mode_valid, 619 .atomic_check = drm_atomic_helper_check, 620 .atomic_commit = drm_atomic_helper_commit, 621 }; 622 623 static int bochs_kms_init(struct bochs_device *bochs) 624 { 625 struct drm_device *dev = &bochs->dev; 626 struct drm_plane *primary_plane; 627 struct drm_crtc *crtc; 628 struct drm_connector *connector; 629 struct drm_encoder *encoder; 630 int ret; 631 632 ret = drmm_mode_config_init(dev); 633 if (ret) 634 return ret; 635 636 dev->mode_config.max_width = 8192; 637 dev->mode_config.max_height = 8192; 638 639 dev->mode_config.preferred_depth = 24; 640 dev->mode_config.quirk_addfb_prefer_host_byte_order = true; 641 642 dev->mode_config.funcs = &bochs_mode_config_funcs; 643 644 primary_plane = &bochs->primary_plane; 645 ret = drm_universal_plane_init(dev, primary_plane, 0, 646 &bochs_primary_plane_funcs, 647 bochs_primary_plane_formats, 648 ARRAY_SIZE(bochs_primary_plane_formats), 649 NULL, 650 DRM_PLANE_TYPE_PRIMARY, NULL); 651 if (ret) 652 return ret; 653 drm_plane_helper_add(primary_plane, &bochs_primary_plane_helper_funcs); 654 drm_plane_enable_fb_damage_clips(primary_plane); 655 656 crtc = &bochs->crtc; 657 ret = drm_crtc_init_with_planes(dev, crtc, primary_plane, NULL, 658 &bochs_crtc_funcs, NULL); 659 if (ret) 660 return ret; 661 drm_crtc_helper_add(crtc, &bochs_crtc_helper_funcs); 662 663 encoder = &bochs->encoder; 664 ret = drm_encoder_init(dev, encoder, &bochs_encoder_funcs, 665 DRM_MODE_ENCODER_VIRTUAL, NULL); 666 if (ret) 667 return ret; 668 encoder->possible_crtcs = drm_crtc_mask(crtc); 669 670 connector = &bochs->connector; 671 ret = drm_connector_init(dev, connector, &bochs_connector_funcs, 672 DRM_MODE_CONNECTOR_VIRTUAL); 673 if (ret) 674 return ret; 675 drm_connector_helper_add(connector, &bochs_connector_helper_funcs); 676 drm_connector_attach_edid_property(connector); 677 drm_connector_attach_encoder(connector, encoder); 678 679 ret = drm_vblank_init(dev, 1); 680 if (ret) 681 return ret; 682 683 drm_mode_config_reset(dev); 684 685 return 0; 686 } 687 688 /* ---------------------------------------------------------------------- */ 689 /* drm interface */ 690 691 static int bochs_load(struct bochs_device *bochs) 692 { 693 int ret; 694 695 ret = bochs_hw_init(bochs); 696 if (ret) 697 return ret; 698 699 ret = bochs_kms_init(bochs); 700 if (ret) 701 return ret; 702 703 return 0; 704 } 705 706 DEFINE_DRM_GEM_FOPS(bochs_fops); 707 708 static const struct drm_driver bochs_driver = { 709 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC, 710 .fops = &bochs_fops, 711 .name = "bochs-drm", 712 .desc = "bochs dispi vga interface (qemu stdvga)", 713 .major = 1, 714 .minor = 0, 715 DRM_GEM_SHMEM_DRIVER_OPS, 716 DRM_FBDEV_SHMEM_DRIVER_OPS, 717 }; 718 719 /* ---------------------------------------------------------------------- */ 720 /* pm interface */ 721 722 #ifdef CONFIG_PM_SLEEP 723 static int bochs_pm_suspend(struct device *dev) 724 { 725 struct drm_device *drm_dev = dev_get_drvdata(dev); 726 727 return drm_mode_config_helper_suspend(drm_dev); 728 } 729 730 static int bochs_pm_resume(struct device *dev) 731 { 732 struct drm_device *drm_dev = dev_get_drvdata(dev); 733 734 return drm_mode_config_helper_resume(drm_dev); 735 } 736 #endif 737 738 static const struct dev_pm_ops bochs_pm_ops = { 739 SET_SYSTEM_SLEEP_PM_OPS(bochs_pm_suspend, 740 bochs_pm_resume) 741 }; 742 743 /* ---------------------------------------------------------------------- */ 744 /* pci interface */ 745 746 static int bochs_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 747 { 748 struct bochs_device *bochs; 749 struct drm_device *dev; 750 int ret; 751 752 ret = aperture_remove_conflicting_pci_devices(pdev, bochs_driver.name); 753 if (ret) 754 return ret; 755 756 bochs = devm_drm_dev_alloc(&pdev->dev, &bochs_driver, struct bochs_device, dev); 757 if (IS_ERR(bochs)) 758 return PTR_ERR(bochs); 759 dev = &bochs->dev; 760 761 ret = pcim_enable_device(pdev); 762 if (ret) 763 goto err_free_dev; 764 765 pci_set_drvdata(pdev, dev); 766 767 ret = bochs_load(bochs); 768 if (ret) 769 goto err_free_dev; 770 771 ret = drm_dev_register(dev, 0); 772 if (ret) 773 goto err_free_dev; 774 775 drm_client_setup(dev, NULL); 776 777 return ret; 778 779 err_free_dev: 780 drm_dev_put(dev); 781 return ret; 782 } 783 784 static void bochs_pci_remove(struct pci_dev *pdev) 785 { 786 struct drm_device *dev = pci_get_drvdata(pdev); 787 788 drm_dev_unplug(dev); 789 drm_atomic_helper_shutdown(dev); 790 } 791 792 static void bochs_pci_shutdown(struct pci_dev *pdev) 793 { 794 drm_atomic_helper_shutdown(pci_get_drvdata(pdev)); 795 } 796 797 static const struct pci_device_id bochs_pci_tbl[] = { 798 { 799 .vendor = 0x1234, 800 .device = 0x1111, 801 .subvendor = PCI_SUBVENDOR_ID_REDHAT_QUMRANET, 802 .subdevice = PCI_SUBDEVICE_ID_QEMU, 803 .driver_data = BOCHS_QEMU_STDVGA, 804 }, 805 { 806 .vendor = 0x1234, 807 .device = 0x1111, 808 .subvendor = PCI_ANY_ID, 809 .subdevice = PCI_ANY_ID, 810 .driver_data = BOCHS_UNKNOWN, 811 }, 812 { 813 .vendor = 0x4321, 814 .device = 0x1111, 815 .subvendor = PCI_ANY_ID, 816 .subdevice = PCI_ANY_ID, 817 .driver_data = BOCHS_SIMICS, 818 }, 819 { /* end of list */ } 820 }; 821 822 static struct pci_driver bochs_pci_driver = { 823 .name = "bochs-drm", 824 .id_table = bochs_pci_tbl, 825 .probe = bochs_pci_probe, 826 .remove = bochs_pci_remove, 827 .shutdown = bochs_pci_shutdown, 828 .driver.pm = &bochs_pm_ops, 829 }; 830 831 /* ---------------------------------------------------------------------- */ 832 /* module init/exit */ 833 834 drm_module_pci_driver_if_modeset(bochs_pci_driver, bochs_modeset); 835 836 MODULE_DEVICE_TABLE(pci, bochs_pci_tbl); 837 MODULE_AUTHOR("Gerd Hoffmann <kraxel@redhat.com>"); 838 MODULE_DESCRIPTION("DRM Support for bochs dispi vga interface (qemu stdvga)"); 839 MODULE_LICENSE("GPL"); 840