1 // SPDX-License-Identifier: GPL-2.0-or-later 2 3 #include <linux/bug.h> 4 #include <linux/aperture.h> 5 #include <linux/module.h> 6 #include <linux/pci.h> 7 8 #include <drm/clients/drm_client_setup.h> 9 #include <drm/drm_atomic.h> 10 #include <drm/drm_atomic_helper.h> 11 #include <drm/drm_damage_helper.h> 12 #include <drm/drm_drv.h> 13 #include <drm/drm_edid.h> 14 #include <drm/drm_fbdev_shmem.h> 15 #include <drm/drm_fourcc.h> 16 #include <drm/drm_framebuffer.h> 17 #include <drm/drm_gem_atomic_helper.h> 18 #include <drm/drm_gem_framebuffer_helper.h> 19 #include <drm/drm_gem_shmem_helper.h> 20 #include <drm/drm_managed.h> 21 #include <drm/drm_module.h> 22 #include <drm/drm_panic.h> 23 #include <drm/drm_plane_helper.h> 24 #include <drm/drm_print.h> 25 #include <drm/drm_probe_helper.h> 26 #include <drm/drm_vblank.h> 27 #include <drm/drm_vblank_helper.h> 28 29 #include <video/vga.h> 30 31 /* ---------------------------------------------------------------------- */ 32 33 #define VBE_DISPI_IOPORT_INDEX 0x01CE 34 #define VBE_DISPI_IOPORT_DATA 0x01CF 35 36 #define VBE_DISPI_INDEX_ID 0x0 37 #define VBE_DISPI_INDEX_XRES 0x1 38 #define VBE_DISPI_INDEX_YRES 0x2 39 #define VBE_DISPI_INDEX_BPP 0x3 40 #define VBE_DISPI_INDEX_ENABLE 0x4 41 #define VBE_DISPI_INDEX_BANK 0x5 42 #define VBE_DISPI_INDEX_VIRT_WIDTH 0x6 43 #define VBE_DISPI_INDEX_VIRT_HEIGHT 0x7 44 #define VBE_DISPI_INDEX_X_OFFSET 0x8 45 #define VBE_DISPI_INDEX_Y_OFFSET 0x9 46 #define VBE_DISPI_INDEX_VIDEO_MEMORY_64K 0xa 47 48 #define VBE_DISPI_ID0 0xB0C0 49 #define VBE_DISPI_ID1 0xB0C1 50 #define VBE_DISPI_ID2 0xB0C2 51 #define VBE_DISPI_ID3 0xB0C3 52 #define VBE_DISPI_ID4 0xB0C4 53 #define VBE_DISPI_ID5 0xB0C5 54 55 #define VBE_DISPI_DISABLED 0x00 56 #define VBE_DISPI_ENABLED 0x01 57 #define VBE_DISPI_GETCAPS 0x02 58 #define VBE_DISPI_8BIT_DAC 0x20 59 #define VBE_DISPI_LFB_ENABLED 0x40 60 #define VBE_DISPI_NOCLEARMEM 0x80 61 62 static int bochs_modeset = -1; 63 static int defx = 1024; 64 static int defy = 768; 65 66 module_param_named(modeset, bochs_modeset, int, 0444); 67 MODULE_PARM_DESC(modeset, "enable/disable kernel modesetting"); 68 69 module_param(defx, int, 0444); 70 module_param(defy, int, 0444); 71 MODULE_PARM_DESC(defx, "default x resolution"); 72 MODULE_PARM_DESC(defy, "default y resolution"); 73 74 /* ---------------------------------------------------------------------- */ 75 76 enum bochs_types { 77 BOCHS_QEMU_STDVGA, 78 BOCHS_SIMICS, 79 BOCHS_UNKNOWN, 80 }; 81 82 struct bochs_device { 83 struct drm_device dev; 84 85 /* hw */ 86 void __iomem *mmio; 87 int ioports; 88 void __iomem *fb_map; 89 unsigned long fb_base; 90 unsigned long fb_size; 91 unsigned long qext_size; 92 93 /* mode */ 94 u16 xres; 95 u16 yres; 96 u16 yres_virtual; 97 u32 stride; 98 u32 bpp; 99 100 /* drm */ 101 struct drm_plane primary_plane; 102 struct drm_crtc crtc; 103 struct drm_encoder encoder; 104 struct drm_connector connector; 105 }; 106 107 static struct bochs_device *to_bochs_device(const struct drm_device *dev) 108 { 109 return container_of(dev, struct bochs_device, dev); 110 } 111 112 /* ---------------------------------------------------------------------- */ 113 114 static __always_inline bool bochs_uses_mmio(struct bochs_device *bochs) 115 { 116 return !IS_ENABLED(CONFIG_HAS_IOPORT) || bochs->mmio; 117 } 118 119 static void bochs_vga_writeb(struct bochs_device *bochs, u16 ioport, u8 val) 120 { 121 if (WARN_ON(ioport < 0x3c0 || ioport > 0x3df)) 122 return; 123 124 if (bochs_uses_mmio(bochs)) { 125 int offset = ioport - 0x3c0 + 0x400; 126 127 writeb(val, bochs->mmio + offset); 128 } else { 129 outb(val, ioport); 130 } 131 } 132 133 static u8 bochs_vga_readb(struct bochs_device *bochs, u16 ioport) 134 { 135 if (WARN_ON(ioport < 0x3c0 || ioport > 0x3df)) 136 return 0xff; 137 138 if (bochs_uses_mmio(bochs)) { 139 int offset = ioport - 0x3c0 + 0x400; 140 141 return readb(bochs->mmio + offset); 142 } else { 143 return inb(ioport); 144 } 145 } 146 147 static u16 bochs_dispi_read(struct bochs_device *bochs, u16 reg) 148 { 149 u16 ret = 0; 150 151 if (bochs_uses_mmio(bochs)) { 152 int offset = 0x500 + (reg << 1); 153 154 ret = readw(bochs->mmio + offset); 155 } else { 156 outw(reg, VBE_DISPI_IOPORT_INDEX); 157 ret = inw(VBE_DISPI_IOPORT_DATA); 158 } 159 return ret; 160 } 161 162 static void bochs_dispi_write(struct bochs_device *bochs, u16 reg, u16 val) 163 { 164 if (bochs_uses_mmio(bochs)) { 165 int offset = 0x500 + (reg << 1); 166 167 writew(val, bochs->mmio + offset); 168 } else { 169 outw(reg, VBE_DISPI_IOPORT_INDEX); 170 outw(val, VBE_DISPI_IOPORT_DATA); 171 } 172 } 173 174 static void bochs_hw_set_big_endian(struct bochs_device *bochs) 175 { 176 if (bochs->qext_size < 8) 177 return; 178 179 writel(0xbebebebe, bochs->mmio + 0x604); 180 } 181 182 static void bochs_hw_set_little_endian(struct bochs_device *bochs) 183 { 184 if (bochs->qext_size < 8) 185 return; 186 187 writel(0x1e1e1e1e, bochs->mmio + 0x604); 188 } 189 190 #ifdef __BIG_ENDIAN 191 #define bochs_hw_set_native_endian(_b) bochs_hw_set_big_endian(_b) 192 #else 193 #define bochs_hw_set_native_endian(_b) bochs_hw_set_little_endian(_b) 194 #endif 195 196 static int bochs_get_edid_block(void *data, u8 *buf, unsigned int block, size_t len) 197 { 198 struct bochs_device *bochs = data; 199 size_t i, start = block * EDID_LENGTH; 200 201 if (!bochs->mmio) 202 return -1; 203 204 if (start + len > 0x400 /* vga register offset */) 205 return -1; 206 207 for (i = 0; i < len; i++) 208 buf[i] = readb(bochs->mmio + start + i); 209 210 return 0; 211 } 212 213 static const struct drm_edid *bochs_hw_read_edid(struct drm_connector *connector) 214 { 215 struct drm_device *dev = connector->dev; 216 struct bochs_device *bochs = to_bochs_device(dev); 217 u8 header[8]; 218 219 /* check header to detect whenever edid support is enabled in qemu */ 220 bochs_get_edid_block(bochs, header, 0, ARRAY_SIZE(header)); 221 if (drm_edid_header_is_valid(header) != 8) 222 return NULL; 223 224 drm_dbg(dev, "Found EDID data blob.\n"); 225 226 return drm_edid_read_custom(connector, bochs_get_edid_block, bochs); 227 } 228 229 static int bochs_hw_init(struct bochs_device *bochs) 230 { 231 struct drm_device *dev = &bochs->dev; 232 struct pci_dev *pdev = to_pci_dev(dev->dev); 233 unsigned long addr, size, mem, ioaddr, iosize; 234 u16 id; 235 236 if (pdev->resource[2].flags & IORESOURCE_MEM) { 237 ioaddr = pci_resource_start(pdev, 2); 238 iosize = pci_resource_len(pdev, 2); 239 /* mmio bar with vga and bochs registers present */ 240 if (!devm_request_mem_region(&pdev->dev, ioaddr, iosize, "bochs-drm")) { 241 DRM_ERROR("Cannot request mmio region\n"); 242 return -EBUSY; 243 } 244 bochs->mmio = devm_ioremap(&pdev->dev, ioaddr, iosize); 245 if (bochs->mmio == NULL) { 246 DRM_ERROR("Cannot map mmio region\n"); 247 return -ENOMEM; 248 } 249 } else if (IS_ENABLED(CONFIG_HAS_IOPORT)) { 250 ioaddr = VBE_DISPI_IOPORT_INDEX; 251 iosize = 2; 252 if (!devm_request_region(&pdev->dev, ioaddr, iosize, "bochs-drm")) { 253 DRM_ERROR("Cannot request ioports\n"); 254 return -EBUSY; 255 } 256 bochs->ioports = 1; 257 } else { 258 drm_err(dev, "I/O ports are not supported\n"); 259 return -EIO; 260 } 261 262 id = bochs_dispi_read(bochs, VBE_DISPI_INDEX_ID); 263 mem = bochs_dispi_read(bochs, VBE_DISPI_INDEX_VIDEO_MEMORY_64K) 264 * 64 * 1024; 265 if ((id & 0xfff0) != VBE_DISPI_ID0) { 266 DRM_ERROR("ID mismatch\n"); 267 return -ENODEV; 268 } 269 270 if ((pdev->resource[0].flags & IORESOURCE_MEM) == 0) 271 return -ENODEV; 272 addr = pci_resource_start(pdev, 0); 273 size = pci_resource_len(pdev, 0); 274 if (addr == 0) 275 return -ENODEV; 276 if (size != mem) { 277 DRM_ERROR("Size mismatch: pci=%ld, bochs=%ld\n", 278 size, mem); 279 size = min(size, mem); 280 } 281 282 if (!devm_request_mem_region(&pdev->dev, addr, size, "bochs-drm")) 283 DRM_WARN("Cannot request framebuffer, boot fb still active?\n"); 284 285 bochs->fb_map = devm_ioremap_wc(&pdev->dev, addr, size); 286 if (bochs->fb_map == NULL) { 287 DRM_ERROR("Cannot map framebuffer\n"); 288 return -ENOMEM; 289 } 290 bochs->fb_base = addr; 291 bochs->fb_size = size; 292 293 DRM_INFO("Found bochs VGA, ID 0x%x.\n", id); 294 DRM_INFO("Framebuffer size %ld kB @ 0x%lx, %s @ 0x%lx.\n", 295 size / 1024, addr, 296 bochs->ioports ? "ioports" : "mmio", 297 ioaddr); 298 299 if (bochs->mmio && pdev->revision >= 2) { 300 bochs->qext_size = readl(bochs->mmio + 0x600); 301 if (bochs->qext_size < 4 || bochs->qext_size > iosize) { 302 bochs->qext_size = 0; 303 goto noext; 304 } 305 DRM_DEBUG("Found qemu ext regs, size %ld\n", 306 bochs->qext_size); 307 bochs_hw_set_native_endian(bochs); 308 } 309 310 noext: 311 return 0; 312 } 313 314 static void bochs_hw_blank(struct bochs_device *bochs, bool blank) 315 { 316 DRM_DEBUG_DRIVER("hw_blank %d\n", blank); 317 /* enable color bit (so VGA_IS1_RC access works) */ 318 bochs_vga_writeb(bochs, VGA_MIS_W, VGA_MIS_COLOR); 319 /* discard ar_flip_flop */ 320 (void)bochs_vga_readb(bochs, VGA_IS1_RC); 321 /* blank or unblank; we need only update index and set 0x20 */ 322 bochs_vga_writeb(bochs, VGA_ATT_W, blank ? 0 : 0x20); 323 } 324 325 static void bochs_hw_setmode(struct bochs_device *bochs, struct drm_display_mode *mode) 326 { 327 int idx; 328 329 if (!drm_dev_enter(&bochs->dev, &idx)) 330 return; 331 332 bochs->xres = mode->hdisplay; 333 bochs->yres = mode->vdisplay; 334 bochs->bpp = 32; 335 bochs->stride = mode->hdisplay * (bochs->bpp / 8); 336 bochs->yres_virtual = bochs->fb_size / bochs->stride; 337 338 DRM_DEBUG_DRIVER("%dx%d @ %d bpp, vy %d\n", 339 bochs->xres, bochs->yres, bochs->bpp, 340 bochs->yres_virtual); 341 342 bochs_dispi_write(bochs, VBE_DISPI_INDEX_ENABLE, 0); 343 bochs_dispi_write(bochs, VBE_DISPI_INDEX_BPP, bochs->bpp); 344 bochs_dispi_write(bochs, VBE_DISPI_INDEX_XRES, bochs->xres); 345 bochs_dispi_write(bochs, VBE_DISPI_INDEX_YRES, bochs->yres); 346 bochs_dispi_write(bochs, VBE_DISPI_INDEX_BANK, 0); 347 bochs_dispi_write(bochs, VBE_DISPI_INDEX_VIRT_WIDTH, bochs->xres); 348 bochs_dispi_write(bochs, VBE_DISPI_INDEX_VIRT_HEIGHT, 349 bochs->yres_virtual); 350 bochs_dispi_write(bochs, VBE_DISPI_INDEX_X_OFFSET, 0); 351 bochs_dispi_write(bochs, VBE_DISPI_INDEX_Y_OFFSET, 0); 352 353 bochs_dispi_write(bochs, VBE_DISPI_INDEX_ENABLE, 354 VBE_DISPI_ENABLED | VBE_DISPI_LFB_ENABLED); 355 356 drm_dev_exit(idx); 357 } 358 359 static void bochs_hw_setformat(struct bochs_device *bochs, const struct drm_format_info *format) 360 { 361 int idx; 362 363 if (!drm_dev_enter(&bochs->dev, &idx)) 364 return; 365 366 DRM_DEBUG_DRIVER("format %c%c%c%c\n", 367 (format->format >> 0) & 0xff, 368 (format->format >> 8) & 0xff, 369 (format->format >> 16) & 0xff, 370 (format->format >> 24) & 0xff); 371 372 switch (format->format) { 373 case DRM_FORMAT_XRGB8888: 374 bochs_hw_set_little_endian(bochs); 375 break; 376 case DRM_FORMAT_BGRX8888: 377 bochs_hw_set_big_endian(bochs); 378 break; 379 default: 380 /* should not happen */ 381 DRM_ERROR("%s: Huh? Got framebuffer format 0x%x", 382 __func__, format->format); 383 break; 384 } 385 386 drm_dev_exit(idx); 387 } 388 389 static void bochs_hw_setbase(struct bochs_device *bochs, int x, int y, int stride, u64 addr) 390 { 391 unsigned long offset; 392 unsigned int vx, vy, vwidth, idx; 393 394 if (!drm_dev_enter(&bochs->dev, &idx)) 395 return; 396 397 bochs->stride = stride; 398 offset = (unsigned long)addr + 399 y * bochs->stride + 400 x * (bochs->bpp / 8); 401 vy = offset / bochs->stride; 402 vx = (offset % bochs->stride) * 8 / bochs->bpp; 403 vwidth = stride * 8 / bochs->bpp; 404 405 DRM_DEBUG_DRIVER("x %d, y %d, addr %llx -> offset %lx, vx %d, vy %d\n", 406 x, y, addr, offset, vx, vy); 407 bochs_dispi_write(bochs, VBE_DISPI_INDEX_VIRT_WIDTH, vwidth); 408 bochs_dispi_write(bochs, VBE_DISPI_INDEX_X_OFFSET, vx); 409 bochs_dispi_write(bochs, VBE_DISPI_INDEX_Y_OFFSET, vy); 410 411 drm_dev_exit(idx); 412 } 413 414 /* ---------------------------------------------------------------------- */ 415 416 static const uint32_t bochs_primary_plane_formats[] = { 417 DRM_FORMAT_XRGB8888, 418 DRM_FORMAT_BGRX8888, 419 }; 420 421 static int bochs_primary_plane_helper_atomic_check(struct drm_plane *plane, 422 struct drm_atomic_state *state) 423 { 424 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); 425 struct drm_crtc *new_crtc = new_plane_state->crtc; 426 struct drm_crtc_state *new_crtc_state = NULL; 427 int ret; 428 429 if (new_crtc) 430 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc); 431 432 ret = drm_atomic_helper_check_plane_state(new_plane_state, new_crtc_state, 433 DRM_PLANE_NO_SCALING, 434 DRM_PLANE_NO_SCALING, 435 false, false); 436 if (ret) 437 return ret; 438 else if (!new_plane_state->visible) 439 return 0; 440 441 return 0; 442 } 443 444 static void bochs_primary_plane_helper_atomic_update(struct drm_plane *plane, 445 struct drm_atomic_state *state) 446 { 447 struct drm_device *dev = plane->dev; 448 struct bochs_device *bochs = to_bochs_device(dev); 449 struct drm_plane_state *plane_state = plane->state; 450 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane); 451 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state); 452 struct drm_framebuffer *fb = plane_state->fb; 453 struct drm_atomic_helper_damage_iter iter; 454 struct drm_rect damage; 455 456 if (!fb || !bochs->stride) 457 return; 458 459 drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state); 460 drm_atomic_for_each_plane_damage(&iter, &damage) { 461 struct iosys_map dst = IOSYS_MAP_INIT_VADDR_IOMEM(bochs->fb_map); 462 463 iosys_map_incr(&dst, drm_fb_clip_offset(fb->pitches[0], fb->format, &damage)); 464 drm_fb_memcpy(&dst, fb->pitches, shadow_plane_state->data, fb, &damage); 465 } 466 467 /* Always scanout image at VRAM offset 0 */ 468 bochs_hw_setbase(bochs, 469 plane_state->crtc_x, 470 plane_state->crtc_y, 471 fb->pitches[0], 472 0); 473 bochs_hw_setformat(bochs, fb->format); 474 } 475 476 static int bochs_primary_plane_helper_get_scanout_buffer(struct drm_plane *plane, 477 struct drm_scanout_buffer *sb) 478 { 479 struct bochs_device *bochs = to_bochs_device(plane->dev); 480 struct iosys_map map = IOSYS_MAP_INIT_VADDR_IOMEM(bochs->fb_map); 481 482 if (plane->state && plane->state->fb) { 483 sb->format = plane->state->fb->format; 484 sb->width = plane->state->fb->width; 485 sb->height = plane->state->fb->height; 486 sb->pitch[0] = plane->state->fb->pitches[0]; 487 sb->map[0] = map; 488 return 0; 489 } 490 return -ENODEV; 491 } 492 493 static const struct drm_plane_helper_funcs bochs_primary_plane_helper_funcs = { 494 DRM_GEM_SHADOW_PLANE_HELPER_FUNCS, 495 .atomic_check = bochs_primary_plane_helper_atomic_check, 496 .atomic_update = bochs_primary_plane_helper_atomic_update, 497 .get_scanout_buffer = bochs_primary_plane_helper_get_scanout_buffer, 498 }; 499 500 static const struct drm_plane_funcs bochs_primary_plane_funcs = { 501 .update_plane = drm_atomic_helper_update_plane, 502 .disable_plane = drm_atomic_helper_disable_plane, 503 .destroy = drm_plane_cleanup, 504 DRM_GEM_SHADOW_PLANE_FUNCS 505 }; 506 507 static void bochs_crtc_helper_mode_set_nofb(struct drm_crtc *crtc) 508 { 509 struct bochs_device *bochs = to_bochs_device(crtc->dev); 510 struct drm_crtc_state *crtc_state = crtc->state; 511 512 bochs_hw_setmode(bochs, &crtc_state->mode); 513 } 514 515 static int bochs_crtc_helper_atomic_check(struct drm_crtc *crtc, 516 struct drm_atomic_state *state) 517 { 518 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 519 520 if (!crtc_state->enable) 521 return 0; 522 523 return drm_atomic_helper_check_crtc_primary_plane(crtc_state); 524 } 525 526 static void bochs_crtc_helper_atomic_enable(struct drm_crtc *crtc, 527 struct drm_atomic_state *state) 528 { 529 struct bochs_device *bochs = to_bochs_device(crtc->dev); 530 531 bochs_hw_blank(bochs, false); 532 drm_crtc_vblank_on(crtc); 533 } 534 535 static void bochs_crtc_helper_atomic_disable(struct drm_crtc *crtc, 536 struct drm_atomic_state *crtc_state) 537 { 538 struct bochs_device *bochs = to_bochs_device(crtc->dev); 539 540 drm_crtc_vblank_off(crtc); 541 bochs_hw_blank(bochs, true); 542 } 543 544 static const struct drm_crtc_helper_funcs bochs_crtc_helper_funcs = { 545 .mode_set_nofb = bochs_crtc_helper_mode_set_nofb, 546 .atomic_check = bochs_crtc_helper_atomic_check, 547 .atomic_flush = drm_crtc_vblank_atomic_flush, 548 .atomic_enable = bochs_crtc_helper_atomic_enable, 549 .atomic_disable = bochs_crtc_helper_atomic_disable, 550 }; 551 552 static const struct drm_crtc_funcs bochs_crtc_funcs = { 553 .reset = drm_atomic_helper_crtc_reset, 554 .destroy = drm_crtc_cleanup, 555 .set_config = drm_atomic_helper_set_config, 556 .page_flip = drm_atomic_helper_page_flip, 557 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 558 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 559 DRM_CRTC_VBLANK_TIMER_FUNCS, 560 }; 561 562 static const struct drm_encoder_funcs bochs_encoder_funcs = { 563 .destroy = drm_encoder_cleanup, 564 }; 565 566 static int bochs_connector_helper_get_modes(struct drm_connector *connector) 567 { 568 const struct drm_edid *edid; 569 int count; 570 571 edid = bochs_hw_read_edid(connector); 572 573 if (edid) { 574 drm_edid_connector_update(connector, edid); 575 count = drm_edid_connector_add_modes(connector); 576 drm_edid_free(edid); 577 } else { 578 drm_edid_connector_update(connector, NULL); 579 count = drm_add_modes_noedid(connector, 8192, 8192); 580 drm_set_preferred_mode(connector, defx, defy); 581 } 582 583 return count; 584 } 585 586 static const struct drm_connector_helper_funcs bochs_connector_helper_funcs = { 587 .get_modes = bochs_connector_helper_get_modes, 588 }; 589 590 static const struct drm_connector_funcs bochs_connector_funcs = { 591 .fill_modes = drm_helper_probe_single_connector_modes, 592 .destroy = drm_connector_cleanup, 593 .reset = drm_atomic_helper_connector_reset, 594 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 595 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 596 }; 597 598 static enum drm_mode_status bochs_mode_config_mode_valid(struct drm_device *dev, 599 const struct drm_display_mode *mode) 600 { 601 struct bochs_device *bochs = to_bochs_device(dev); 602 const struct drm_format_info *format = drm_format_info(DRM_FORMAT_XRGB8888); 603 u64 pitch; 604 605 if (drm_WARN_ON(dev, !format)) 606 return MODE_ERROR; 607 608 pitch = drm_format_info_min_pitch(format, 0, mode->hdisplay); 609 if (!pitch) 610 return MODE_BAD_WIDTH; 611 if (mode->vdisplay > DIV_ROUND_DOWN_ULL(bochs->fb_size, pitch)) 612 return MODE_MEM; 613 614 return MODE_OK; 615 } 616 617 static const struct drm_mode_config_funcs bochs_mode_config_funcs = { 618 .fb_create = drm_gem_fb_create_with_dirty, 619 .mode_valid = bochs_mode_config_mode_valid, 620 .atomic_check = drm_atomic_helper_check, 621 .atomic_commit = drm_atomic_helper_commit, 622 }; 623 624 static int bochs_kms_init(struct bochs_device *bochs) 625 { 626 struct drm_device *dev = &bochs->dev; 627 struct drm_plane *primary_plane; 628 struct drm_crtc *crtc; 629 struct drm_connector *connector; 630 struct drm_encoder *encoder; 631 int ret; 632 633 ret = drmm_mode_config_init(dev); 634 if (ret) 635 return ret; 636 637 dev->mode_config.max_width = 8192; 638 dev->mode_config.max_height = 8192; 639 640 dev->mode_config.preferred_depth = 24; 641 dev->mode_config.quirk_addfb_prefer_host_byte_order = true; 642 643 dev->mode_config.funcs = &bochs_mode_config_funcs; 644 645 primary_plane = &bochs->primary_plane; 646 ret = drm_universal_plane_init(dev, primary_plane, 0, 647 &bochs_primary_plane_funcs, 648 bochs_primary_plane_formats, 649 ARRAY_SIZE(bochs_primary_plane_formats), 650 NULL, 651 DRM_PLANE_TYPE_PRIMARY, NULL); 652 if (ret) 653 return ret; 654 drm_plane_helper_add(primary_plane, &bochs_primary_plane_helper_funcs); 655 drm_plane_enable_fb_damage_clips(primary_plane); 656 657 crtc = &bochs->crtc; 658 ret = drm_crtc_init_with_planes(dev, crtc, primary_plane, NULL, 659 &bochs_crtc_funcs, NULL); 660 if (ret) 661 return ret; 662 drm_crtc_helper_add(crtc, &bochs_crtc_helper_funcs); 663 664 encoder = &bochs->encoder; 665 ret = drm_encoder_init(dev, encoder, &bochs_encoder_funcs, 666 DRM_MODE_ENCODER_VIRTUAL, NULL); 667 if (ret) 668 return ret; 669 encoder->possible_crtcs = drm_crtc_mask(crtc); 670 671 connector = &bochs->connector; 672 ret = drm_connector_init(dev, connector, &bochs_connector_funcs, 673 DRM_MODE_CONNECTOR_VIRTUAL); 674 if (ret) 675 return ret; 676 drm_connector_helper_add(connector, &bochs_connector_helper_funcs); 677 drm_connector_attach_edid_property(connector); 678 drm_connector_attach_encoder(connector, encoder); 679 680 ret = drm_vblank_init(dev, 1); 681 if (ret) 682 return ret; 683 684 drm_mode_config_reset(dev); 685 686 return 0; 687 } 688 689 /* ---------------------------------------------------------------------- */ 690 /* drm interface */ 691 692 static int bochs_load(struct bochs_device *bochs) 693 { 694 int ret; 695 696 ret = bochs_hw_init(bochs); 697 if (ret) 698 return ret; 699 700 ret = bochs_kms_init(bochs); 701 if (ret) 702 return ret; 703 704 return 0; 705 } 706 707 DEFINE_DRM_GEM_FOPS(bochs_fops); 708 709 static const struct drm_driver bochs_driver = { 710 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC, 711 .fops = &bochs_fops, 712 .name = "bochs-drm", 713 .desc = "bochs dispi vga interface (qemu stdvga)", 714 .major = 1, 715 .minor = 0, 716 DRM_GEM_SHMEM_DRIVER_OPS, 717 DRM_FBDEV_SHMEM_DRIVER_OPS, 718 }; 719 720 /* ---------------------------------------------------------------------- */ 721 /* pm interface */ 722 723 #ifdef CONFIG_PM_SLEEP 724 static int bochs_pm_suspend(struct device *dev) 725 { 726 struct drm_device *drm_dev = dev_get_drvdata(dev); 727 728 return drm_mode_config_helper_suspend(drm_dev); 729 } 730 731 static int bochs_pm_resume(struct device *dev) 732 { 733 struct drm_device *drm_dev = dev_get_drvdata(dev); 734 735 return drm_mode_config_helper_resume(drm_dev); 736 } 737 #endif 738 739 static const struct dev_pm_ops bochs_pm_ops = { 740 SET_SYSTEM_SLEEP_PM_OPS(bochs_pm_suspend, 741 bochs_pm_resume) 742 }; 743 744 /* ---------------------------------------------------------------------- */ 745 /* pci interface */ 746 747 static int bochs_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 748 { 749 struct bochs_device *bochs; 750 struct drm_device *dev; 751 int ret; 752 753 ret = aperture_remove_conflicting_pci_devices(pdev, bochs_driver.name); 754 if (ret) 755 return ret; 756 757 bochs = devm_drm_dev_alloc(&pdev->dev, &bochs_driver, struct bochs_device, dev); 758 if (IS_ERR(bochs)) 759 return PTR_ERR(bochs); 760 dev = &bochs->dev; 761 762 ret = pcim_enable_device(pdev); 763 if (ret) 764 goto err_free_dev; 765 766 pci_set_drvdata(pdev, dev); 767 768 ret = bochs_load(bochs); 769 if (ret) 770 goto err_free_dev; 771 772 ret = drm_dev_register(dev, 0); 773 if (ret) 774 goto err_free_dev; 775 776 drm_client_setup(dev, NULL); 777 778 return ret; 779 780 err_free_dev: 781 drm_dev_put(dev); 782 return ret; 783 } 784 785 static void bochs_pci_remove(struct pci_dev *pdev) 786 { 787 struct drm_device *dev = pci_get_drvdata(pdev); 788 789 drm_dev_unplug(dev); 790 drm_atomic_helper_shutdown(dev); 791 } 792 793 static void bochs_pci_shutdown(struct pci_dev *pdev) 794 { 795 drm_atomic_helper_shutdown(pci_get_drvdata(pdev)); 796 } 797 798 static const struct pci_device_id bochs_pci_tbl[] = { 799 { 800 .vendor = 0x1234, 801 .device = 0x1111, 802 .subvendor = PCI_SUBVENDOR_ID_REDHAT_QUMRANET, 803 .subdevice = PCI_SUBDEVICE_ID_QEMU, 804 .driver_data = BOCHS_QEMU_STDVGA, 805 }, 806 { 807 .vendor = 0x1234, 808 .device = 0x1111, 809 .subvendor = PCI_ANY_ID, 810 .subdevice = PCI_ANY_ID, 811 .driver_data = BOCHS_UNKNOWN, 812 }, 813 { 814 .vendor = 0x4321, 815 .device = 0x1111, 816 .subvendor = PCI_ANY_ID, 817 .subdevice = PCI_ANY_ID, 818 .driver_data = BOCHS_SIMICS, 819 }, 820 { /* end of list */ } 821 }; 822 823 static struct pci_driver bochs_pci_driver = { 824 .name = "bochs-drm", 825 .id_table = bochs_pci_tbl, 826 .probe = bochs_pci_probe, 827 .remove = bochs_pci_remove, 828 .shutdown = bochs_pci_shutdown, 829 .driver.pm = &bochs_pm_ops, 830 }; 831 832 /* ---------------------------------------------------------------------- */ 833 /* module init/exit */ 834 835 drm_module_pci_driver_if_modeset(bochs_pci_driver, bochs_modeset); 836 837 MODULE_DEVICE_TABLE(pci, bochs_pci_tbl); 838 MODULE_AUTHOR("Gerd Hoffmann <kraxel@redhat.com>"); 839 MODULE_DESCRIPTION("DRM Support for bochs dispi vga interface (qemu stdvga)"); 840 MODULE_LICENSE("GPL"); 841