1 // SPDX-License-Identifier: GPL-2.0-or-later 2 3 #include <linux/aperture.h> 4 #include <linux/module.h> 5 #include <linux/pci.h> 6 7 #include <drm/drm_atomic.h> 8 #include <drm/drm_atomic_helper.h> 9 #include <drm/drm_client_setup.h> 10 #include <drm/drm_damage_helper.h> 11 #include <drm/drm_drv.h> 12 #include <drm/drm_edid.h> 13 #include <drm/drm_fbdev_shmem.h> 14 #include <drm/drm_fourcc.h> 15 #include <drm/drm_framebuffer.h> 16 #include <drm/drm_gem_atomic_helper.h> 17 #include <drm/drm_gem_framebuffer_helper.h> 18 #include <drm/drm_gem_shmem_helper.h> 19 #include <drm/drm_managed.h> 20 #include <drm/drm_module.h> 21 #include <drm/drm_plane_helper.h> 22 #include <drm/drm_probe_helper.h> 23 24 #include <video/vga.h> 25 26 /* ---------------------------------------------------------------------- */ 27 28 #define VBE_DISPI_IOPORT_INDEX 0x01CE 29 #define VBE_DISPI_IOPORT_DATA 0x01CF 30 31 #define VBE_DISPI_INDEX_ID 0x0 32 #define VBE_DISPI_INDEX_XRES 0x1 33 #define VBE_DISPI_INDEX_YRES 0x2 34 #define VBE_DISPI_INDEX_BPP 0x3 35 #define VBE_DISPI_INDEX_ENABLE 0x4 36 #define VBE_DISPI_INDEX_BANK 0x5 37 #define VBE_DISPI_INDEX_VIRT_WIDTH 0x6 38 #define VBE_DISPI_INDEX_VIRT_HEIGHT 0x7 39 #define VBE_DISPI_INDEX_X_OFFSET 0x8 40 #define VBE_DISPI_INDEX_Y_OFFSET 0x9 41 #define VBE_DISPI_INDEX_VIDEO_MEMORY_64K 0xa 42 43 #define VBE_DISPI_ID0 0xB0C0 44 #define VBE_DISPI_ID1 0xB0C1 45 #define VBE_DISPI_ID2 0xB0C2 46 #define VBE_DISPI_ID3 0xB0C3 47 #define VBE_DISPI_ID4 0xB0C4 48 #define VBE_DISPI_ID5 0xB0C5 49 50 #define VBE_DISPI_DISABLED 0x00 51 #define VBE_DISPI_ENABLED 0x01 52 #define VBE_DISPI_GETCAPS 0x02 53 #define VBE_DISPI_8BIT_DAC 0x20 54 #define VBE_DISPI_LFB_ENABLED 0x40 55 #define VBE_DISPI_NOCLEARMEM 0x80 56 57 static int bochs_modeset = -1; 58 static int defx = 1024; 59 static int defy = 768; 60 61 module_param_named(modeset, bochs_modeset, int, 0444); 62 MODULE_PARM_DESC(modeset, "enable/disable kernel modesetting"); 63 64 module_param(defx, int, 0444); 65 module_param(defy, int, 0444); 66 MODULE_PARM_DESC(defx, "default x resolution"); 67 MODULE_PARM_DESC(defy, "default y resolution"); 68 69 /* ---------------------------------------------------------------------- */ 70 71 enum bochs_types { 72 BOCHS_QEMU_STDVGA, 73 BOCHS_SIMICS, 74 BOCHS_UNKNOWN, 75 }; 76 77 struct bochs_device { 78 struct drm_device dev; 79 80 /* hw */ 81 void __iomem *mmio; 82 int ioports; 83 void __iomem *fb_map; 84 unsigned long fb_base; 85 unsigned long fb_size; 86 unsigned long qext_size; 87 88 /* mode */ 89 u16 xres; 90 u16 yres; 91 u16 yres_virtual; 92 u32 stride; 93 u32 bpp; 94 95 /* drm */ 96 struct drm_plane primary_plane; 97 struct drm_crtc crtc; 98 struct drm_encoder encoder; 99 struct drm_connector connector; 100 }; 101 102 static struct bochs_device *to_bochs_device(const struct drm_device *dev) 103 { 104 return container_of(dev, struct bochs_device, dev); 105 } 106 107 /* ---------------------------------------------------------------------- */ 108 109 static void bochs_vga_writeb(struct bochs_device *bochs, u16 ioport, u8 val) 110 { 111 if (WARN_ON(ioport < 0x3c0 || ioport > 0x3df)) 112 return; 113 114 if (bochs->mmio) { 115 int offset = ioport - 0x3c0 + 0x400; 116 117 writeb(val, bochs->mmio + offset); 118 } else { 119 outb(val, ioport); 120 } 121 } 122 123 static u8 bochs_vga_readb(struct bochs_device *bochs, u16 ioport) 124 { 125 if (WARN_ON(ioport < 0x3c0 || ioport > 0x3df)) 126 return 0xff; 127 128 if (bochs->mmio) { 129 int offset = ioport - 0x3c0 + 0x400; 130 131 return readb(bochs->mmio + offset); 132 } else { 133 return inb(ioport); 134 } 135 } 136 137 static u16 bochs_dispi_read(struct bochs_device *bochs, u16 reg) 138 { 139 u16 ret = 0; 140 141 if (bochs->mmio) { 142 int offset = 0x500 + (reg << 1); 143 144 ret = readw(bochs->mmio + offset); 145 } else { 146 outw(reg, VBE_DISPI_IOPORT_INDEX); 147 ret = inw(VBE_DISPI_IOPORT_DATA); 148 } 149 return ret; 150 } 151 152 static void bochs_dispi_write(struct bochs_device *bochs, u16 reg, u16 val) 153 { 154 if (bochs->mmio) { 155 int offset = 0x500 + (reg << 1); 156 157 writew(val, bochs->mmio + offset); 158 } else { 159 outw(reg, VBE_DISPI_IOPORT_INDEX); 160 outw(val, VBE_DISPI_IOPORT_DATA); 161 } 162 } 163 164 static void bochs_hw_set_big_endian(struct bochs_device *bochs) 165 { 166 if (bochs->qext_size < 8) 167 return; 168 169 writel(0xbebebebe, bochs->mmio + 0x604); 170 } 171 172 static void bochs_hw_set_little_endian(struct bochs_device *bochs) 173 { 174 if (bochs->qext_size < 8) 175 return; 176 177 writel(0x1e1e1e1e, bochs->mmio + 0x604); 178 } 179 180 #ifdef __BIG_ENDIAN 181 #define bochs_hw_set_native_endian(_b) bochs_hw_set_big_endian(_b) 182 #else 183 #define bochs_hw_set_native_endian(_b) bochs_hw_set_little_endian(_b) 184 #endif 185 186 static int bochs_get_edid_block(void *data, u8 *buf, unsigned int block, size_t len) 187 { 188 struct bochs_device *bochs = data; 189 size_t i, start = block * EDID_LENGTH; 190 191 if (!bochs->mmio) 192 return -1; 193 194 if (start + len > 0x400 /* vga register offset */) 195 return -1; 196 197 for (i = 0; i < len; i++) 198 buf[i] = readb(bochs->mmio + start + i); 199 200 return 0; 201 } 202 203 static const struct drm_edid *bochs_hw_read_edid(struct drm_connector *connector) 204 { 205 struct drm_device *dev = connector->dev; 206 struct bochs_device *bochs = to_bochs_device(dev); 207 u8 header[8]; 208 209 /* check header to detect whenever edid support is enabled in qemu */ 210 bochs_get_edid_block(bochs, header, 0, ARRAY_SIZE(header)); 211 if (drm_edid_header_is_valid(header) != 8) 212 return NULL; 213 214 drm_dbg(dev, "Found EDID data blob.\n"); 215 216 return drm_edid_read_custom(connector, bochs_get_edid_block, bochs); 217 } 218 219 static int bochs_hw_init(struct bochs_device *bochs) 220 { 221 struct drm_device *dev = &bochs->dev; 222 struct pci_dev *pdev = to_pci_dev(dev->dev); 223 unsigned long addr, size, mem, ioaddr, iosize; 224 u16 id; 225 226 if (pdev->resource[2].flags & IORESOURCE_MEM) { 227 ioaddr = pci_resource_start(pdev, 2); 228 iosize = pci_resource_len(pdev, 2); 229 /* mmio bar with vga and bochs registers present */ 230 if (!devm_request_mem_region(&pdev->dev, ioaddr, iosize, "bochs-drm")) { 231 DRM_ERROR("Cannot request mmio region\n"); 232 return -EBUSY; 233 } 234 bochs->mmio = devm_ioremap(&pdev->dev, ioaddr, iosize); 235 if (bochs->mmio == NULL) { 236 DRM_ERROR("Cannot map mmio region\n"); 237 return -ENOMEM; 238 } 239 } else { 240 ioaddr = VBE_DISPI_IOPORT_INDEX; 241 iosize = 2; 242 if (!devm_request_region(&pdev->dev, ioaddr, iosize, "bochs-drm")) { 243 DRM_ERROR("Cannot request ioports\n"); 244 return -EBUSY; 245 } 246 bochs->ioports = 1; 247 } 248 249 id = bochs_dispi_read(bochs, VBE_DISPI_INDEX_ID); 250 mem = bochs_dispi_read(bochs, VBE_DISPI_INDEX_VIDEO_MEMORY_64K) 251 * 64 * 1024; 252 if ((id & 0xfff0) != VBE_DISPI_ID0) { 253 DRM_ERROR("ID mismatch\n"); 254 return -ENODEV; 255 } 256 257 if ((pdev->resource[0].flags & IORESOURCE_MEM) == 0) 258 return -ENODEV; 259 addr = pci_resource_start(pdev, 0); 260 size = pci_resource_len(pdev, 0); 261 if (addr == 0) 262 return -ENODEV; 263 if (size != mem) { 264 DRM_ERROR("Size mismatch: pci=%ld, bochs=%ld\n", 265 size, mem); 266 size = min(size, mem); 267 } 268 269 if (!devm_request_mem_region(&pdev->dev, addr, size, "bochs-drm")) 270 DRM_WARN("Cannot request framebuffer, boot fb still active?\n"); 271 272 bochs->fb_map = devm_ioremap_wc(&pdev->dev, addr, size); 273 if (bochs->fb_map == NULL) { 274 DRM_ERROR("Cannot map framebuffer\n"); 275 return -ENOMEM; 276 } 277 bochs->fb_base = addr; 278 bochs->fb_size = size; 279 280 DRM_INFO("Found bochs VGA, ID 0x%x.\n", id); 281 DRM_INFO("Framebuffer size %ld kB @ 0x%lx, %s @ 0x%lx.\n", 282 size / 1024, addr, 283 bochs->ioports ? "ioports" : "mmio", 284 ioaddr); 285 286 if (bochs->mmio && pdev->revision >= 2) { 287 bochs->qext_size = readl(bochs->mmio + 0x600); 288 if (bochs->qext_size < 4 || bochs->qext_size > iosize) { 289 bochs->qext_size = 0; 290 goto noext; 291 } 292 DRM_DEBUG("Found qemu ext regs, size %ld\n", 293 bochs->qext_size); 294 bochs_hw_set_native_endian(bochs); 295 } 296 297 noext: 298 return 0; 299 } 300 301 static void bochs_hw_blank(struct bochs_device *bochs, bool blank) 302 { 303 DRM_DEBUG_DRIVER("hw_blank %d\n", blank); 304 /* enable color bit (so VGA_IS1_RC access works) */ 305 bochs_vga_writeb(bochs, VGA_MIS_W, VGA_MIS_COLOR); 306 /* discard ar_flip_flop */ 307 (void)bochs_vga_readb(bochs, VGA_IS1_RC); 308 /* blank or unblank; we need only update index and set 0x20 */ 309 bochs_vga_writeb(bochs, VGA_ATT_W, blank ? 0 : 0x20); 310 } 311 312 static void bochs_hw_setmode(struct bochs_device *bochs, struct drm_display_mode *mode) 313 { 314 int idx; 315 316 if (!drm_dev_enter(&bochs->dev, &idx)) 317 return; 318 319 bochs->xres = mode->hdisplay; 320 bochs->yres = mode->vdisplay; 321 bochs->bpp = 32; 322 bochs->stride = mode->hdisplay * (bochs->bpp / 8); 323 bochs->yres_virtual = bochs->fb_size / bochs->stride; 324 325 DRM_DEBUG_DRIVER("%dx%d @ %d bpp, vy %d\n", 326 bochs->xres, bochs->yres, bochs->bpp, 327 bochs->yres_virtual); 328 329 bochs_hw_blank(bochs, false); 330 331 bochs_dispi_write(bochs, VBE_DISPI_INDEX_ENABLE, 0); 332 bochs_dispi_write(bochs, VBE_DISPI_INDEX_BPP, bochs->bpp); 333 bochs_dispi_write(bochs, VBE_DISPI_INDEX_XRES, bochs->xres); 334 bochs_dispi_write(bochs, VBE_DISPI_INDEX_YRES, bochs->yres); 335 bochs_dispi_write(bochs, VBE_DISPI_INDEX_BANK, 0); 336 bochs_dispi_write(bochs, VBE_DISPI_INDEX_VIRT_WIDTH, bochs->xres); 337 bochs_dispi_write(bochs, VBE_DISPI_INDEX_VIRT_HEIGHT, 338 bochs->yres_virtual); 339 bochs_dispi_write(bochs, VBE_DISPI_INDEX_X_OFFSET, 0); 340 bochs_dispi_write(bochs, VBE_DISPI_INDEX_Y_OFFSET, 0); 341 342 bochs_dispi_write(bochs, VBE_DISPI_INDEX_ENABLE, 343 VBE_DISPI_ENABLED | VBE_DISPI_LFB_ENABLED); 344 345 drm_dev_exit(idx); 346 } 347 348 static void bochs_hw_setformat(struct bochs_device *bochs, const struct drm_format_info *format) 349 { 350 int idx; 351 352 if (!drm_dev_enter(&bochs->dev, &idx)) 353 return; 354 355 DRM_DEBUG_DRIVER("format %c%c%c%c\n", 356 (format->format >> 0) & 0xff, 357 (format->format >> 8) & 0xff, 358 (format->format >> 16) & 0xff, 359 (format->format >> 24) & 0xff); 360 361 switch (format->format) { 362 case DRM_FORMAT_XRGB8888: 363 bochs_hw_set_little_endian(bochs); 364 break; 365 case DRM_FORMAT_BGRX8888: 366 bochs_hw_set_big_endian(bochs); 367 break; 368 default: 369 /* should not happen */ 370 DRM_ERROR("%s: Huh? Got framebuffer format 0x%x", 371 __func__, format->format); 372 break; 373 } 374 375 drm_dev_exit(idx); 376 } 377 378 static void bochs_hw_setbase(struct bochs_device *bochs, int x, int y, int stride, u64 addr) 379 { 380 unsigned long offset; 381 unsigned int vx, vy, vwidth, idx; 382 383 if (!drm_dev_enter(&bochs->dev, &idx)) 384 return; 385 386 bochs->stride = stride; 387 offset = (unsigned long)addr + 388 y * bochs->stride + 389 x * (bochs->bpp / 8); 390 vy = offset / bochs->stride; 391 vx = (offset % bochs->stride) * 8 / bochs->bpp; 392 vwidth = stride * 8 / bochs->bpp; 393 394 DRM_DEBUG_DRIVER("x %d, y %d, addr %llx -> offset %lx, vx %d, vy %d\n", 395 x, y, addr, offset, vx, vy); 396 bochs_dispi_write(bochs, VBE_DISPI_INDEX_VIRT_WIDTH, vwidth); 397 bochs_dispi_write(bochs, VBE_DISPI_INDEX_X_OFFSET, vx); 398 bochs_dispi_write(bochs, VBE_DISPI_INDEX_Y_OFFSET, vy); 399 400 drm_dev_exit(idx); 401 } 402 403 /* ---------------------------------------------------------------------- */ 404 405 static const uint32_t bochs_primary_plane_formats[] = { 406 DRM_FORMAT_XRGB8888, 407 DRM_FORMAT_BGRX8888, 408 }; 409 410 static int bochs_primary_plane_helper_atomic_check(struct drm_plane *plane, 411 struct drm_atomic_state *state) 412 { 413 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); 414 struct drm_crtc *new_crtc = new_plane_state->crtc; 415 struct drm_crtc_state *new_crtc_state = NULL; 416 int ret; 417 418 if (new_crtc) 419 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc); 420 421 ret = drm_atomic_helper_check_plane_state(new_plane_state, new_crtc_state, 422 DRM_PLANE_NO_SCALING, 423 DRM_PLANE_NO_SCALING, 424 false, false); 425 if (ret) 426 return ret; 427 else if (!new_plane_state->visible) 428 return 0; 429 430 return 0; 431 } 432 433 static void bochs_primary_plane_helper_atomic_update(struct drm_plane *plane, 434 struct drm_atomic_state *state) 435 { 436 struct drm_device *dev = plane->dev; 437 struct bochs_device *bochs = to_bochs_device(dev); 438 struct drm_plane_state *plane_state = plane->state; 439 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane); 440 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state); 441 struct drm_framebuffer *fb = plane_state->fb; 442 struct drm_atomic_helper_damage_iter iter; 443 struct drm_rect damage; 444 445 if (!fb || !bochs->stride) 446 return; 447 448 drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state); 449 drm_atomic_for_each_plane_damage(&iter, &damage) { 450 struct iosys_map dst = IOSYS_MAP_INIT_VADDR_IOMEM(bochs->fb_map); 451 452 iosys_map_incr(&dst, drm_fb_clip_offset(fb->pitches[0], fb->format, &damage)); 453 drm_fb_memcpy(&dst, fb->pitches, shadow_plane_state->data, fb, &damage); 454 } 455 456 /* Always scanout image at VRAM offset 0 */ 457 bochs_hw_setbase(bochs, 458 plane_state->crtc_x, 459 plane_state->crtc_y, 460 fb->pitches[0], 461 0); 462 bochs_hw_setformat(bochs, fb->format); 463 } 464 465 static const struct drm_plane_helper_funcs bochs_primary_plane_helper_funcs = { 466 DRM_GEM_SHADOW_PLANE_HELPER_FUNCS, 467 .atomic_check = bochs_primary_plane_helper_atomic_check, 468 .atomic_update = bochs_primary_plane_helper_atomic_update, 469 }; 470 471 static const struct drm_plane_funcs bochs_primary_plane_funcs = { 472 .update_plane = drm_atomic_helper_update_plane, 473 .disable_plane = drm_atomic_helper_disable_plane, 474 .destroy = drm_plane_cleanup, 475 DRM_GEM_SHADOW_PLANE_FUNCS 476 }; 477 478 static void bochs_crtc_helper_mode_set_nofb(struct drm_crtc *crtc) 479 { 480 struct bochs_device *bochs = to_bochs_device(crtc->dev); 481 struct drm_crtc_state *crtc_state = crtc->state; 482 483 bochs_hw_setmode(bochs, &crtc_state->mode); 484 } 485 486 static int bochs_crtc_helper_atomic_check(struct drm_crtc *crtc, 487 struct drm_atomic_state *state) 488 { 489 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 490 491 if (!crtc_state->enable) 492 return 0; 493 494 return drm_atomic_helper_check_crtc_primary_plane(crtc_state); 495 } 496 497 static void bochs_crtc_helper_atomic_enable(struct drm_crtc *crtc, 498 struct drm_atomic_state *state) 499 { 500 } 501 502 static void bochs_crtc_helper_atomic_disable(struct drm_crtc *crtc, 503 struct drm_atomic_state *crtc_state) 504 { 505 struct bochs_device *bochs = to_bochs_device(crtc->dev); 506 507 bochs_hw_blank(bochs, true); 508 } 509 510 static const struct drm_crtc_helper_funcs bochs_crtc_helper_funcs = { 511 .mode_set_nofb = bochs_crtc_helper_mode_set_nofb, 512 .atomic_check = bochs_crtc_helper_atomic_check, 513 .atomic_enable = bochs_crtc_helper_atomic_enable, 514 .atomic_disable = bochs_crtc_helper_atomic_disable, 515 }; 516 517 static const struct drm_crtc_funcs bochs_crtc_funcs = { 518 .reset = drm_atomic_helper_crtc_reset, 519 .destroy = drm_crtc_cleanup, 520 .set_config = drm_atomic_helper_set_config, 521 .page_flip = drm_atomic_helper_page_flip, 522 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 523 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 524 }; 525 526 static const struct drm_encoder_funcs bochs_encoder_funcs = { 527 .destroy = drm_encoder_cleanup, 528 }; 529 530 static int bochs_connector_helper_get_modes(struct drm_connector *connector) 531 { 532 const struct drm_edid *edid; 533 int count; 534 535 edid = bochs_hw_read_edid(connector); 536 537 if (edid) { 538 drm_edid_connector_update(connector, edid); 539 count = drm_edid_connector_add_modes(connector); 540 drm_edid_free(edid); 541 } else { 542 drm_edid_connector_update(connector, NULL); 543 count = drm_add_modes_noedid(connector, 8192, 8192); 544 drm_set_preferred_mode(connector, defx, defy); 545 } 546 547 return count; 548 } 549 550 static const struct drm_connector_helper_funcs bochs_connector_helper_funcs = { 551 .get_modes = bochs_connector_helper_get_modes, 552 }; 553 554 static const struct drm_connector_funcs bochs_connector_funcs = { 555 .fill_modes = drm_helper_probe_single_connector_modes, 556 .destroy = drm_connector_cleanup, 557 .reset = drm_atomic_helper_connector_reset, 558 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 559 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 560 }; 561 562 static enum drm_mode_status bochs_mode_config_mode_valid(struct drm_device *dev, 563 const struct drm_display_mode *mode) 564 { 565 struct bochs_device *bochs = to_bochs_device(dev); 566 const struct drm_format_info *format = drm_format_info(DRM_FORMAT_XRGB8888); 567 u64 pitch; 568 569 if (drm_WARN_ON(dev, !format)) 570 return MODE_ERROR; 571 572 pitch = drm_format_info_min_pitch(format, 0, mode->hdisplay); 573 if (!pitch) 574 return MODE_BAD_WIDTH; 575 if (mode->vdisplay > DIV_ROUND_DOWN_ULL(bochs->fb_size, pitch)) 576 return MODE_MEM; 577 578 return MODE_OK; 579 } 580 581 static const struct drm_mode_config_funcs bochs_mode_config_funcs = { 582 .fb_create = drm_gem_fb_create_with_dirty, 583 .mode_valid = bochs_mode_config_mode_valid, 584 .atomic_check = drm_atomic_helper_check, 585 .atomic_commit = drm_atomic_helper_commit, 586 }; 587 588 static int bochs_kms_init(struct bochs_device *bochs) 589 { 590 struct drm_device *dev = &bochs->dev; 591 struct drm_plane *primary_plane; 592 struct drm_crtc *crtc; 593 struct drm_connector *connector; 594 struct drm_encoder *encoder; 595 int ret; 596 597 ret = drmm_mode_config_init(dev); 598 if (ret) 599 return ret; 600 601 dev->mode_config.max_width = 8192; 602 dev->mode_config.max_height = 8192; 603 604 dev->mode_config.preferred_depth = 24; 605 dev->mode_config.quirk_addfb_prefer_host_byte_order = true; 606 607 dev->mode_config.funcs = &bochs_mode_config_funcs; 608 609 primary_plane = &bochs->primary_plane; 610 ret = drm_universal_plane_init(dev, primary_plane, 0, 611 &bochs_primary_plane_funcs, 612 bochs_primary_plane_formats, 613 ARRAY_SIZE(bochs_primary_plane_formats), 614 NULL, 615 DRM_PLANE_TYPE_PRIMARY, NULL); 616 if (ret) 617 return ret; 618 drm_plane_helper_add(primary_plane, &bochs_primary_plane_helper_funcs); 619 drm_plane_enable_fb_damage_clips(primary_plane); 620 621 crtc = &bochs->crtc; 622 ret = drm_crtc_init_with_planes(dev, crtc, primary_plane, NULL, 623 &bochs_crtc_funcs, NULL); 624 if (ret) 625 return ret; 626 drm_crtc_helper_add(crtc, &bochs_crtc_helper_funcs); 627 628 encoder = &bochs->encoder; 629 ret = drm_encoder_init(dev, encoder, &bochs_encoder_funcs, 630 DRM_MODE_ENCODER_VIRTUAL, NULL); 631 if (ret) 632 return ret; 633 encoder->possible_crtcs = drm_crtc_mask(crtc); 634 635 connector = &bochs->connector; 636 ret = drm_connector_init(dev, connector, &bochs_connector_funcs, 637 DRM_MODE_CONNECTOR_VIRTUAL); 638 if (ret) 639 return ret; 640 drm_connector_helper_add(connector, &bochs_connector_helper_funcs); 641 drm_connector_attach_edid_property(connector); 642 drm_connector_attach_encoder(connector, encoder); 643 644 drm_mode_config_reset(dev); 645 646 return 0; 647 } 648 649 /* ---------------------------------------------------------------------- */ 650 /* drm interface */ 651 652 static int bochs_load(struct bochs_device *bochs) 653 { 654 int ret; 655 656 ret = bochs_hw_init(bochs); 657 if (ret) 658 return ret; 659 660 ret = bochs_kms_init(bochs); 661 if (ret) 662 return ret; 663 664 return 0; 665 } 666 667 DEFINE_DRM_GEM_FOPS(bochs_fops); 668 669 static const struct drm_driver bochs_driver = { 670 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC, 671 .fops = &bochs_fops, 672 .name = "bochs-drm", 673 .desc = "bochs dispi vga interface (qemu stdvga)", 674 .date = "20130925", 675 .major = 1, 676 .minor = 0, 677 DRM_GEM_SHMEM_DRIVER_OPS, 678 DRM_FBDEV_SHMEM_DRIVER_OPS, 679 }; 680 681 /* ---------------------------------------------------------------------- */ 682 /* pm interface */ 683 684 #ifdef CONFIG_PM_SLEEP 685 static int bochs_pm_suspend(struct device *dev) 686 { 687 struct drm_device *drm_dev = dev_get_drvdata(dev); 688 689 return drm_mode_config_helper_suspend(drm_dev); 690 } 691 692 static int bochs_pm_resume(struct device *dev) 693 { 694 struct drm_device *drm_dev = dev_get_drvdata(dev); 695 696 return drm_mode_config_helper_resume(drm_dev); 697 } 698 #endif 699 700 static const struct dev_pm_ops bochs_pm_ops = { 701 SET_SYSTEM_SLEEP_PM_OPS(bochs_pm_suspend, 702 bochs_pm_resume) 703 }; 704 705 /* ---------------------------------------------------------------------- */ 706 /* pci interface */ 707 708 static int bochs_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 709 { 710 struct bochs_device *bochs; 711 struct drm_device *dev; 712 int ret; 713 714 ret = aperture_remove_conflicting_pci_devices(pdev, bochs_driver.name); 715 if (ret) 716 return ret; 717 718 bochs = devm_drm_dev_alloc(&pdev->dev, &bochs_driver, struct bochs_device, dev); 719 if (IS_ERR(bochs)) 720 return PTR_ERR(bochs); 721 dev = &bochs->dev; 722 723 ret = pcim_enable_device(pdev); 724 if (ret) 725 goto err_free_dev; 726 727 pci_set_drvdata(pdev, dev); 728 729 ret = bochs_load(bochs); 730 if (ret) 731 goto err_free_dev; 732 733 ret = drm_dev_register(dev, 0); 734 if (ret) 735 goto err_free_dev; 736 737 drm_client_setup(dev, NULL); 738 739 return ret; 740 741 err_free_dev: 742 drm_dev_put(dev); 743 return ret; 744 } 745 746 static void bochs_pci_remove(struct pci_dev *pdev) 747 { 748 struct drm_device *dev = pci_get_drvdata(pdev); 749 750 drm_dev_unplug(dev); 751 drm_atomic_helper_shutdown(dev); 752 drm_dev_put(dev); 753 } 754 755 static void bochs_pci_shutdown(struct pci_dev *pdev) 756 { 757 drm_atomic_helper_shutdown(pci_get_drvdata(pdev)); 758 } 759 760 static const struct pci_device_id bochs_pci_tbl[] = { 761 { 762 .vendor = 0x1234, 763 .device = 0x1111, 764 .subvendor = PCI_SUBVENDOR_ID_REDHAT_QUMRANET, 765 .subdevice = PCI_SUBDEVICE_ID_QEMU, 766 .driver_data = BOCHS_QEMU_STDVGA, 767 }, 768 { 769 .vendor = 0x1234, 770 .device = 0x1111, 771 .subvendor = PCI_ANY_ID, 772 .subdevice = PCI_ANY_ID, 773 .driver_data = BOCHS_UNKNOWN, 774 }, 775 { 776 .vendor = 0x4321, 777 .device = 0x1111, 778 .subvendor = PCI_ANY_ID, 779 .subdevice = PCI_ANY_ID, 780 .driver_data = BOCHS_SIMICS, 781 }, 782 { /* end of list */ } 783 }; 784 785 static struct pci_driver bochs_pci_driver = { 786 .name = "bochs-drm", 787 .id_table = bochs_pci_tbl, 788 .probe = bochs_pci_probe, 789 .remove = bochs_pci_remove, 790 .shutdown = bochs_pci_shutdown, 791 .driver.pm = &bochs_pm_ops, 792 }; 793 794 /* ---------------------------------------------------------------------- */ 795 /* module init/exit */ 796 797 drm_module_pci_driver_if_modeset(bochs_pci_driver, bochs_modeset); 798 799 MODULE_DEVICE_TABLE(pci, bochs_pci_tbl); 800 MODULE_AUTHOR("Gerd Hoffmann <kraxel@redhat.com>"); 801 MODULE_DESCRIPTION("DRM Support for bochs dispi vga interface (qemu stdvga)"); 802 MODULE_LICENSE("GPL"); 803