1 // SPDX-License-Identifier: GPL-2.0-or-later 2 3 #include <linux/bug.h> 4 #include <linux/aperture.h> 5 #include <linux/module.h> 6 #include <linux/pci.h> 7 8 #include <drm/clients/drm_client_setup.h> 9 #include <drm/drm_atomic.h> 10 #include <drm/drm_atomic_helper.h> 11 #include <drm/drm_damage_helper.h> 12 #include <drm/drm_drv.h> 13 #include <drm/drm_edid.h> 14 #include <drm/drm_fbdev_shmem.h> 15 #include <drm/drm_fourcc.h> 16 #include <drm/drm_framebuffer.h> 17 #include <drm/drm_gem_atomic_helper.h> 18 #include <drm/drm_gem_framebuffer_helper.h> 19 #include <drm/drm_gem_shmem_helper.h> 20 #include <drm/drm_managed.h> 21 #include <drm/drm_module.h> 22 #include <drm/drm_panic.h> 23 #include <drm/drm_panic_helper.h> 24 #include <drm/drm_plane_helper.h> 25 #include <drm/drm_print.h> 26 #include <drm/drm_probe_helper.h> 27 #include <drm/drm_vblank.h> 28 #include <drm/drm_vblank_helper.h> 29 30 #include <video/vga.h> 31 32 /* ---------------------------------------------------------------------- */ 33 34 #define VBE_DISPI_IOPORT_INDEX 0x01CE 35 #define VBE_DISPI_IOPORT_DATA 0x01CF 36 37 #define VBE_DISPI_INDEX_ID 0x0 38 #define VBE_DISPI_INDEX_XRES 0x1 39 #define VBE_DISPI_INDEX_YRES 0x2 40 #define VBE_DISPI_INDEX_BPP 0x3 41 #define VBE_DISPI_INDEX_ENABLE 0x4 42 #define VBE_DISPI_INDEX_BANK 0x5 43 #define VBE_DISPI_INDEX_VIRT_WIDTH 0x6 44 #define VBE_DISPI_INDEX_VIRT_HEIGHT 0x7 45 #define VBE_DISPI_INDEX_X_OFFSET 0x8 46 #define VBE_DISPI_INDEX_Y_OFFSET 0x9 47 #define VBE_DISPI_INDEX_VIDEO_MEMORY_64K 0xa 48 49 #define VBE_DISPI_ID0 0xB0C0 50 #define VBE_DISPI_ID1 0xB0C1 51 #define VBE_DISPI_ID2 0xB0C2 52 #define VBE_DISPI_ID3 0xB0C3 53 #define VBE_DISPI_ID4 0xB0C4 54 #define VBE_DISPI_ID5 0xB0C5 55 56 #define VBE_DISPI_DISABLED 0x00 57 #define VBE_DISPI_ENABLED 0x01 58 #define VBE_DISPI_GETCAPS 0x02 59 #define VBE_DISPI_8BIT_DAC 0x20 60 #define VBE_DISPI_LFB_ENABLED 0x40 61 #define VBE_DISPI_NOCLEARMEM 0x80 62 63 static int bochs_modeset = -1; 64 static int defx = 1024; 65 static int defy = 768; 66 67 module_param_named(modeset, bochs_modeset, int, 0444); 68 MODULE_PARM_DESC(modeset, "enable/disable kernel modesetting"); 69 70 module_param(defx, int, 0444); 71 module_param(defy, int, 0444); 72 MODULE_PARM_DESC(defx, "default x resolution"); 73 MODULE_PARM_DESC(defy, "default y resolution"); 74 75 /* ---------------------------------------------------------------------- */ 76 77 enum bochs_types { 78 BOCHS_QEMU_STDVGA, 79 BOCHS_SIMICS, 80 BOCHS_UNKNOWN, 81 }; 82 83 struct bochs_device { 84 struct drm_device dev; 85 86 /* hw */ 87 void __iomem *mmio; 88 int ioports; 89 void __iomem *fb_map; 90 unsigned long fb_base; 91 unsigned long fb_size; 92 unsigned long qext_size; 93 94 /* mode */ 95 u16 xres; 96 u16 yres; 97 u16 yres_virtual; 98 u32 stride; 99 u32 bpp; 100 101 /* drm */ 102 struct drm_plane primary_plane; 103 struct drm_crtc crtc; 104 struct drm_encoder encoder; 105 struct drm_connector connector; 106 }; 107 108 static struct bochs_device *to_bochs_device(const struct drm_device *dev) 109 { 110 return container_of(dev, struct bochs_device, dev); 111 } 112 113 /* ---------------------------------------------------------------------- */ 114 115 static __always_inline bool bochs_uses_mmio(struct bochs_device *bochs) 116 { 117 return !IS_ENABLED(CONFIG_HAS_IOPORT) || bochs->mmio; 118 } 119 120 static void bochs_vga_writeb(struct bochs_device *bochs, u16 ioport, u8 val) 121 { 122 if (WARN_ON(ioport < 0x3c0 || ioport > 0x3df)) 123 return; 124 125 if (bochs_uses_mmio(bochs)) { 126 int offset = ioport - 0x3c0 + 0x400; 127 128 writeb(val, bochs->mmio + offset); 129 } else { 130 outb(val, ioport); 131 } 132 } 133 134 static u8 bochs_vga_readb(struct bochs_device *bochs, u16 ioport) 135 { 136 if (WARN_ON(ioport < 0x3c0 || ioport > 0x3df)) 137 return 0xff; 138 139 if (bochs_uses_mmio(bochs)) { 140 int offset = ioport - 0x3c0 + 0x400; 141 142 return readb(bochs->mmio + offset); 143 } else { 144 return inb(ioport); 145 } 146 } 147 148 static u16 bochs_dispi_read(struct bochs_device *bochs, u16 reg) 149 { 150 u16 ret = 0; 151 152 if (bochs_uses_mmio(bochs)) { 153 int offset = 0x500 + (reg << 1); 154 155 ret = readw(bochs->mmio + offset); 156 } else { 157 outw(reg, VBE_DISPI_IOPORT_INDEX); 158 ret = inw(VBE_DISPI_IOPORT_DATA); 159 } 160 return ret; 161 } 162 163 static void bochs_dispi_write(struct bochs_device *bochs, u16 reg, u16 val) 164 { 165 if (bochs_uses_mmio(bochs)) { 166 int offset = 0x500 + (reg << 1); 167 168 writew(val, bochs->mmio + offset); 169 } else { 170 outw(reg, VBE_DISPI_IOPORT_INDEX); 171 outw(val, VBE_DISPI_IOPORT_DATA); 172 } 173 } 174 175 static void bochs_hw_set_big_endian(struct bochs_device *bochs) 176 { 177 if (bochs->qext_size < 8) 178 return; 179 180 writel(0xbebebebe, bochs->mmio + 0x604); 181 } 182 183 static void bochs_hw_set_little_endian(struct bochs_device *bochs) 184 { 185 if (bochs->qext_size < 8) 186 return; 187 188 writel(0x1e1e1e1e, bochs->mmio + 0x604); 189 } 190 191 #ifdef __BIG_ENDIAN 192 #define bochs_hw_set_native_endian(_b) bochs_hw_set_big_endian(_b) 193 #else 194 #define bochs_hw_set_native_endian(_b) bochs_hw_set_little_endian(_b) 195 #endif 196 197 static int bochs_get_edid_block(void *data, u8 *buf, unsigned int block, size_t len) 198 { 199 struct bochs_device *bochs = data; 200 size_t i, start = block * EDID_LENGTH; 201 202 if (!bochs->mmio) 203 return -1; 204 205 if (start + len > 0x400 /* vga register offset */) 206 return -1; 207 208 for (i = 0; i < len; i++) 209 buf[i] = readb(bochs->mmio + start + i); 210 211 return 0; 212 } 213 214 static const struct drm_edid *bochs_hw_read_edid(struct drm_connector *connector) 215 { 216 struct drm_device *dev = connector->dev; 217 struct bochs_device *bochs = to_bochs_device(dev); 218 u8 header[8]; 219 220 /* check header to detect whenever edid support is enabled in qemu */ 221 bochs_get_edid_block(bochs, header, 0, ARRAY_SIZE(header)); 222 if (drm_edid_header_is_valid(header) != 8) 223 return NULL; 224 225 drm_dbg(dev, "Found EDID data blob.\n"); 226 227 return drm_edid_read_custom(connector, bochs_get_edid_block, bochs); 228 } 229 230 static int bochs_hw_init(struct bochs_device *bochs) 231 { 232 struct drm_device *dev = &bochs->dev; 233 struct pci_dev *pdev = to_pci_dev(dev->dev); 234 unsigned long addr, size, mem, ioaddr, iosize; 235 u16 id; 236 237 if (pdev->resource[2].flags & IORESOURCE_MEM) { 238 ioaddr = pci_resource_start(pdev, 2); 239 iosize = pci_resource_len(pdev, 2); 240 /* mmio bar with vga and bochs registers present */ 241 if (!devm_request_mem_region(&pdev->dev, ioaddr, iosize, "bochs-drm")) { 242 DRM_ERROR("Cannot request mmio region\n"); 243 return -EBUSY; 244 } 245 bochs->mmio = devm_ioremap(&pdev->dev, ioaddr, iosize); 246 if (bochs->mmio == NULL) { 247 DRM_ERROR("Cannot map mmio region\n"); 248 return -ENOMEM; 249 } 250 } else if (IS_ENABLED(CONFIG_HAS_IOPORT)) { 251 ioaddr = VBE_DISPI_IOPORT_INDEX; 252 iosize = 2; 253 if (!devm_request_region(&pdev->dev, ioaddr, iosize, "bochs-drm")) { 254 DRM_ERROR("Cannot request ioports\n"); 255 return -EBUSY; 256 } 257 bochs->ioports = 1; 258 } else { 259 drm_err(dev, "I/O ports are not supported\n"); 260 return -EIO; 261 } 262 263 id = bochs_dispi_read(bochs, VBE_DISPI_INDEX_ID); 264 mem = bochs_dispi_read(bochs, VBE_DISPI_INDEX_VIDEO_MEMORY_64K) 265 * 64 * 1024; 266 if ((id & 0xfff0) != VBE_DISPI_ID0) { 267 DRM_ERROR("ID mismatch\n"); 268 return -ENODEV; 269 } 270 271 if ((pdev->resource[0].flags & IORESOURCE_MEM) == 0) 272 return -ENODEV; 273 addr = pci_resource_start(pdev, 0); 274 size = pci_resource_len(pdev, 0); 275 if (addr == 0) 276 return -ENODEV; 277 if (size != mem) { 278 DRM_ERROR("Size mismatch: pci=%ld, bochs=%ld\n", 279 size, mem); 280 size = min(size, mem); 281 } 282 283 if (!devm_request_mem_region(&pdev->dev, addr, size, "bochs-drm")) 284 DRM_WARN("Cannot request framebuffer, boot fb still active?\n"); 285 286 bochs->fb_map = devm_ioremap_wc(&pdev->dev, addr, size); 287 if (bochs->fb_map == NULL) { 288 DRM_ERROR("Cannot map framebuffer\n"); 289 return -ENOMEM; 290 } 291 bochs->fb_base = addr; 292 bochs->fb_size = size; 293 294 DRM_INFO("Found bochs VGA, ID 0x%x.\n", id); 295 DRM_INFO("Framebuffer size %ld kB @ 0x%lx, %s @ 0x%lx.\n", 296 size / 1024, addr, 297 bochs->ioports ? "ioports" : "mmio", 298 ioaddr); 299 300 if (bochs->mmio && pdev->revision >= 2) { 301 bochs->qext_size = readl(bochs->mmio + 0x600); 302 if (bochs->qext_size < 4 || bochs->qext_size > iosize) { 303 bochs->qext_size = 0; 304 goto noext; 305 } 306 DRM_DEBUG("Found qemu ext regs, size %ld\n", 307 bochs->qext_size); 308 bochs_hw_set_native_endian(bochs); 309 } 310 311 noext: 312 return 0; 313 } 314 315 static void bochs_hw_blank(struct bochs_device *bochs, bool blank) 316 { 317 DRM_DEBUG_DRIVER("hw_blank %d\n", blank); 318 /* enable color bit (so VGA_IS1_RC access works) */ 319 bochs_vga_writeb(bochs, VGA_MIS_W, VGA_MIS_COLOR); 320 /* discard ar_flip_flop */ 321 (void)bochs_vga_readb(bochs, VGA_IS1_RC); 322 /* blank or unblank; we need only update index and set 0x20 */ 323 bochs_vga_writeb(bochs, VGA_ATT_W, blank ? 0 : 0x20); 324 } 325 326 static void bochs_hw_setmode(struct bochs_device *bochs, struct drm_display_mode *mode) 327 { 328 int idx; 329 330 if (!drm_dev_enter(&bochs->dev, &idx)) 331 return; 332 333 bochs->xres = mode->hdisplay; 334 bochs->yres = mode->vdisplay; 335 bochs->bpp = 32; 336 bochs->stride = mode->hdisplay * (bochs->bpp / 8); 337 bochs->yres_virtual = bochs->fb_size / bochs->stride; 338 339 DRM_DEBUG_DRIVER("%dx%d @ %d bpp, vy %d\n", 340 bochs->xres, bochs->yres, bochs->bpp, 341 bochs->yres_virtual); 342 343 bochs_dispi_write(bochs, VBE_DISPI_INDEX_ENABLE, 0); 344 bochs_dispi_write(bochs, VBE_DISPI_INDEX_BPP, bochs->bpp); 345 bochs_dispi_write(bochs, VBE_DISPI_INDEX_XRES, bochs->xres); 346 bochs_dispi_write(bochs, VBE_DISPI_INDEX_YRES, bochs->yres); 347 bochs_dispi_write(bochs, VBE_DISPI_INDEX_BANK, 0); 348 bochs_dispi_write(bochs, VBE_DISPI_INDEX_VIRT_WIDTH, bochs->xres); 349 bochs_dispi_write(bochs, VBE_DISPI_INDEX_VIRT_HEIGHT, 350 bochs->yres_virtual); 351 bochs_dispi_write(bochs, VBE_DISPI_INDEX_X_OFFSET, 0); 352 bochs_dispi_write(bochs, VBE_DISPI_INDEX_Y_OFFSET, 0); 353 354 bochs_dispi_write(bochs, VBE_DISPI_INDEX_ENABLE, 355 VBE_DISPI_ENABLED | VBE_DISPI_LFB_ENABLED); 356 357 drm_dev_exit(idx); 358 } 359 360 static void bochs_hw_setformat(struct bochs_device *bochs, const struct drm_format_info *format) 361 { 362 int idx; 363 364 if (!drm_dev_enter(&bochs->dev, &idx)) 365 return; 366 367 DRM_DEBUG_DRIVER("format %c%c%c%c\n", 368 (format->format >> 0) & 0xff, 369 (format->format >> 8) & 0xff, 370 (format->format >> 16) & 0xff, 371 (format->format >> 24) & 0xff); 372 373 switch (format->format) { 374 case DRM_FORMAT_XRGB8888: 375 bochs_hw_set_little_endian(bochs); 376 break; 377 case DRM_FORMAT_BGRX8888: 378 bochs_hw_set_big_endian(bochs); 379 break; 380 default: 381 /* should not happen */ 382 DRM_ERROR("%s: Huh? Got framebuffer format 0x%x", 383 __func__, format->format); 384 break; 385 } 386 387 drm_dev_exit(idx); 388 } 389 390 static void bochs_hw_setbase(struct bochs_device *bochs, int x, int y, int stride, u64 addr) 391 { 392 unsigned long offset; 393 unsigned int vx, vy, vwidth, idx; 394 395 if (!drm_dev_enter(&bochs->dev, &idx)) 396 return; 397 398 bochs->stride = stride; 399 offset = (unsigned long)addr + 400 y * bochs->stride + 401 x * (bochs->bpp / 8); 402 vy = offset / bochs->stride; 403 vx = (offset % bochs->stride) * 8 / bochs->bpp; 404 vwidth = stride * 8 / bochs->bpp; 405 406 DRM_DEBUG_DRIVER("x %d, y %d, addr %llx -> offset %lx, vx %d, vy %d\n", 407 x, y, addr, offset, vx, vy); 408 bochs_dispi_write(bochs, VBE_DISPI_INDEX_VIRT_WIDTH, vwidth); 409 bochs_dispi_write(bochs, VBE_DISPI_INDEX_X_OFFSET, vx); 410 bochs_dispi_write(bochs, VBE_DISPI_INDEX_Y_OFFSET, vy); 411 412 drm_dev_exit(idx); 413 } 414 415 /* ---------------------------------------------------------------------- */ 416 417 static const uint32_t bochs_primary_plane_formats[] = { 418 DRM_FORMAT_XRGB8888, 419 DRM_FORMAT_BGRX8888, 420 }; 421 422 static int bochs_primary_plane_helper_atomic_check(struct drm_plane *plane, 423 struct drm_atomic_commit *state) 424 { 425 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); 426 struct drm_crtc *new_crtc = new_plane_state->crtc; 427 struct drm_crtc_state *new_crtc_state = NULL; 428 int ret; 429 430 if (new_crtc) 431 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc); 432 433 ret = drm_atomic_helper_check_plane_state(new_plane_state, new_crtc_state, 434 DRM_PLANE_NO_SCALING, 435 DRM_PLANE_NO_SCALING, 436 false, false); 437 if (ret) 438 return ret; 439 else if (!new_plane_state->visible) 440 return 0; 441 442 return 0; 443 } 444 445 static void bochs_primary_plane_helper_atomic_update(struct drm_plane *plane, 446 struct drm_atomic_commit *state) 447 { 448 struct drm_device *dev = plane->dev; 449 struct bochs_device *bochs = to_bochs_device(dev); 450 struct drm_plane_state *plane_state = plane->state; 451 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane); 452 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state); 453 struct drm_framebuffer *fb = plane_state->fb; 454 struct drm_atomic_helper_damage_iter iter; 455 struct drm_rect damage; 456 457 if (!fb || !bochs->stride) 458 return; 459 460 drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state); 461 drm_atomic_for_each_plane_damage(&iter, &damage) { 462 struct iosys_map dst = IOSYS_MAP_INIT_VADDR_IOMEM(bochs->fb_map); 463 464 iosys_map_incr(&dst, drm_fb_clip_offset(fb->pitches[0], fb->format, &damage)); 465 drm_fb_memcpy(&dst, fb->pitches, shadow_plane_state->data, fb, &damage); 466 } 467 468 /* Always scanout image at VRAM offset 0 */ 469 bochs_hw_setbase(bochs, 470 plane_state->crtc_x, 471 plane_state->crtc_y, 472 fb->pitches[0], 473 0); 474 bochs_hw_setformat(bochs, fb->format); 475 } 476 477 static int bochs_primary_plane_helper_get_scanout_buffer(struct drm_plane *plane, 478 struct drm_scanout_buffer *sb) 479 { 480 struct bochs_device *bochs = to_bochs_device(plane->dev); 481 struct iosys_map map = IOSYS_MAP_INIT_VADDR_IOMEM(bochs->fb_map); 482 483 if (plane->state && plane->state->fb) { 484 sb->format = plane->state->fb->format; 485 sb->width = plane->state->fb->width; 486 sb->height = plane->state->fb->height; 487 sb->pitch[0] = plane->state->fb->pitches[0]; 488 sb->map[0] = map; 489 return 0; 490 } 491 return -ENODEV; 492 } 493 494 static const struct drm_plane_helper_funcs bochs_primary_plane_helper_funcs = { 495 DRM_GEM_SHADOW_PLANE_HELPER_FUNCS, 496 .atomic_check = bochs_primary_plane_helper_atomic_check, 497 .atomic_update = bochs_primary_plane_helper_atomic_update, 498 .get_scanout_buffer = bochs_primary_plane_helper_get_scanout_buffer, 499 }; 500 501 static const struct drm_plane_funcs bochs_primary_plane_funcs = { 502 .update_plane = drm_atomic_helper_update_plane, 503 .disable_plane = drm_atomic_helper_disable_plane, 504 .destroy = drm_plane_cleanup, 505 DRM_GEM_SHADOW_PLANE_FUNCS, 506 DRM_PANIC_PLANE_FUNCS, 507 }; 508 509 static void bochs_crtc_helper_mode_set_nofb(struct drm_crtc *crtc) 510 { 511 struct bochs_device *bochs = to_bochs_device(crtc->dev); 512 struct drm_crtc_state *crtc_state = crtc->state; 513 514 bochs_hw_setmode(bochs, &crtc_state->mode); 515 } 516 517 static int bochs_crtc_helper_atomic_check(struct drm_crtc *crtc, 518 struct drm_atomic_commit *state) 519 { 520 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 521 522 if (!crtc_state->enable) 523 return 0; 524 525 return drm_atomic_helper_check_crtc_primary_plane(crtc_state); 526 } 527 528 static void bochs_crtc_helper_atomic_enable(struct drm_crtc *crtc, 529 struct drm_atomic_commit *state) 530 { 531 struct bochs_device *bochs = to_bochs_device(crtc->dev); 532 533 bochs_hw_blank(bochs, false); 534 drm_crtc_vblank_on(crtc); 535 } 536 537 static void bochs_crtc_helper_atomic_disable(struct drm_crtc *crtc, 538 struct drm_atomic_commit *crtc_state) 539 { 540 struct bochs_device *bochs = to_bochs_device(crtc->dev); 541 542 drm_crtc_vblank_off(crtc); 543 bochs_hw_blank(bochs, true); 544 } 545 546 static const struct drm_crtc_helper_funcs bochs_crtc_helper_funcs = { 547 .mode_set_nofb = bochs_crtc_helper_mode_set_nofb, 548 .atomic_check = bochs_crtc_helper_atomic_check, 549 .atomic_flush = drm_crtc_vblank_atomic_flush, 550 .atomic_enable = bochs_crtc_helper_atomic_enable, 551 .atomic_disable = bochs_crtc_helper_atomic_disable, 552 }; 553 554 static const struct drm_crtc_funcs bochs_crtc_funcs = { 555 .atomic_create_state = drm_atomic_helper_crtc_create_state, 556 .destroy = drm_crtc_cleanup, 557 .set_config = drm_atomic_helper_set_config, 558 .page_flip = drm_atomic_helper_page_flip, 559 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 560 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 561 DRM_CRTC_VBLANK_TIMER_FUNCS, 562 }; 563 564 static const struct drm_encoder_funcs bochs_encoder_funcs = { 565 .destroy = drm_encoder_cleanup, 566 }; 567 568 static int bochs_connector_helper_get_modes(struct drm_connector *connector) 569 { 570 const struct drm_edid *edid; 571 int count; 572 573 edid = bochs_hw_read_edid(connector); 574 575 if (edid) { 576 drm_edid_connector_update(connector, edid); 577 count = drm_edid_connector_add_modes(connector); 578 drm_edid_free(edid); 579 } else { 580 drm_edid_connector_update(connector, NULL); 581 count = drm_add_modes_noedid(connector, 8192, 8192); 582 drm_set_preferred_mode(connector, defx, defy); 583 } 584 585 return count; 586 } 587 588 static const struct drm_connector_helper_funcs bochs_connector_helper_funcs = { 589 .get_modes = bochs_connector_helper_get_modes, 590 }; 591 592 static const struct drm_connector_funcs bochs_connector_funcs = { 593 .fill_modes = drm_helper_probe_single_connector_modes, 594 .destroy = drm_connector_cleanup, 595 .reset = drm_atomic_helper_connector_reset, 596 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 597 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 598 }; 599 600 static enum drm_mode_status bochs_mode_config_mode_valid(struct drm_device *dev, 601 const struct drm_display_mode *mode) 602 { 603 struct bochs_device *bochs = to_bochs_device(dev); 604 const struct drm_format_info *format = drm_format_info(DRM_FORMAT_XRGB8888); 605 u64 pitch; 606 607 if (drm_WARN_ON(dev, !format)) 608 return MODE_ERROR; 609 610 pitch = drm_format_info_min_pitch(format, 0, mode->hdisplay); 611 if (!pitch) 612 return MODE_BAD_WIDTH; 613 if (mode->vdisplay > DIV_ROUND_DOWN_ULL(bochs->fb_size, pitch)) 614 return MODE_MEM; 615 616 return MODE_OK; 617 } 618 619 static const struct drm_mode_config_funcs bochs_mode_config_funcs = { 620 .fb_create = drm_gem_fb_create_with_dirty, 621 .mode_valid = bochs_mode_config_mode_valid, 622 .atomic_check = drm_atomic_helper_check, 623 .atomic_commit = drm_atomic_helper_commit, 624 }; 625 626 static int bochs_kms_init(struct bochs_device *bochs) 627 { 628 struct drm_device *dev = &bochs->dev; 629 struct drm_plane *primary_plane; 630 struct drm_crtc *crtc; 631 struct drm_connector *connector; 632 struct drm_encoder *encoder; 633 int ret; 634 635 ret = drmm_mode_config_init(dev); 636 if (ret) 637 return ret; 638 639 dev->mode_config.max_width = 8192; 640 dev->mode_config.max_height = 8192; 641 642 dev->mode_config.preferred_depth = 24; 643 dev->mode_config.quirk_addfb_prefer_host_byte_order = true; 644 645 dev->mode_config.funcs = &bochs_mode_config_funcs; 646 647 primary_plane = &bochs->primary_plane; 648 ret = drm_universal_plane_init(dev, primary_plane, 0, 649 &bochs_primary_plane_funcs, 650 bochs_primary_plane_formats, 651 ARRAY_SIZE(bochs_primary_plane_formats), 652 NULL, 653 DRM_PLANE_TYPE_PRIMARY, NULL); 654 if (ret) 655 return ret; 656 drm_plane_helper_add(primary_plane, &bochs_primary_plane_helper_funcs); 657 drm_plane_enable_fb_damage_clips(primary_plane); 658 659 crtc = &bochs->crtc; 660 ret = drm_crtc_init_with_planes(dev, crtc, primary_plane, NULL, 661 &bochs_crtc_funcs, NULL); 662 if (ret) 663 return ret; 664 drm_crtc_helper_add(crtc, &bochs_crtc_helper_funcs); 665 666 encoder = &bochs->encoder; 667 ret = drm_encoder_init(dev, encoder, &bochs_encoder_funcs, 668 DRM_MODE_ENCODER_VIRTUAL, NULL); 669 if (ret) 670 return ret; 671 encoder->possible_crtcs = drm_crtc_mask(crtc); 672 673 connector = &bochs->connector; 674 ret = drm_connector_init(dev, connector, &bochs_connector_funcs, 675 DRM_MODE_CONNECTOR_VIRTUAL); 676 if (ret) 677 return ret; 678 drm_connector_helper_add(connector, &bochs_connector_helper_funcs); 679 drm_connector_attach_edid_property(connector); 680 drm_connector_attach_encoder(connector, encoder); 681 682 ret = drm_vblank_init(dev, 1); 683 if (ret) 684 return ret; 685 686 drm_mode_config_reset(dev); 687 688 return 0; 689 } 690 691 /* ---------------------------------------------------------------------- */ 692 /* drm interface */ 693 694 static int bochs_load(struct bochs_device *bochs) 695 { 696 int ret; 697 698 ret = bochs_hw_init(bochs); 699 if (ret) 700 return ret; 701 702 ret = bochs_kms_init(bochs); 703 if (ret) 704 return ret; 705 706 return 0; 707 } 708 709 DEFINE_DRM_GEM_FOPS(bochs_fops); 710 711 static const struct drm_driver bochs_driver = { 712 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC, 713 .fops = &bochs_fops, 714 .name = "bochs-drm", 715 .desc = "bochs dispi vga interface (qemu stdvga)", 716 .major = 1, 717 .minor = 0, 718 DRM_GEM_SHMEM_DRIVER_OPS, 719 DRM_FBDEV_SHMEM_DRIVER_OPS, 720 }; 721 722 /* ---------------------------------------------------------------------- */ 723 /* pm interface */ 724 725 #ifdef CONFIG_PM_SLEEP 726 static int bochs_pm_suspend(struct device *dev) 727 { 728 struct drm_device *drm_dev = dev_get_drvdata(dev); 729 730 return drm_mode_config_helper_suspend(drm_dev); 731 } 732 733 static int bochs_pm_resume(struct device *dev) 734 { 735 struct drm_device *drm_dev = dev_get_drvdata(dev); 736 737 return drm_mode_config_helper_resume(drm_dev); 738 } 739 #endif 740 741 static const struct dev_pm_ops bochs_pm_ops = { 742 SET_SYSTEM_SLEEP_PM_OPS(bochs_pm_suspend, 743 bochs_pm_resume) 744 }; 745 746 /* ---------------------------------------------------------------------- */ 747 /* pci interface */ 748 749 static int bochs_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 750 { 751 struct bochs_device *bochs; 752 struct drm_device *dev; 753 int ret; 754 755 ret = aperture_remove_conflicting_pci_devices(pdev, bochs_driver.name); 756 if (ret) 757 return ret; 758 759 bochs = devm_drm_dev_alloc(&pdev->dev, &bochs_driver, struct bochs_device, dev); 760 if (IS_ERR(bochs)) 761 return PTR_ERR(bochs); 762 dev = &bochs->dev; 763 764 ret = pcim_enable_device(pdev); 765 if (ret) 766 return ret; 767 768 pci_set_drvdata(pdev, dev); 769 770 ret = bochs_load(bochs); 771 if (ret) 772 return ret; 773 774 ret = drm_dev_register(dev, 0); 775 if (ret) 776 return ret; 777 778 drm_client_setup(dev, NULL); 779 780 return ret; 781 } 782 783 static void bochs_pci_remove(struct pci_dev *pdev) 784 { 785 struct drm_device *dev = pci_get_drvdata(pdev); 786 787 drm_dev_unplug(dev); 788 drm_atomic_helper_shutdown(dev); 789 } 790 791 static void bochs_pci_shutdown(struct pci_dev *pdev) 792 { 793 drm_atomic_helper_shutdown(pci_get_drvdata(pdev)); 794 } 795 796 static const struct pci_device_id bochs_pci_tbl[] = { 797 { 798 .vendor = 0x1234, 799 .device = 0x1111, 800 .subvendor = PCI_SUBVENDOR_ID_REDHAT_QUMRANET, 801 .subdevice = PCI_SUBDEVICE_ID_QEMU, 802 .driver_data = BOCHS_QEMU_STDVGA, 803 }, 804 { 805 .vendor = 0x1234, 806 .device = 0x1111, 807 .subvendor = PCI_ANY_ID, 808 .subdevice = PCI_ANY_ID, 809 .driver_data = BOCHS_UNKNOWN, 810 }, 811 { 812 .vendor = 0x4321, 813 .device = 0x1111, 814 .subvendor = PCI_ANY_ID, 815 .subdevice = PCI_ANY_ID, 816 .driver_data = BOCHS_SIMICS, 817 }, 818 { /* end of list */ } 819 }; 820 821 static struct pci_driver bochs_pci_driver = { 822 .name = "bochs-drm", 823 .id_table = bochs_pci_tbl, 824 .probe = bochs_pci_probe, 825 .remove = bochs_pci_remove, 826 .shutdown = bochs_pci_shutdown, 827 .driver.pm = &bochs_pm_ops, 828 }; 829 830 /* ---------------------------------------------------------------------- */ 831 /* module init/exit */ 832 833 drm_module_pci_driver_if_modeset(bochs_pci_driver, bochs_modeset); 834 835 MODULE_DEVICE_TABLE(pci, bochs_pci_tbl); 836 MODULE_AUTHOR("Gerd Hoffmann <kraxel@redhat.com>"); 837 MODULE_DESCRIPTION("DRM Support for bochs dispi vga interface (qemu stdvga)"); 838 MODULE_LICENSE("GPL"); 839