1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ARC PGU DRM driver. 4 * 5 * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com) 6 */ 7 8 #include <linux/clk.h> 9 10 #include <drm/clients/drm_client_setup.h> 11 #include <drm/drm_atomic_helper.h> 12 #include <drm/drm_debugfs.h> 13 #include <drm/drm_device.h> 14 #include <drm/drm_drv.h> 15 #include <drm/drm_edid.h> 16 #include <drm/drm_fb_dma_helper.h> 17 #include <drm/drm_fbdev_dma.h> 18 #include <drm/drm_fourcc.h> 19 #include <drm/drm_framebuffer.h> 20 #include <drm/drm_gem_dma_helper.h> 21 #include <drm/drm_gem_framebuffer_helper.h> 22 #include <drm/drm_module.h> 23 #include <drm/drm_of.h> 24 #include <drm/drm_probe_helper.h> 25 #include <drm/drm_simple_kms_helper.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/module.h> 28 #include <linux/of_reserved_mem.h> 29 #include <linux/platform_device.h> 30 31 #define ARCPGU_REG_CTRL 0x00 32 #define ARCPGU_REG_STAT 0x04 33 #define ARCPGU_REG_FMT 0x10 34 #define ARCPGU_REG_HSYNC 0x14 35 #define ARCPGU_REG_VSYNC 0x18 36 #define ARCPGU_REG_ACTIVE 0x1c 37 #define ARCPGU_REG_BUF0_ADDR 0x40 38 #define ARCPGU_REG_STRIDE 0x50 39 #define ARCPGU_REG_START_SET 0x84 40 41 #define ARCPGU_REG_ID 0x3FC 42 43 #define ARCPGU_CTRL_ENABLE_MASK 0x02 44 #define ARCPGU_CTRL_VS_POL_MASK 0x1 45 #define ARCPGU_CTRL_VS_POL_OFST 0x3 46 #define ARCPGU_CTRL_HS_POL_MASK 0x1 47 #define ARCPGU_CTRL_HS_POL_OFST 0x4 48 #define ARCPGU_MODE_XRGB8888 BIT(2) 49 #define ARCPGU_STAT_BUSY_MASK 0x02 50 51 struct arcpgu_drm_private { 52 struct drm_device drm; 53 void __iomem *regs; 54 struct clk *clk; 55 struct drm_simple_display_pipe pipe; 56 struct drm_connector sim_conn; 57 }; 58 59 #define dev_to_arcpgu(x) container_of(x, struct arcpgu_drm_private, drm) 60 61 #define pipe_to_arcpgu_priv(x) container_of(x, struct arcpgu_drm_private, pipe) 62 63 static inline void arc_pgu_write(struct arcpgu_drm_private *arcpgu, 64 unsigned int reg, u32 value) 65 { 66 iowrite32(value, arcpgu->regs + reg); 67 } 68 69 static inline u32 arc_pgu_read(struct arcpgu_drm_private *arcpgu, 70 unsigned int reg) 71 { 72 return ioread32(arcpgu->regs + reg); 73 } 74 75 #define XRES_DEF 640 76 #define YRES_DEF 480 77 78 #define XRES_MAX 8192 79 #define YRES_MAX 8192 80 81 static int arcpgu_drm_connector_get_modes(struct drm_connector *connector) 82 { 83 int count; 84 85 count = drm_add_modes_noedid(connector, XRES_MAX, YRES_MAX); 86 drm_set_preferred_mode(connector, XRES_DEF, YRES_DEF); 87 return count; 88 } 89 90 static const struct drm_connector_helper_funcs 91 arcpgu_drm_connector_helper_funcs = { 92 .get_modes = arcpgu_drm_connector_get_modes, 93 }; 94 95 static const struct drm_connector_funcs arcpgu_drm_connector_funcs = { 96 .reset = drm_atomic_helper_connector_reset, 97 .fill_modes = drm_helper_probe_single_connector_modes, 98 .destroy = drm_connector_cleanup, 99 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 100 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 101 }; 102 103 static int arcpgu_drm_sim_init(struct drm_device *drm, struct drm_connector *connector) 104 { 105 drm_connector_helper_add(connector, &arcpgu_drm_connector_helper_funcs); 106 return drm_connector_init(drm, connector, &arcpgu_drm_connector_funcs, 107 DRM_MODE_CONNECTOR_VIRTUAL); 108 } 109 110 #define ENCODE_PGU_XY(x, y) ((((x) - 1) << 16) | ((y) - 1)) 111 112 static const u32 arc_pgu_supported_formats[] = { 113 DRM_FORMAT_RGB565, 114 DRM_FORMAT_XRGB8888, 115 DRM_FORMAT_ARGB8888, 116 }; 117 118 static void arc_pgu_set_pxl_fmt(struct arcpgu_drm_private *arcpgu) 119 { 120 const struct drm_framebuffer *fb = arcpgu->pipe.plane.state->fb; 121 uint32_t pixel_format = fb->format->format; 122 u32 format = DRM_FORMAT_INVALID; 123 int i; 124 u32 reg_ctrl; 125 126 for (i = 0; i < ARRAY_SIZE(arc_pgu_supported_formats); i++) { 127 if (arc_pgu_supported_formats[i] == pixel_format) 128 format = arc_pgu_supported_formats[i]; 129 } 130 131 if (WARN_ON(format == DRM_FORMAT_INVALID)) 132 return; 133 134 reg_ctrl = arc_pgu_read(arcpgu, ARCPGU_REG_CTRL); 135 if (format == DRM_FORMAT_RGB565) 136 reg_ctrl &= ~ARCPGU_MODE_XRGB8888; 137 else 138 reg_ctrl |= ARCPGU_MODE_XRGB8888; 139 arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, reg_ctrl); 140 } 141 142 static enum drm_mode_status arc_pgu_mode_valid(struct drm_simple_display_pipe *pipe, 143 const struct drm_display_mode *mode) 144 { 145 struct arcpgu_drm_private *arcpgu = pipe_to_arcpgu_priv(pipe); 146 long rate, clk_rate = mode->clock * 1000; 147 long diff = clk_rate / 200; /* +-0.5% allowed by HDMI spec */ 148 149 rate = clk_round_rate(arcpgu->clk, clk_rate); 150 if ((max(rate, clk_rate) - min(rate, clk_rate) < diff) && (rate > 0)) 151 return MODE_OK; 152 153 return MODE_NOCLOCK; 154 } 155 156 static void arc_pgu_mode_set(struct arcpgu_drm_private *arcpgu) 157 { 158 struct drm_display_mode *m = &arcpgu->pipe.crtc.state->adjusted_mode; 159 u32 val; 160 161 arc_pgu_write(arcpgu, ARCPGU_REG_FMT, 162 ENCODE_PGU_XY(m->crtc_htotal, m->crtc_vtotal)); 163 164 arc_pgu_write(arcpgu, ARCPGU_REG_HSYNC, 165 ENCODE_PGU_XY(m->crtc_hsync_start - m->crtc_hdisplay, 166 m->crtc_hsync_end - m->crtc_hdisplay)); 167 168 arc_pgu_write(arcpgu, ARCPGU_REG_VSYNC, 169 ENCODE_PGU_XY(m->crtc_vsync_start - m->crtc_vdisplay, 170 m->crtc_vsync_end - m->crtc_vdisplay)); 171 172 arc_pgu_write(arcpgu, ARCPGU_REG_ACTIVE, 173 ENCODE_PGU_XY(m->crtc_hblank_end - m->crtc_hblank_start, 174 m->crtc_vblank_end - m->crtc_vblank_start)); 175 176 val = arc_pgu_read(arcpgu, ARCPGU_REG_CTRL); 177 178 if (m->flags & DRM_MODE_FLAG_PVSYNC) 179 val |= ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST; 180 else 181 val &= ~(ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST); 182 183 if (m->flags & DRM_MODE_FLAG_PHSYNC) 184 val |= ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST; 185 else 186 val &= ~(ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST); 187 188 arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, val); 189 arc_pgu_write(arcpgu, ARCPGU_REG_STRIDE, 0); 190 arc_pgu_write(arcpgu, ARCPGU_REG_START_SET, 1); 191 192 arc_pgu_set_pxl_fmt(arcpgu); 193 194 clk_set_rate(arcpgu->clk, m->crtc_clock * 1000); 195 } 196 197 static void arc_pgu_enable(struct drm_simple_display_pipe *pipe, 198 struct drm_crtc_state *crtc_state, 199 struct drm_plane_state *plane_state) 200 { 201 struct arcpgu_drm_private *arcpgu = pipe_to_arcpgu_priv(pipe); 202 203 arc_pgu_mode_set(arcpgu); 204 205 clk_prepare_enable(arcpgu->clk); 206 arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, 207 arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) | 208 ARCPGU_CTRL_ENABLE_MASK); 209 } 210 211 static void arc_pgu_disable(struct drm_simple_display_pipe *pipe) 212 { 213 struct arcpgu_drm_private *arcpgu = pipe_to_arcpgu_priv(pipe); 214 215 clk_disable_unprepare(arcpgu->clk); 216 arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, 217 arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) & 218 ~ARCPGU_CTRL_ENABLE_MASK); 219 } 220 221 static void arc_pgu_update(struct drm_simple_display_pipe *pipe, 222 struct drm_plane_state *state) 223 { 224 struct arcpgu_drm_private *arcpgu; 225 struct drm_gem_dma_object *gem; 226 227 if (!pipe->plane.state->fb) 228 return; 229 230 arcpgu = pipe_to_arcpgu_priv(pipe); 231 gem = drm_fb_dma_get_gem_obj(pipe->plane.state->fb, 0); 232 arc_pgu_write(arcpgu, ARCPGU_REG_BUF0_ADDR, gem->dma_addr); 233 } 234 235 static const struct drm_simple_display_pipe_funcs arc_pgu_pipe_funcs = { 236 .update = arc_pgu_update, 237 .mode_valid = arc_pgu_mode_valid, 238 .enable = arc_pgu_enable, 239 .disable = arc_pgu_disable, 240 }; 241 242 static const struct drm_mode_config_funcs arcpgu_drm_modecfg_funcs = { 243 .fb_create = drm_gem_fb_create, 244 .atomic_check = drm_atomic_helper_check, 245 .atomic_commit = drm_atomic_helper_commit, 246 }; 247 248 DEFINE_DRM_GEM_DMA_FOPS(arcpgu_drm_ops); 249 250 static int arcpgu_load(struct arcpgu_drm_private *arcpgu) 251 { 252 struct platform_device *pdev = to_platform_device(arcpgu->drm.dev); 253 struct device_node *encoder_node = NULL, *endpoint_node = NULL; 254 struct drm_connector *connector = NULL; 255 struct drm_device *drm = &arcpgu->drm; 256 int ret; 257 258 arcpgu->clk = devm_clk_get(drm->dev, "pxlclk"); 259 if (IS_ERR(arcpgu->clk)) 260 return PTR_ERR(arcpgu->clk); 261 262 ret = drmm_mode_config_init(drm); 263 if (ret) 264 return ret; 265 266 drm->mode_config.min_width = 0; 267 drm->mode_config.min_height = 0; 268 drm->mode_config.max_width = 1920; 269 drm->mode_config.max_height = 1080; 270 drm->mode_config.funcs = &arcpgu_drm_modecfg_funcs; 271 272 arcpgu->regs = devm_platform_ioremap_resource(pdev, 0); 273 if (IS_ERR(arcpgu->regs)) 274 return PTR_ERR(arcpgu->regs); 275 276 dev_info(drm->dev, "arc_pgu ID: 0x%x\n", 277 arc_pgu_read(arcpgu, ARCPGU_REG_ID)); 278 279 /* Get the optional framebuffer memory resource */ 280 ret = of_reserved_mem_device_init(drm->dev); 281 if (ret && ret != -ENODEV) 282 return ret; 283 284 if (dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32))) 285 return -ENODEV; 286 287 /* 288 * There is only one output port inside each device. It is linked with 289 * encoder endpoint. 290 */ 291 endpoint_node = of_graph_get_endpoint_by_regs(pdev->dev.of_node, 0, -1); 292 if (endpoint_node) { 293 encoder_node = of_graph_get_remote_port_parent(endpoint_node); 294 of_node_put(endpoint_node); 295 } else { 296 connector = &arcpgu->sim_conn; 297 dev_info(drm->dev, "no encoder found. Assumed virtual LCD on simulation platform\n"); 298 ret = arcpgu_drm_sim_init(drm, connector); 299 if (ret < 0) 300 return ret; 301 } 302 303 ret = drm_simple_display_pipe_init(drm, &arcpgu->pipe, &arc_pgu_pipe_funcs, 304 arc_pgu_supported_formats, 305 ARRAY_SIZE(arc_pgu_supported_formats), 306 NULL, connector); 307 if (ret) 308 return ret; 309 310 if (encoder_node) { 311 /* Locate drm bridge from the hdmi encoder DT node */ 312 struct drm_bridge *bridge __free(drm_bridge_put) = 313 of_drm_find_and_get_bridge(encoder_node); 314 if (!bridge) 315 return -EPROBE_DEFER; 316 317 ret = drm_simple_display_pipe_attach_bridge(&arcpgu->pipe, bridge); 318 if (ret) 319 return ret; 320 } 321 322 drm_mode_config_reset(drm); 323 drm_kms_helper_poll_init(drm); 324 325 platform_set_drvdata(pdev, drm); 326 return 0; 327 } 328 329 static int arcpgu_unload(struct drm_device *drm) 330 { 331 drm_kms_helper_poll_fini(drm); 332 drm_atomic_helper_shutdown(drm); 333 334 return 0; 335 } 336 337 #ifdef CONFIG_DEBUG_FS 338 static int arcpgu_show_pxlclock(struct seq_file *m, void *arg) 339 { 340 struct drm_info_node *node = (struct drm_info_node *)m->private; 341 struct drm_device *drm = node->minor->dev; 342 struct arcpgu_drm_private *arcpgu = dev_to_arcpgu(drm); 343 unsigned long clkrate = clk_get_rate(arcpgu->clk); 344 unsigned long mode_clock = arcpgu->pipe.crtc.mode.crtc_clock * 1000; 345 346 seq_printf(m, "hw : %lu\n", clkrate); 347 seq_printf(m, "mode: %lu\n", mode_clock); 348 return 0; 349 } 350 351 static struct drm_info_list arcpgu_debugfs_list[] = { 352 { "clocks", arcpgu_show_pxlclock, 0 }, 353 }; 354 355 static void arcpgu_debugfs_init(struct drm_minor *minor) 356 { 357 drm_debugfs_create_files(arcpgu_debugfs_list, 358 ARRAY_SIZE(arcpgu_debugfs_list), 359 minor->debugfs_root, minor); 360 } 361 #endif 362 363 static const struct drm_driver arcpgu_drm_driver = { 364 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, 365 .name = "arcpgu", 366 .desc = "ARC PGU Controller", 367 .major = 1, 368 .minor = 0, 369 .patchlevel = 0, 370 .fops = &arcpgu_drm_ops, 371 DRM_GEM_DMA_DRIVER_OPS, 372 DRM_FBDEV_DMA_DRIVER_OPS, 373 #ifdef CONFIG_DEBUG_FS 374 .debugfs_init = arcpgu_debugfs_init, 375 #endif 376 }; 377 378 static int arcpgu_probe(struct platform_device *pdev) 379 { 380 struct arcpgu_drm_private *arcpgu; 381 int ret; 382 383 arcpgu = devm_drm_dev_alloc(&pdev->dev, &arcpgu_drm_driver, 384 struct arcpgu_drm_private, drm); 385 if (IS_ERR(arcpgu)) 386 return PTR_ERR(arcpgu); 387 388 ret = arcpgu_load(arcpgu); 389 if (ret) 390 return ret; 391 392 ret = drm_dev_register(&arcpgu->drm, 0); 393 if (ret) 394 goto err_unload; 395 396 drm_client_setup_with_fourcc(&arcpgu->drm, DRM_FORMAT_RGB565); 397 398 return 0; 399 400 err_unload: 401 arcpgu_unload(&arcpgu->drm); 402 403 return ret; 404 } 405 406 static void arcpgu_remove(struct platform_device *pdev) 407 { 408 struct drm_device *drm = platform_get_drvdata(pdev); 409 410 drm_dev_unregister(drm); 411 arcpgu_unload(drm); 412 } 413 414 static const struct of_device_id arcpgu_of_table[] = { 415 {.compatible = "snps,arcpgu"}, 416 {} 417 }; 418 419 MODULE_DEVICE_TABLE(of, arcpgu_of_table); 420 421 static struct platform_driver arcpgu_platform_driver = { 422 .probe = arcpgu_probe, 423 .remove = arcpgu_remove, 424 .driver = { 425 .name = "arcpgu", 426 .of_match_table = arcpgu_of_table, 427 }, 428 }; 429 430 drm_module_platform_driver(arcpgu_platform_driver); 431 432 MODULE_AUTHOR("Carlos Palminha <palminha@synopsys.com>"); 433 MODULE_DESCRIPTION("ARC PGU DRM driver"); 434 MODULE_LICENSE("GPL"); 435