1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ARC PGU DRM driver. 4 * 5 * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com) 6 */ 7 8 #include <linux/clk.h> 9 10 #include <drm/clients/drm_client_setup.h> 11 #include <drm/drm_atomic.h> 12 #include <drm/drm_atomic_helper.h> 13 #include <drm/drm_debugfs.h> 14 #include <drm/drm_device.h> 15 #include <drm/drm_drv.h> 16 #include <drm/drm_edid.h> 17 #include <drm/drm_fb_dma_helper.h> 18 #include <drm/drm_fbdev_dma.h> 19 #include <drm/drm_fourcc.h> 20 #include <drm/drm_framebuffer.h> 21 #include <drm/drm_gem_atomic_helper.h> 22 #include <drm/drm_gem_dma_helper.h> 23 #include <drm/drm_gem_framebuffer_helper.h> 24 #include <drm/drm_module.h> 25 #include <drm/drm_of.h> 26 #include <drm/drm_plane.h> 27 #include <drm/drm_probe_helper.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/module.h> 30 #include <linux/of_reserved_mem.h> 31 #include <linux/platform_device.h> 32 33 #define ARCPGU_REG_CTRL 0x00 34 #define ARCPGU_REG_STAT 0x04 35 #define ARCPGU_REG_FMT 0x10 36 #define ARCPGU_REG_HSYNC 0x14 37 #define ARCPGU_REG_VSYNC 0x18 38 #define ARCPGU_REG_ACTIVE 0x1c 39 #define ARCPGU_REG_BUF0_ADDR 0x40 40 #define ARCPGU_REG_STRIDE 0x50 41 #define ARCPGU_REG_START_SET 0x84 42 43 #define ARCPGU_REG_ID 0x3FC 44 45 #define ARCPGU_CTRL_ENABLE_MASK 0x02 46 #define ARCPGU_CTRL_VS_POL_MASK 0x1 47 #define ARCPGU_CTRL_VS_POL_OFST 0x3 48 #define ARCPGU_CTRL_HS_POL_MASK 0x1 49 #define ARCPGU_CTRL_HS_POL_OFST 0x4 50 #define ARCPGU_MODE_XRGB8888 BIT(2) 51 #define ARCPGU_STAT_BUSY_MASK 0x02 52 53 struct arcpgu_drm_private { 54 struct drm_device drm; 55 void __iomem *regs; 56 struct clk *clk; 57 struct drm_plane plane; 58 struct drm_crtc crtc; 59 struct drm_encoder encoder; 60 struct drm_connector sim_conn; 61 }; 62 63 static inline struct arcpgu_drm_private *dev_to_arcpgu(struct drm_device *drm) 64 { 65 return container_of(drm, struct arcpgu_drm_private, drm); 66 } 67 68 static inline void arc_pgu_write(struct arcpgu_drm_private *arcpgu, 69 unsigned int reg, u32 value) 70 { 71 iowrite32(value, arcpgu->regs + reg); 72 } 73 74 static inline u32 arc_pgu_read(struct arcpgu_drm_private *arcpgu, 75 unsigned int reg) 76 { 77 return ioread32(arcpgu->regs + reg); 78 } 79 80 #define XRES_DEF 640 81 #define YRES_DEF 480 82 83 #define XRES_MAX 8192 84 #define YRES_MAX 8192 85 86 static int arcpgu_drm_connector_get_modes(struct drm_connector *connector) 87 { 88 int count; 89 90 count = drm_add_modes_noedid(connector, XRES_MAX, YRES_MAX); 91 drm_set_preferred_mode(connector, XRES_DEF, YRES_DEF); 92 return count; 93 } 94 95 static const struct drm_connector_helper_funcs 96 arcpgu_drm_connector_helper_funcs = { 97 .get_modes = arcpgu_drm_connector_get_modes, 98 }; 99 100 static const struct drm_connector_funcs arcpgu_drm_connector_funcs = { 101 .reset = drm_atomic_helper_connector_reset, 102 .fill_modes = drm_helper_probe_single_connector_modes, 103 .destroy = drm_connector_cleanup, 104 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 105 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 106 }; 107 108 static int arcpgu_drm_sim_init(struct drm_device *drm, struct drm_connector *connector) 109 { 110 drm_connector_helper_add(connector, &arcpgu_drm_connector_helper_funcs); 111 return drm_connector_init(drm, connector, &arcpgu_drm_connector_funcs, 112 DRM_MODE_CONNECTOR_VIRTUAL); 113 } 114 115 #define ENCODE_PGU_XY(x, y) ((((x) - 1) << 16) | ((y) - 1)) 116 117 static const u32 arc_pgu_supported_formats[] = { 118 DRM_FORMAT_RGB565, 119 DRM_FORMAT_XRGB8888, 120 DRM_FORMAT_ARGB8888, 121 }; 122 123 static void arc_pgu_set_pxl_fmt(struct arcpgu_drm_private *arcpgu, 124 const struct drm_plane_state *plane_state) 125 { 126 const struct drm_framebuffer *fb = plane_state->fb; 127 uint32_t pixel_format = fb->format->format; 128 u32 format = DRM_FORMAT_INVALID; 129 int i; 130 u32 reg_ctrl; 131 132 for (i = 0; i < ARRAY_SIZE(arc_pgu_supported_formats); i++) { 133 if (arc_pgu_supported_formats[i] == pixel_format) 134 format = arc_pgu_supported_formats[i]; 135 } 136 137 if (WARN_ON(format == DRM_FORMAT_INVALID)) 138 return; 139 140 reg_ctrl = arc_pgu_read(arcpgu, ARCPGU_REG_CTRL); 141 if (format == DRM_FORMAT_RGB565) 142 reg_ctrl &= ~ARCPGU_MODE_XRGB8888; 143 else 144 reg_ctrl |= ARCPGU_MODE_XRGB8888; 145 arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, reg_ctrl); 146 } 147 148 static enum drm_mode_status arcpgu_crtc_helper_mode_valid(struct drm_crtc *crtc, 149 const struct drm_display_mode *mode) 150 { 151 struct arcpgu_drm_private *arcpgu = dev_to_arcpgu(crtc->dev); 152 long rate, clk_rate = mode->clock * 1000; 153 long diff = clk_rate / 200; /* +-0.5% allowed by HDMI spec */ 154 155 rate = clk_round_rate(arcpgu->clk, clk_rate); 156 if ((max(rate, clk_rate) - min(rate, clk_rate) < diff) && (rate > 0)) 157 return MODE_OK; 158 159 return MODE_NOCLOCK; 160 } 161 162 static void arc_pgu_mode_set(struct arcpgu_drm_private *arcpgu, 163 struct drm_crtc_state *crtc_state, 164 struct drm_plane_state *plane_state) 165 { 166 struct drm_display_mode *m = &crtc_state->adjusted_mode; 167 u32 val; 168 169 arc_pgu_write(arcpgu, ARCPGU_REG_FMT, 170 ENCODE_PGU_XY(m->crtc_htotal, m->crtc_vtotal)); 171 172 arc_pgu_write(arcpgu, ARCPGU_REG_HSYNC, 173 ENCODE_PGU_XY(m->crtc_hsync_start - m->crtc_hdisplay, 174 m->crtc_hsync_end - m->crtc_hdisplay)); 175 176 arc_pgu_write(arcpgu, ARCPGU_REG_VSYNC, 177 ENCODE_PGU_XY(m->crtc_vsync_start - m->crtc_vdisplay, 178 m->crtc_vsync_end - m->crtc_vdisplay)); 179 180 arc_pgu_write(arcpgu, ARCPGU_REG_ACTIVE, 181 ENCODE_PGU_XY(m->crtc_hblank_end - m->crtc_hblank_start, 182 m->crtc_vblank_end - m->crtc_vblank_start)); 183 184 val = arc_pgu_read(arcpgu, ARCPGU_REG_CTRL); 185 186 if (m->flags & DRM_MODE_FLAG_PVSYNC) 187 val |= ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST; 188 else 189 val &= ~(ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST); 190 191 if (m->flags & DRM_MODE_FLAG_PHSYNC) 192 val |= ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST; 193 else 194 val &= ~(ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST); 195 196 arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, val); 197 arc_pgu_write(arcpgu, ARCPGU_REG_STRIDE, 0); 198 arc_pgu_write(arcpgu, ARCPGU_REG_START_SET, 1); 199 200 arc_pgu_set_pxl_fmt(arcpgu, plane_state); 201 202 clk_set_rate(arcpgu->clk, m->crtc_clock * 1000); 203 } 204 205 static void arcpgu_crtc_helper_atomic_enable(struct drm_crtc *crtc, 206 struct drm_atomic_commit *commit) 207 { 208 struct arcpgu_drm_private *arcpgu = dev_to_arcpgu(crtc->dev); 209 struct drm_plane_state *pstate = drm_atomic_get_new_plane_state(commit, &arcpgu->plane); 210 struct drm_crtc_state *cstate = drm_atomic_get_new_crtc_state(commit, crtc); 211 212 arc_pgu_mode_set(arcpgu, cstate, pstate); 213 214 clk_prepare_enable(arcpgu->clk); 215 arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, 216 arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) | 217 ARCPGU_CTRL_ENABLE_MASK); 218 } 219 220 static void arcpgu_crtc_helper_atomic_disable(struct drm_crtc *crtc, 221 struct drm_atomic_commit *commit) 222 { 223 struct arcpgu_drm_private *arcpgu = dev_to_arcpgu(crtc->dev); 224 225 clk_disable_unprepare(arcpgu->clk); 226 arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, 227 arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) & 228 ~ARCPGU_CTRL_ENABLE_MASK); 229 } 230 231 static void arcpgu_plane_helper_atomic_update(struct drm_plane *plane, 232 struct drm_atomic_commit *commit) 233 { 234 struct drm_plane_state *pstate = drm_atomic_get_new_plane_state(commit, plane); 235 struct arcpgu_drm_private *arcpgu; 236 struct drm_gem_dma_object *gem; 237 238 if (!pstate->fb) 239 return; 240 241 arcpgu = dev_to_arcpgu(plane->dev); 242 gem = drm_fb_dma_get_gem_obj(pstate->fb, 0); 243 arc_pgu_write(arcpgu, ARCPGU_REG_BUF0_ADDR, gem->dma_addr); 244 } 245 246 static const struct drm_mode_config_funcs arcpgu_drm_modecfg_funcs = { 247 .fb_create = drm_gem_fb_create, 248 .atomic_check = drm_atomic_helper_check, 249 .atomic_commit = drm_atomic_helper_commit, 250 }; 251 252 DEFINE_DRM_GEM_DMA_FOPS(arcpgu_drm_ops); 253 254 static int arcpgu_plane_helper_atomic_check(struct drm_plane *plane, 255 struct drm_atomic_commit *commit) 256 { 257 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(commit, plane); 258 struct drm_crtc_state *crtc_state = NULL; 259 260 if (plane_state->crtc) { 261 crtc_state = drm_atomic_get_crtc_state(commit, plane_state->crtc); 262 if (IS_ERR(crtc_state)) 263 return PTR_ERR(crtc_state); 264 } 265 266 return drm_atomic_helper_check_plane_state(plane_state, crtc_state, 267 DRM_PLANE_NO_SCALING, 268 DRM_PLANE_NO_SCALING, 269 false, false); 270 } 271 272 static const struct drm_plane_helper_funcs arcpgu_plane_helper_funcs = { 273 .prepare_fb = drm_gem_plane_helper_prepare_fb, 274 .atomic_check = arcpgu_plane_helper_atomic_check, 275 .atomic_update = arcpgu_plane_helper_atomic_update, 276 }; 277 278 static const struct drm_plane_funcs arcpgu_plane_funcs = { 279 .update_plane = drm_atomic_helper_update_plane, 280 .disable_plane = drm_atomic_helper_disable_plane, 281 .destroy = drm_plane_cleanup, 282 .atomic_create_state = drm_atomic_helper_plane_create_state, 283 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 284 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 285 }; 286 287 static int arcpgu_crtc_helper_atomic_check(struct drm_crtc *crtc, 288 struct drm_atomic_commit *commit) 289 { 290 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(commit, crtc); 291 int ret; 292 293 if (crtc_state->enable) { 294 ret = drm_atomic_helper_check_crtc_primary_plane(crtc_state); 295 if (ret) 296 return ret; 297 } 298 299 return drm_atomic_add_affected_planes(commit, crtc); 300 } 301 302 static const struct drm_crtc_helper_funcs arcpgu_crtc_helper_funcs = { 303 .mode_valid = arcpgu_crtc_helper_mode_valid, 304 .atomic_check = arcpgu_crtc_helper_atomic_check, 305 .atomic_enable = arcpgu_crtc_helper_atomic_enable, 306 .atomic_disable = arcpgu_crtc_helper_atomic_disable, 307 }; 308 309 static const struct drm_crtc_funcs arcpgu_crtc_funcs = { 310 .atomic_create_state = drm_atomic_helper_crtc_create_state, 311 .destroy = drm_crtc_cleanup, 312 .set_config = drm_atomic_helper_set_config, 313 .page_flip = drm_atomic_helper_page_flip, 314 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 315 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 316 }; 317 318 static const struct drm_encoder_funcs arcpgu_encoder_funcs = { 319 .destroy = drm_encoder_cleanup, 320 }; 321 322 static int arcpgu_load(struct arcpgu_drm_private *arcpgu) 323 { 324 struct platform_device *pdev = to_platform_device(arcpgu->drm.dev); 325 struct device_node *encoder_node __free(device_node) = NULL; 326 struct device_node *endpoint_node = NULL; 327 struct drm_connector *connector = NULL; 328 struct drm_device *drm = &arcpgu->drm; 329 struct drm_plane *plane; 330 struct drm_encoder *encoder; 331 struct drm_crtc *crtc; 332 int ret; 333 334 arcpgu->clk = devm_clk_get(drm->dev, "pxlclk"); 335 if (IS_ERR(arcpgu->clk)) 336 return PTR_ERR(arcpgu->clk); 337 338 ret = drmm_mode_config_init(drm); 339 if (ret) 340 return ret; 341 342 drm->mode_config.min_width = 0; 343 drm->mode_config.min_height = 0; 344 drm->mode_config.max_width = 1920; 345 drm->mode_config.max_height = 1080; 346 drm->mode_config.funcs = &arcpgu_drm_modecfg_funcs; 347 348 arcpgu->regs = devm_platform_ioremap_resource(pdev, 0); 349 if (IS_ERR(arcpgu->regs)) 350 return PTR_ERR(arcpgu->regs); 351 352 dev_info(drm->dev, "arc_pgu ID: 0x%x\n", 353 arc_pgu_read(arcpgu, ARCPGU_REG_ID)); 354 355 /* Get the optional framebuffer memory resource */ 356 ret = of_reserved_mem_device_init(drm->dev); 357 if (ret && ret != -ENODEV) 358 return ret; 359 360 if (dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32))) 361 return -ENODEV; 362 363 plane = &arcpgu->plane; 364 ret = drm_universal_plane_init(drm, plane, 0, 365 &arcpgu_plane_funcs, 366 arc_pgu_supported_formats, 367 ARRAY_SIZE(arc_pgu_supported_formats), 368 NULL, 369 DRM_PLANE_TYPE_PRIMARY, NULL); 370 if (ret) 371 return ret; 372 drm_plane_helper_add(plane, &arcpgu_plane_helper_funcs); 373 374 crtc = &arcpgu->crtc; 375 ret = drm_crtc_init_with_planes(drm, crtc, plane, NULL, 376 &arcpgu_crtc_funcs, NULL); 377 if (ret) 378 return ret; 379 drm_crtc_helper_add(crtc, &arcpgu_crtc_helper_funcs); 380 381 encoder = &arcpgu->encoder; 382 ret = drm_encoder_init(drm, encoder, &arcpgu_encoder_funcs, DRM_MODE_ENCODER_NONE, NULL); 383 if (ret) 384 return ret; 385 encoder->possible_crtcs = drm_crtc_mask(crtc); 386 387 /* 388 * There is only one output port inside each device. It is linked with 389 * encoder endpoint. 390 */ 391 endpoint_node = of_graph_get_endpoint_by_regs(pdev->dev.of_node, 0, -1); 392 if (endpoint_node) { 393 encoder_node = of_graph_get_remote_port_parent(endpoint_node); 394 of_node_put(endpoint_node); 395 if (!encoder_node) 396 return -ENODEV; 397 398 /* Locate drm bridge from the hdmi encoder DT node */ 399 struct drm_bridge *bridge __free(drm_bridge_put) = 400 of_drm_find_and_get_bridge(encoder_node); 401 if (!bridge) 402 return -EPROBE_DEFER; 403 404 ret = drm_bridge_attach(encoder, bridge, NULL, 0); 405 if (ret) 406 return ret; 407 } else { 408 connector = &arcpgu->sim_conn; 409 dev_info(drm->dev, "no encoder found. Assumed virtual LCD on simulation platform\n"); 410 ret = arcpgu_drm_sim_init(drm, connector); 411 if (ret < 0) 412 return ret; 413 414 ret = drm_connector_attach_encoder(connector, encoder); 415 if (ret) 416 return ret; 417 } 418 419 drm_mode_config_reset(drm); 420 drm_kms_helper_poll_init(drm); 421 422 platform_set_drvdata(pdev, drm); 423 return 0; 424 } 425 426 static int arcpgu_unload(struct drm_device *drm) 427 { 428 drm_kms_helper_poll_fini(drm); 429 drm_atomic_helper_shutdown(drm); 430 431 return 0; 432 } 433 434 #ifdef CONFIG_DEBUG_FS 435 static int arcpgu_show_pxlclock(struct seq_file *m, void *arg) 436 { 437 struct drm_info_node *node = (struct drm_info_node *)m->private; 438 struct drm_device *drm = node->minor->dev; 439 struct arcpgu_drm_private *arcpgu = dev_to_arcpgu(drm); 440 unsigned long clkrate = clk_get_rate(arcpgu->clk); 441 unsigned long mode_clock; 442 int ret; 443 444 ret = drm_modeset_lock_single_interruptible(&arcpgu->crtc.mutex); 445 if (ret) 446 return ret; 447 mode_clock = arcpgu->crtc.state->mode.crtc_clock * 1000; 448 drm_modeset_unlock(&arcpgu->crtc.mutex); 449 450 seq_printf(m, "hw : %lu\n", clkrate); 451 seq_printf(m, "mode: %lu\n", mode_clock); 452 return 0; 453 } 454 455 static struct drm_info_list arcpgu_debugfs_list[] = { 456 { "clocks", arcpgu_show_pxlclock, 0 }, 457 }; 458 459 static void arcpgu_debugfs_init(struct drm_minor *minor) 460 { 461 drm_debugfs_create_files(arcpgu_debugfs_list, 462 ARRAY_SIZE(arcpgu_debugfs_list), 463 minor->debugfs_root, minor); 464 } 465 #endif 466 467 static const struct drm_driver arcpgu_drm_driver = { 468 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, 469 .name = "arcpgu", 470 .desc = "ARC PGU Controller", 471 .major = 1, 472 .minor = 0, 473 .patchlevel = 0, 474 .fops = &arcpgu_drm_ops, 475 DRM_GEM_DMA_DRIVER_OPS, 476 DRM_FBDEV_DMA_DRIVER_OPS, 477 #ifdef CONFIG_DEBUG_FS 478 .debugfs_init = arcpgu_debugfs_init, 479 #endif 480 }; 481 482 static int arcpgu_probe(struct platform_device *pdev) 483 { 484 struct arcpgu_drm_private *arcpgu; 485 int ret; 486 487 arcpgu = devm_drm_dev_alloc(&pdev->dev, &arcpgu_drm_driver, 488 struct arcpgu_drm_private, drm); 489 if (IS_ERR(arcpgu)) 490 return PTR_ERR(arcpgu); 491 492 ret = arcpgu_load(arcpgu); 493 if (ret) 494 return ret; 495 496 ret = drm_dev_register(&arcpgu->drm, 0); 497 if (ret) 498 goto err_unload; 499 500 drm_client_setup_with_fourcc(&arcpgu->drm, DRM_FORMAT_RGB565); 501 502 return 0; 503 504 err_unload: 505 arcpgu_unload(&arcpgu->drm); 506 507 return ret; 508 } 509 510 static void arcpgu_remove(struct platform_device *pdev) 511 { 512 struct drm_device *drm = platform_get_drvdata(pdev); 513 514 drm_dev_unregister(drm); 515 arcpgu_unload(drm); 516 } 517 518 static const struct of_device_id arcpgu_of_table[] = { 519 {.compatible = "snps,arcpgu"}, 520 {} 521 }; 522 523 MODULE_DEVICE_TABLE(of, arcpgu_of_table); 524 525 static struct platform_driver arcpgu_platform_driver = { 526 .probe = arcpgu_probe, 527 .remove = arcpgu_remove, 528 .driver = { 529 .name = "arcpgu", 530 .of_match_table = arcpgu_of_table, 531 }, 532 }; 533 534 drm_module_platform_driver(arcpgu_platform_driver); 535 536 MODULE_AUTHOR("Carlos Palminha <palminha@synopsys.com>"); 537 MODULE_DESCRIPTION("ARC PGU DRM driver"); 538 MODULE_LICENSE("GPL"); 539