1 /* 2 * Copyright (C) 2012 Texas Instruments 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 /* LCDC DRM driver, based on da8xx-fb */ 19 20 #include "tilcdc_drv.h" 21 #include "tilcdc_regs.h" 22 #include "tilcdc_tfp410.h" 23 #include "tilcdc_slave.h" 24 #include "tilcdc_panel.h" 25 26 #include "drm_fb_helper.h" 27 28 static LIST_HEAD(module_list); 29 static bool slave_probing; 30 31 void tilcdc_module_init(struct tilcdc_module *mod, const char *name, 32 const struct tilcdc_module_ops *funcs) 33 { 34 mod->name = name; 35 mod->funcs = funcs; 36 INIT_LIST_HEAD(&mod->list); 37 list_add(&mod->list, &module_list); 38 } 39 40 void tilcdc_module_cleanup(struct tilcdc_module *mod) 41 { 42 list_del(&mod->list); 43 } 44 45 void tilcdc_slave_probedefer(bool defered) 46 { 47 slave_probing = defered; 48 } 49 50 static struct of_device_id tilcdc_of_match[]; 51 52 static struct drm_framebuffer *tilcdc_fb_create(struct drm_device *dev, 53 struct drm_file *file_priv, struct drm_mode_fb_cmd2 *mode_cmd) 54 { 55 return drm_fb_cma_create(dev, file_priv, mode_cmd); 56 } 57 58 static void tilcdc_fb_output_poll_changed(struct drm_device *dev) 59 { 60 struct tilcdc_drm_private *priv = dev->dev_private; 61 if (priv->fbdev) 62 drm_fbdev_cma_hotplug_event(priv->fbdev); 63 } 64 65 static const struct drm_mode_config_funcs mode_config_funcs = { 66 .fb_create = tilcdc_fb_create, 67 .output_poll_changed = tilcdc_fb_output_poll_changed, 68 }; 69 70 static int modeset_init(struct drm_device *dev) 71 { 72 struct tilcdc_drm_private *priv = dev->dev_private; 73 struct tilcdc_module *mod; 74 75 drm_mode_config_init(dev); 76 77 priv->crtc = tilcdc_crtc_create(dev); 78 79 list_for_each_entry(mod, &module_list, list) { 80 DBG("loading module: %s", mod->name); 81 mod->funcs->modeset_init(mod, dev); 82 } 83 84 if ((priv->num_encoders == 0) || (priv->num_connectors == 0)) { 85 /* oh nos! */ 86 dev_err(dev->dev, "no encoders/connectors found\n"); 87 return -ENXIO; 88 } 89 90 dev->mode_config.min_width = 0; 91 dev->mode_config.min_height = 0; 92 dev->mode_config.max_width = tilcdc_crtc_max_width(priv->crtc); 93 dev->mode_config.max_height = 2048; 94 dev->mode_config.funcs = &mode_config_funcs; 95 96 return 0; 97 } 98 99 #ifdef CONFIG_CPU_FREQ 100 static int cpufreq_transition(struct notifier_block *nb, 101 unsigned long val, void *data) 102 { 103 struct tilcdc_drm_private *priv = container_of(nb, 104 struct tilcdc_drm_private, freq_transition); 105 if (val == CPUFREQ_POSTCHANGE) { 106 if (priv->lcd_fck_rate != clk_get_rate(priv->clk)) { 107 priv->lcd_fck_rate = clk_get_rate(priv->clk); 108 tilcdc_crtc_update_clk(priv->crtc); 109 } 110 } 111 112 return 0; 113 } 114 #endif 115 116 /* 117 * DRM operations: 118 */ 119 120 static int tilcdc_unload(struct drm_device *dev) 121 { 122 struct tilcdc_drm_private *priv = dev->dev_private; 123 124 drm_fbdev_cma_fini(priv->fbdev); 125 drm_kms_helper_poll_fini(dev); 126 drm_mode_config_cleanup(dev); 127 drm_vblank_cleanup(dev); 128 129 pm_runtime_get_sync(dev->dev); 130 drm_irq_uninstall(dev); 131 pm_runtime_put_sync(dev->dev); 132 133 #ifdef CONFIG_CPU_FREQ 134 cpufreq_unregister_notifier(&priv->freq_transition, 135 CPUFREQ_TRANSITION_NOTIFIER); 136 #endif 137 138 if (priv->clk) 139 clk_put(priv->clk); 140 141 if (priv->mmio) 142 iounmap(priv->mmio); 143 144 flush_workqueue(priv->wq); 145 destroy_workqueue(priv->wq); 146 147 dev->dev_private = NULL; 148 149 pm_runtime_disable(dev->dev); 150 151 kfree(priv); 152 153 return 0; 154 } 155 156 static int tilcdc_load(struct drm_device *dev, unsigned long flags) 157 { 158 struct platform_device *pdev = dev->platformdev; 159 struct device_node *node = pdev->dev.of_node; 160 struct tilcdc_drm_private *priv; 161 struct tilcdc_module *mod; 162 struct resource *res; 163 u32 bpp = 0; 164 int ret; 165 166 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 167 if (!priv) { 168 dev_err(dev->dev, "failed to allocate private data\n"); 169 return -ENOMEM; 170 } 171 172 dev->dev_private = priv; 173 174 priv->wq = alloc_ordered_workqueue("tilcdc", 0); 175 176 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 177 if (!res) { 178 dev_err(dev->dev, "failed to get memory resource\n"); 179 ret = -EINVAL; 180 goto fail; 181 } 182 183 priv->mmio = ioremap_nocache(res->start, resource_size(res)); 184 if (!priv->mmio) { 185 dev_err(dev->dev, "failed to ioremap\n"); 186 ret = -ENOMEM; 187 goto fail; 188 } 189 190 priv->clk = clk_get(dev->dev, "fck"); 191 if (IS_ERR(priv->clk)) { 192 dev_err(dev->dev, "failed to get functional clock\n"); 193 ret = -ENODEV; 194 goto fail; 195 } 196 197 priv->disp_clk = clk_get(dev->dev, "dpll_disp_ck"); 198 if (IS_ERR(priv->clk)) { 199 dev_err(dev->dev, "failed to get display clock\n"); 200 ret = -ENODEV; 201 goto fail; 202 } 203 204 #ifdef CONFIG_CPU_FREQ 205 priv->lcd_fck_rate = clk_get_rate(priv->clk); 206 priv->freq_transition.notifier_call = cpufreq_transition; 207 ret = cpufreq_register_notifier(&priv->freq_transition, 208 CPUFREQ_TRANSITION_NOTIFIER); 209 if (ret) { 210 dev_err(dev->dev, "failed to register cpufreq notifier\n"); 211 goto fail; 212 } 213 #endif 214 215 if (of_property_read_u32(node, "max-bandwidth", &priv->max_bandwidth)) 216 priv->max_bandwidth = TILCDC_DEFAULT_MAX_BANDWIDTH; 217 218 DBG("Maximum Bandwidth Value %d", priv->max_bandwidth); 219 220 if (of_property_read_u32(node, "ti,max-width", &priv->max_width)) 221 priv->max_width = TILCDC_DEFAULT_MAX_WIDTH; 222 223 DBG("Maximum Horizontal Pixel Width Value %dpixels", priv->max_width); 224 225 if (of_property_read_u32(node, "ti,max-pixelclock", 226 &priv->max_pixelclock)) 227 priv->max_pixelclock = TILCDC_DEFAULT_MAX_PIXELCLOCK; 228 229 DBG("Maximum Pixel Clock Value %dKHz", priv->max_pixelclock); 230 231 pm_runtime_enable(dev->dev); 232 233 /* Determine LCD IP Version */ 234 pm_runtime_get_sync(dev->dev); 235 switch (tilcdc_read(dev, LCDC_PID_REG)) { 236 case 0x4c100102: 237 priv->rev = 1; 238 break; 239 case 0x4f200800: 240 case 0x4f201000: 241 priv->rev = 2; 242 break; 243 default: 244 dev_warn(dev->dev, "Unknown PID Reg value 0x%08x, " 245 "defaulting to LCD revision 1\n", 246 tilcdc_read(dev, LCDC_PID_REG)); 247 priv->rev = 1; 248 break; 249 } 250 251 pm_runtime_put_sync(dev->dev); 252 253 ret = modeset_init(dev); 254 if (ret < 0) { 255 dev_err(dev->dev, "failed to initialize mode setting\n"); 256 goto fail; 257 } 258 259 ret = drm_vblank_init(dev, 1); 260 if (ret < 0) { 261 dev_err(dev->dev, "failed to initialize vblank\n"); 262 goto fail; 263 } 264 265 pm_runtime_get_sync(dev->dev); 266 ret = drm_irq_install(dev, platform_get_irq(dev->platformdev, 0)); 267 pm_runtime_put_sync(dev->dev); 268 if (ret < 0) { 269 dev_err(dev->dev, "failed to install IRQ handler\n"); 270 goto fail; 271 } 272 273 platform_set_drvdata(pdev, dev); 274 275 276 list_for_each_entry(mod, &module_list, list) { 277 DBG("%s: preferred_bpp: %d", mod->name, mod->preferred_bpp); 278 bpp = mod->preferred_bpp; 279 if (bpp > 0) 280 break; 281 } 282 283 priv->fbdev = drm_fbdev_cma_init(dev, bpp, 284 dev->mode_config.num_crtc, 285 dev->mode_config.num_connector); 286 287 drm_kms_helper_poll_init(dev); 288 289 return 0; 290 291 fail: 292 tilcdc_unload(dev); 293 return ret; 294 } 295 296 static void tilcdc_preclose(struct drm_device *dev, struct drm_file *file) 297 { 298 struct tilcdc_drm_private *priv = dev->dev_private; 299 300 tilcdc_crtc_cancel_page_flip(priv->crtc, file); 301 } 302 303 static void tilcdc_lastclose(struct drm_device *dev) 304 { 305 struct tilcdc_drm_private *priv = dev->dev_private; 306 drm_fbdev_cma_restore_mode(priv->fbdev); 307 } 308 309 static irqreturn_t tilcdc_irq(int irq, void *arg) 310 { 311 struct drm_device *dev = arg; 312 struct tilcdc_drm_private *priv = dev->dev_private; 313 return tilcdc_crtc_irq(priv->crtc); 314 } 315 316 static void tilcdc_irq_preinstall(struct drm_device *dev) 317 { 318 tilcdc_clear_irqstatus(dev, 0xffffffff); 319 } 320 321 static int tilcdc_irq_postinstall(struct drm_device *dev) 322 { 323 struct tilcdc_drm_private *priv = dev->dev_private; 324 325 /* enable FIFO underflow irq: */ 326 if (priv->rev == 1) 327 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_UNDERFLOW_INT_ENA); 328 else 329 tilcdc_set(dev, LCDC_INT_ENABLE_SET_REG, LCDC_V2_UNDERFLOW_INT_ENA); 330 331 return 0; 332 } 333 334 static void tilcdc_irq_uninstall(struct drm_device *dev) 335 { 336 struct tilcdc_drm_private *priv = dev->dev_private; 337 338 /* disable irqs that we might have enabled: */ 339 if (priv->rev == 1) { 340 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, 341 LCDC_V1_UNDERFLOW_INT_ENA | LCDC_V1_PL_INT_ENA); 342 tilcdc_clear(dev, LCDC_DMA_CTRL_REG, LCDC_V1_END_OF_FRAME_INT_ENA); 343 } else { 344 tilcdc_clear(dev, LCDC_INT_ENABLE_SET_REG, 345 LCDC_V2_UNDERFLOW_INT_ENA | LCDC_V2_PL_INT_ENA | 346 LCDC_V2_END_OF_FRAME0_INT_ENA | LCDC_V2_END_OF_FRAME1_INT_ENA | 347 LCDC_FRAME_DONE); 348 } 349 350 } 351 352 static void enable_vblank(struct drm_device *dev, bool enable) 353 { 354 struct tilcdc_drm_private *priv = dev->dev_private; 355 u32 reg, mask; 356 357 if (priv->rev == 1) { 358 reg = LCDC_DMA_CTRL_REG; 359 mask = LCDC_V1_END_OF_FRAME_INT_ENA; 360 } else { 361 reg = LCDC_INT_ENABLE_SET_REG; 362 mask = LCDC_V2_END_OF_FRAME0_INT_ENA | 363 LCDC_V2_END_OF_FRAME1_INT_ENA | LCDC_FRAME_DONE; 364 } 365 366 if (enable) 367 tilcdc_set(dev, reg, mask); 368 else 369 tilcdc_clear(dev, reg, mask); 370 } 371 372 static int tilcdc_enable_vblank(struct drm_device *dev, int crtc) 373 { 374 enable_vblank(dev, true); 375 return 0; 376 } 377 378 static void tilcdc_disable_vblank(struct drm_device *dev, int crtc) 379 { 380 enable_vblank(dev, false); 381 } 382 383 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_PM_SLEEP) 384 static const struct { 385 const char *name; 386 uint8_t rev; 387 uint8_t save; 388 uint32_t reg; 389 } registers[] = { 390 #define REG(rev, save, reg) { #reg, rev, save, reg } 391 /* exists in revision 1: */ 392 REG(1, false, LCDC_PID_REG), 393 REG(1, true, LCDC_CTRL_REG), 394 REG(1, false, LCDC_STAT_REG), 395 REG(1, true, LCDC_RASTER_CTRL_REG), 396 REG(1, true, LCDC_RASTER_TIMING_0_REG), 397 REG(1, true, LCDC_RASTER_TIMING_1_REG), 398 REG(1, true, LCDC_RASTER_TIMING_2_REG), 399 REG(1, true, LCDC_DMA_CTRL_REG), 400 REG(1, true, LCDC_DMA_FB_BASE_ADDR_0_REG), 401 REG(1, true, LCDC_DMA_FB_CEILING_ADDR_0_REG), 402 REG(1, true, LCDC_DMA_FB_BASE_ADDR_1_REG), 403 REG(1, true, LCDC_DMA_FB_CEILING_ADDR_1_REG), 404 /* new in revision 2: */ 405 REG(2, false, LCDC_RAW_STAT_REG), 406 REG(2, false, LCDC_MASKED_STAT_REG), 407 REG(2, false, LCDC_INT_ENABLE_SET_REG), 408 REG(2, false, LCDC_INT_ENABLE_CLR_REG), 409 REG(2, false, LCDC_END_OF_INT_IND_REG), 410 REG(2, true, LCDC_CLK_ENABLE_REG), 411 REG(2, true, LCDC_INT_ENABLE_SET_REG), 412 #undef REG 413 }; 414 #endif 415 416 #ifdef CONFIG_DEBUG_FS 417 static int tilcdc_regs_show(struct seq_file *m, void *arg) 418 { 419 struct drm_info_node *node = (struct drm_info_node *) m->private; 420 struct drm_device *dev = node->minor->dev; 421 struct tilcdc_drm_private *priv = dev->dev_private; 422 unsigned i; 423 424 pm_runtime_get_sync(dev->dev); 425 426 seq_printf(m, "revision: %d\n", priv->rev); 427 428 for (i = 0; i < ARRAY_SIZE(registers); i++) 429 if (priv->rev >= registers[i].rev) 430 seq_printf(m, "%s:\t %08x\n", registers[i].name, 431 tilcdc_read(dev, registers[i].reg)); 432 433 pm_runtime_put_sync(dev->dev); 434 435 return 0; 436 } 437 438 static int tilcdc_mm_show(struct seq_file *m, void *arg) 439 { 440 struct drm_info_node *node = (struct drm_info_node *) m->private; 441 struct drm_device *dev = node->minor->dev; 442 return drm_mm_dump_table(m, &dev->vma_offset_manager->vm_addr_space_mm); 443 } 444 445 static struct drm_info_list tilcdc_debugfs_list[] = { 446 { "regs", tilcdc_regs_show, 0 }, 447 { "mm", tilcdc_mm_show, 0 }, 448 { "fb", drm_fb_cma_debugfs_show, 0 }, 449 }; 450 451 static int tilcdc_debugfs_init(struct drm_minor *minor) 452 { 453 struct drm_device *dev = minor->dev; 454 struct tilcdc_module *mod; 455 int ret; 456 457 ret = drm_debugfs_create_files(tilcdc_debugfs_list, 458 ARRAY_SIZE(tilcdc_debugfs_list), 459 minor->debugfs_root, minor); 460 461 list_for_each_entry(mod, &module_list, list) 462 if (mod->funcs->debugfs_init) 463 mod->funcs->debugfs_init(mod, minor); 464 465 if (ret) { 466 dev_err(dev->dev, "could not install tilcdc_debugfs_list\n"); 467 return ret; 468 } 469 470 return ret; 471 } 472 473 static void tilcdc_debugfs_cleanup(struct drm_minor *minor) 474 { 475 struct tilcdc_module *mod; 476 drm_debugfs_remove_files(tilcdc_debugfs_list, 477 ARRAY_SIZE(tilcdc_debugfs_list), minor); 478 479 list_for_each_entry(mod, &module_list, list) 480 if (mod->funcs->debugfs_cleanup) 481 mod->funcs->debugfs_cleanup(mod, minor); 482 } 483 #endif 484 485 static const struct file_operations fops = { 486 .owner = THIS_MODULE, 487 .open = drm_open, 488 .release = drm_release, 489 .unlocked_ioctl = drm_ioctl, 490 #ifdef CONFIG_COMPAT 491 .compat_ioctl = drm_compat_ioctl, 492 #endif 493 .poll = drm_poll, 494 .read = drm_read, 495 .llseek = no_llseek, 496 .mmap = drm_gem_cma_mmap, 497 }; 498 499 static struct drm_driver tilcdc_driver = { 500 .driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM | DRIVER_MODESET, 501 .load = tilcdc_load, 502 .unload = tilcdc_unload, 503 .preclose = tilcdc_preclose, 504 .lastclose = tilcdc_lastclose, 505 .irq_handler = tilcdc_irq, 506 .irq_preinstall = tilcdc_irq_preinstall, 507 .irq_postinstall = tilcdc_irq_postinstall, 508 .irq_uninstall = tilcdc_irq_uninstall, 509 .get_vblank_counter = drm_vblank_count, 510 .enable_vblank = tilcdc_enable_vblank, 511 .disable_vblank = tilcdc_disable_vblank, 512 .gem_free_object = drm_gem_cma_free_object, 513 .gem_vm_ops = &drm_gem_cma_vm_ops, 514 .dumb_create = drm_gem_cma_dumb_create, 515 .dumb_map_offset = drm_gem_cma_dumb_map_offset, 516 .dumb_destroy = drm_gem_dumb_destroy, 517 #ifdef CONFIG_DEBUG_FS 518 .debugfs_init = tilcdc_debugfs_init, 519 .debugfs_cleanup = tilcdc_debugfs_cleanup, 520 #endif 521 .fops = &fops, 522 .name = "tilcdc", 523 .desc = "TI LCD Controller DRM", 524 .date = "20121205", 525 .major = 1, 526 .minor = 0, 527 }; 528 529 /* 530 * Power management: 531 */ 532 533 #ifdef CONFIG_PM_SLEEP 534 static int tilcdc_pm_suspend(struct device *dev) 535 { 536 struct drm_device *ddev = dev_get_drvdata(dev); 537 struct tilcdc_drm_private *priv = ddev->dev_private; 538 unsigned i, n = 0; 539 540 drm_kms_helper_poll_disable(ddev); 541 542 /* Save register state: */ 543 for (i = 0; i < ARRAY_SIZE(registers); i++) 544 if (registers[i].save && (priv->rev >= registers[i].rev)) 545 priv->saved_register[n++] = tilcdc_read(ddev, registers[i].reg); 546 547 return 0; 548 } 549 550 static int tilcdc_pm_resume(struct device *dev) 551 { 552 struct drm_device *ddev = dev_get_drvdata(dev); 553 struct tilcdc_drm_private *priv = ddev->dev_private; 554 unsigned i, n = 0; 555 556 /* Restore register state: */ 557 for (i = 0; i < ARRAY_SIZE(registers); i++) 558 if (registers[i].save && (priv->rev >= registers[i].rev)) 559 tilcdc_write(ddev, registers[i].reg, priv->saved_register[n++]); 560 561 drm_kms_helper_poll_enable(ddev); 562 563 return 0; 564 } 565 #endif 566 567 static const struct dev_pm_ops tilcdc_pm_ops = { 568 SET_SYSTEM_SLEEP_PM_OPS(tilcdc_pm_suspend, tilcdc_pm_resume) 569 }; 570 571 /* 572 * Platform driver: 573 */ 574 575 static int tilcdc_pdev_probe(struct platform_device *pdev) 576 { 577 /* bail out early if no DT data: */ 578 if (!pdev->dev.of_node) { 579 dev_err(&pdev->dev, "device-tree data is missing\n"); 580 return -ENXIO; 581 } 582 583 /* defer probing if slave is in deferred probing */ 584 if (slave_probing == true) 585 return -EPROBE_DEFER; 586 587 return drm_platform_init(&tilcdc_driver, pdev); 588 } 589 590 static int tilcdc_pdev_remove(struct platform_device *pdev) 591 { 592 drm_put_dev(platform_get_drvdata(pdev)); 593 594 return 0; 595 } 596 597 static struct of_device_id tilcdc_of_match[] = { 598 { .compatible = "ti,am33xx-tilcdc", }, 599 { }, 600 }; 601 MODULE_DEVICE_TABLE(of, tilcdc_of_match); 602 603 static struct platform_driver tilcdc_platform_driver = { 604 .probe = tilcdc_pdev_probe, 605 .remove = tilcdc_pdev_remove, 606 .driver = { 607 .owner = THIS_MODULE, 608 .name = "tilcdc", 609 .pm = &tilcdc_pm_ops, 610 .of_match_table = tilcdc_of_match, 611 }, 612 }; 613 614 static int __init tilcdc_drm_init(void) 615 { 616 DBG("init"); 617 tilcdc_tfp410_init(); 618 tilcdc_slave_init(); 619 tilcdc_panel_init(); 620 return platform_driver_register(&tilcdc_platform_driver); 621 } 622 623 static void __exit tilcdc_drm_fini(void) 624 { 625 DBG("fini"); 626 platform_driver_unregister(&tilcdc_platform_driver); 627 tilcdc_panel_fini(); 628 tilcdc_slave_fini(); 629 tilcdc_tfp410_fini(); 630 } 631 632 module_init(tilcdc_drm_init); 633 module_exit(tilcdc_drm_fini); 634 635 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); 636 MODULE_DESCRIPTION("TI LCD Controller DRM Driver"); 637 MODULE_LICENSE("GPL"); 638