1 /* 2 * Copyright (C) 2012 Texas Instruments 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #include <drm/drm_atomic.h> 19 #include <drm/drm_atomic_helper.h> 20 #include <drm/drm_crtc.h> 21 #include <drm/drm_flip_work.h> 22 #include <drm/drm_plane_helper.h> 23 #include <linux/workqueue.h> 24 25 #include "tilcdc_drv.h" 26 #include "tilcdc_regs.h" 27 28 #define TILCDC_VBLANK_SAFETY_THRESHOLD_US 1000 29 30 struct tilcdc_crtc { 31 struct drm_crtc base; 32 33 struct drm_plane primary; 34 const struct tilcdc_panel_info *info; 35 struct drm_pending_vblank_event *event; 36 bool enabled; 37 wait_queue_head_t frame_done_wq; 38 bool frame_done; 39 spinlock_t irq_lock; 40 41 unsigned int lcd_fck_rate; 42 43 ktime_t last_vblank; 44 45 struct drm_framebuffer *curr_fb; 46 struct drm_framebuffer *next_fb; 47 48 /* for deferred fb unref's: */ 49 struct drm_flip_work unref_work; 50 51 /* Only set if an external encoder is connected */ 52 bool simulate_vesa_sync; 53 54 int sync_lost_count; 55 bool frame_intact; 56 }; 57 #define to_tilcdc_crtc(x) container_of(x, struct tilcdc_crtc, base) 58 59 static void unref_worker(struct drm_flip_work *work, void *val) 60 { 61 struct tilcdc_crtc *tilcdc_crtc = 62 container_of(work, struct tilcdc_crtc, unref_work); 63 struct drm_device *dev = tilcdc_crtc->base.dev; 64 65 mutex_lock(&dev->mode_config.mutex); 66 drm_framebuffer_unreference(val); 67 mutex_unlock(&dev->mode_config.mutex); 68 } 69 70 static void set_scanout(struct drm_crtc *crtc, struct drm_framebuffer *fb) 71 { 72 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 73 struct drm_device *dev = crtc->dev; 74 struct drm_gem_cma_object *gem; 75 dma_addr_t start, end; 76 u64 dma_base_and_ceiling; 77 78 gem = drm_fb_cma_get_gem_obj(fb, 0); 79 80 start = gem->paddr + fb->offsets[0] + 81 crtc->y * fb->pitches[0] + 82 crtc->x * drm_format_plane_cpp(fb->pixel_format, 0); 83 84 end = start + (crtc->mode.vdisplay * fb->pitches[0]); 85 86 /* Write LCDC_DMA_FB_BASE_ADDR_0_REG and LCDC_DMA_FB_CEILING_ADDR_0_REG 87 * with a single insruction, if available. This should make it more 88 * unlikely that LCDC would fetch the DMA addresses in the middle of 89 * an update. 90 */ 91 dma_base_and_ceiling = (u64)(end - 1) << 32 | start; 92 tilcdc_write64(dev, LCDC_DMA_FB_BASE_ADDR_0_REG, dma_base_and_ceiling); 93 94 if (tilcdc_crtc->curr_fb) 95 drm_flip_work_queue(&tilcdc_crtc->unref_work, 96 tilcdc_crtc->curr_fb); 97 98 tilcdc_crtc->curr_fb = fb; 99 } 100 101 static void tilcdc_crtc_enable_irqs(struct drm_device *dev) 102 { 103 struct tilcdc_drm_private *priv = dev->dev_private; 104 105 tilcdc_clear_irqstatus(dev, 0xffffffff); 106 107 if (priv->rev == 1) { 108 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, 109 LCDC_V1_UNDERFLOW_INT_ENA); 110 tilcdc_set(dev, LCDC_DMA_CTRL_REG, 111 LCDC_V1_END_OF_FRAME_INT_ENA); 112 } else { 113 tilcdc_write(dev, LCDC_INT_ENABLE_SET_REG, 114 LCDC_V2_UNDERFLOW_INT_ENA | 115 LCDC_V2_END_OF_FRAME0_INT_ENA | 116 LCDC_FRAME_DONE | LCDC_SYNC_LOST); 117 } 118 } 119 120 static void tilcdc_crtc_disable_irqs(struct drm_device *dev) 121 { 122 struct tilcdc_drm_private *priv = dev->dev_private; 123 124 /* disable irqs that we might have enabled: */ 125 if (priv->rev == 1) { 126 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, 127 LCDC_V1_UNDERFLOW_INT_ENA | LCDC_V1_PL_INT_ENA); 128 tilcdc_clear(dev, LCDC_DMA_CTRL_REG, 129 LCDC_V1_END_OF_FRAME_INT_ENA); 130 } else { 131 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG, 132 LCDC_V2_UNDERFLOW_INT_ENA | LCDC_V2_PL_INT_ENA | 133 LCDC_V2_END_OF_FRAME0_INT_ENA | 134 LCDC_FRAME_DONE | LCDC_SYNC_LOST); 135 } 136 } 137 138 static void reset(struct drm_crtc *crtc) 139 { 140 struct drm_device *dev = crtc->dev; 141 struct tilcdc_drm_private *priv = dev->dev_private; 142 143 if (priv->rev != 2) 144 return; 145 146 tilcdc_set(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET); 147 usleep_range(250, 1000); 148 tilcdc_clear(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET); 149 } 150 151 static void tilcdc_crtc_enable(struct drm_crtc *crtc) 152 { 153 struct drm_device *dev = crtc->dev; 154 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 155 156 WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); 157 158 if (tilcdc_crtc->enabled) 159 return; 160 161 pm_runtime_get_sync(dev->dev); 162 163 reset(crtc); 164 165 tilcdc_crtc_enable_irqs(dev); 166 167 tilcdc_clear(dev, LCDC_DMA_CTRL_REG, LCDC_DUAL_FRAME_BUFFER_ENABLE); 168 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_PALETTE_LOAD_MODE(DATA_ONLY)); 169 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE); 170 171 drm_crtc_vblank_on(crtc); 172 173 tilcdc_crtc->enabled = true; 174 } 175 176 void tilcdc_crtc_disable(struct drm_crtc *crtc) 177 { 178 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 179 struct drm_device *dev = crtc->dev; 180 struct tilcdc_drm_private *priv = dev->dev_private; 181 182 WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); 183 184 if (!tilcdc_crtc->enabled) 185 return; 186 187 tilcdc_crtc->frame_done = false; 188 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE); 189 190 /* 191 * if necessary wait for framedone irq which will still come 192 * before putting things to sleep.. 193 */ 194 if (priv->rev == 2) { 195 int ret = wait_event_timeout(tilcdc_crtc->frame_done_wq, 196 tilcdc_crtc->frame_done, 197 msecs_to_jiffies(500)); 198 if (ret == 0) 199 dev_err(dev->dev, "%s: timeout waiting for framedone\n", 200 __func__); 201 } 202 203 drm_crtc_vblank_off(crtc); 204 205 tilcdc_crtc_disable_irqs(dev); 206 207 pm_runtime_put_sync(dev->dev); 208 209 if (tilcdc_crtc->next_fb) { 210 drm_flip_work_queue(&tilcdc_crtc->unref_work, 211 tilcdc_crtc->next_fb); 212 tilcdc_crtc->next_fb = NULL; 213 } 214 215 if (tilcdc_crtc->curr_fb) { 216 drm_flip_work_queue(&tilcdc_crtc->unref_work, 217 tilcdc_crtc->curr_fb); 218 tilcdc_crtc->curr_fb = NULL; 219 } 220 221 drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq); 222 tilcdc_crtc->last_vblank = ktime_set(0, 0); 223 224 tilcdc_crtc->enabled = false; 225 } 226 227 static bool tilcdc_crtc_is_on(struct drm_crtc *crtc) 228 { 229 return crtc->state && crtc->state->enable && crtc->state->active; 230 } 231 232 static void tilcdc_crtc_destroy(struct drm_crtc *crtc) 233 { 234 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 235 struct tilcdc_drm_private *priv = crtc->dev->dev_private; 236 237 drm_modeset_lock_crtc(crtc, NULL); 238 tilcdc_crtc_disable(crtc); 239 drm_modeset_unlock_crtc(crtc); 240 241 flush_workqueue(priv->wq); 242 243 of_node_put(crtc->port); 244 drm_crtc_cleanup(crtc); 245 drm_flip_work_cleanup(&tilcdc_crtc->unref_work); 246 } 247 248 int tilcdc_crtc_update_fb(struct drm_crtc *crtc, 249 struct drm_framebuffer *fb, 250 struct drm_pending_vblank_event *event) 251 { 252 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 253 struct drm_device *dev = crtc->dev; 254 unsigned long flags; 255 256 WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); 257 258 if (tilcdc_crtc->event) { 259 dev_err(dev->dev, "already pending page flip!\n"); 260 return -EBUSY; 261 } 262 263 drm_framebuffer_reference(fb); 264 265 crtc->primary->fb = fb; 266 267 spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags); 268 269 if (crtc->hwmode.vrefresh && ktime_to_ns(tilcdc_crtc->last_vblank)) { 270 ktime_t next_vblank; 271 s64 tdiff; 272 273 next_vblank = ktime_add_us(tilcdc_crtc->last_vblank, 274 1000000 / crtc->hwmode.vrefresh); 275 276 tdiff = ktime_to_us(ktime_sub(next_vblank, ktime_get())); 277 278 if (tdiff < TILCDC_VBLANK_SAFETY_THRESHOLD_US) 279 tilcdc_crtc->next_fb = fb; 280 } 281 282 if (tilcdc_crtc->next_fb != fb) 283 set_scanout(crtc, fb); 284 285 tilcdc_crtc->event = event; 286 287 spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags); 288 289 return 0; 290 } 291 292 static bool tilcdc_crtc_mode_fixup(struct drm_crtc *crtc, 293 const struct drm_display_mode *mode, 294 struct drm_display_mode *adjusted_mode) 295 { 296 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 297 298 if (!tilcdc_crtc->simulate_vesa_sync) 299 return true; 300 301 /* 302 * tilcdc does not generate VESA-compliant sync but aligns 303 * VS on the second edge of HS instead of first edge. 304 * We use adjusted_mode, to fixup sync by aligning both rising 305 * edges and add HSKEW offset to fix the sync. 306 */ 307 adjusted_mode->hskew = mode->hsync_end - mode->hsync_start; 308 adjusted_mode->flags |= DRM_MODE_FLAG_HSKEW; 309 310 if (mode->flags & DRM_MODE_FLAG_NHSYNC) { 311 adjusted_mode->flags |= DRM_MODE_FLAG_PHSYNC; 312 adjusted_mode->flags &= ~DRM_MODE_FLAG_NHSYNC; 313 } else { 314 adjusted_mode->flags |= DRM_MODE_FLAG_NHSYNC; 315 adjusted_mode->flags &= ~DRM_MODE_FLAG_PHSYNC; 316 } 317 318 return true; 319 } 320 321 static void tilcdc_crtc_set_clk(struct drm_crtc *crtc) 322 { 323 struct drm_device *dev = crtc->dev; 324 struct tilcdc_drm_private *priv = dev->dev_private; 325 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 326 const unsigned clkdiv = 2; /* using a fixed divider of 2 */ 327 int ret; 328 329 /* mode.clock is in KHz, set_rate wants parameter in Hz */ 330 ret = clk_set_rate(priv->clk, crtc->mode.clock * 1000 * clkdiv); 331 if (ret < 0) { 332 dev_err(dev->dev, "failed to set display clock rate to: %d\n", 333 crtc->mode.clock); 334 return; 335 } 336 337 tilcdc_crtc->lcd_fck_rate = clk_get_rate(priv->clk); 338 339 DBG("lcd_clk=%u, mode clock=%d, div=%u", 340 tilcdc_crtc->lcd_fck_rate, crtc->mode.clock, clkdiv); 341 342 /* Configure the LCD clock divisor. */ 343 tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(clkdiv) | 344 LCDC_RASTER_MODE); 345 346 if (priv->rev == 2) 347 tilcdc_set(dev, LCDC_CLK_ENABLE_REG, 348 LCDC_V2_DMA_CLK_EN | LCDC_V2_LIDD_CLK_EN | 349 LCDC_V2_CORE_CLK_EN); 350 } 351 352 static void tilcdc_crtc_mode_set_nofb(struct drm_crtc *crtc) 353 { 354 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 355 struct drm_device *dev = crtc->dev; 356 struct tilcdc_drm_private *priv = dev->dev_private; 357 const struct tilcdc_panel_info *info = tilcdc_crtc->info; 358 uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw; 359 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 360 struct drm_framebuffer *fb = crtc->primary->state->fb; 361 362 WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); 363 364 if (WARN_ON(!info)) 365 return; 366 367 if (WARN_ON(!fb)) 368 return; 369 370 /* Configure the Burst Size and fifo threshold of DMA: */ 371 reg = tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x00000770; 372 switch (info->dma_burst_sz) { 373 case 1: 374 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_1); 375 break; 376 case 2: 377 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_2); 378 break; 379 case 4: 380 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_4); 381 break; 382 case 8: 383 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_8); 384 break; 385 case 16: 386 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_16); 387 break; 388 default: 389 dev_err(dev->dev, "invalid burst size\n"); 390 return; 391 } 392 reg |= (info->fifo_th << 8); 393 tilcdc_write(dev, LCDC_DMA_CTRL_REG, reg); 394 395 /* Configure timings: */ 396 hbp = mode->htotal - mode->hsync_end; 397 hfp = mode->hsync_start - mode->hdisplay; 398 hsw = mode->hsync_end - mode->hsync_start; 399 vbp = mode->vtotal - mode->vsync_end; 400 vfp = mode->vsync_start - mode->vdisplay; 401 vsw = mode->vsync_end - mode->vsync_start; 402 403 DBG("%dx%d, hbp=%u, hfp=%u, hsw=%u, vbp=%u, vfp=%u, vsw=%u", 404 mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, vfp, vsw); 405 406 /* Set AC Bias Period and Number of Transitions per Interrupt: */ 407 reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00; 408 reg |= LCDC_AC_BIAS_FREQUENCY(info->ac_bias) | 409 LCDC_AC_BIAS_TRANSITIONS_PER_INT(info->ac_bias_intrpt); 410 411 /* 412 * subtract one from hfp, hbp, hsw because the hardware uses 413 * a value of 0 as 1 414 */ 415 if (priv->rev == 2) { 416 /* clear bits we're going to set */ 417 reg &= ~0x78000033; 418 reg |= ((hfp-1) & 0x300) >> 8; 419 reg |= ((hbp-1) & 0x300) >> 4; 420 reg |= ((hsw-1) & 0x3c0) << 21; 421 } 422 tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg); 423 424 reg = (((mode->hdisplay >> 4) - 1) << 4) | 425 (((hbp-1) & 0xff) << 24) | 426 (((hfp-1) & 0xff) << 16) | 427 (((hsw-1) & 0x3f) << 10); 428 if (priv->rev == 2) 429 reg |= (((mode->hdisplay >> 4) - 1) & 0x40) >> 3; 430 tilcdc_write(dev, LCDC_RASTER_TIMING_0_REG, reg); 431 432 reg = ((mode->vdisplay - 1) & 0x3ff) | 433 ((vbp & 0xff) << 24) | 434 ((vfp & 0xff) << 16) | 435 (((vsw-1) & 0x3f) << 10); 436 tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg); 437 438 /* 439 * be sure to set Bit 10 for the V2 LCDC controller, 440 * otherwise limited to 1024 pixels width, stopping 441 * 1920x1080 being supported. 442 */ 443 if (priv->rev == 2) { 444 if ((mode->vdisplay - 1) & 0x400) { 445 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, 446 LCDC_LPP_B10); 447 } else { 448 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, 449 LCDC_LPP_B10); 450 } 451 } 452 453 /* Configure display type: */ 454 reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) & 455 ~(LCDC_TFT_MODE | LCDC_MONO_8BIT_MODE | LCDC_MONOCHROME_MODE | 456 LCDC_V2_TFT_24BPP_MODE | LCDC_V2_TFT_24BPP_UNPACK | 457 0x000ff000 /* Palette Loading Delay bits */); 458 reg |= LCDC_TFT_MODE; /* no monochrome/passive support */ 459 if (info->tft_alt_mode) 460 reg |= LCDC_TFT_ALT_ENABLE; 461 if (priv->rev == 2) { 462 switch (fb->pixel_format) { 463 case DRM_FORMAT_BGR565: 464 case DRM_FORMAT_RGB565: 465 break; 466 case DRM_FORMAT_XBGR8888: 467 case DRM_FORMAT_XRGB8888: 468 reg |= LCDC_V2_TFT_24BPP_UNPACK; 469 /* fallthrough */ 470 case DRM_FORMAT_BGR888: 471 case DRM_FORMAT_RGB888: 472 reg |= LCDC_V2_TFT_24BPP_MODE; 473 break; 474 default: 475 dev_err(dev->dev, "invalid pixel format\n"); 476 return; 477 } 478 } 479 reg |= info->fdd < 12; 480 tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg); 481 482 if (info->invert_pxl_clk) 483 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK); 484 else 485 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK); 486 487 if (info->sync_ctrl) 488 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL); 489 else 490 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL); 491 492 if (info->sync_edge) 493 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE); 494 else 495 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE); 496 497 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 498 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC); 499 else 500 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC); 501 502 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 503 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC); 504 else 505 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC); 506 507 if (info->raster_order) 508 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER); 509 else 510 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER); 511 512 drm_framebuffer_reference(fb); 513 514 set_scanout(crtc, fb); 515 516 tilcdc_crtc_set_clk(crtc); 517 518 crtc->hwmode = crtc->state->adjusted_mode; 519 } 520 521 static int tilcdc_crtc_atomic_check(struct drm_crtc *crtc, 522 struct drm_crtc_state *state) 523 { 524 struct drm_display_mode *mode = &state->mode; 525 int ret; 526 527 /* If we are not active we don't care */ 528 if (!state->active) 529 return 0; 530 531 if (state->state->planes[0].ptr != crtc->primary || 532 state->state->planes[0].state == NULL || 533 state->state->planes[0].state->crtc != crtc) { 534 dev_dbg(crtc->dev->dev, "CRTC primary plane must be present"); 535 return -EINVAL; 536 } 537 538 ret = tilcdc_crtc_mode_valid(crtc, mode); 539 if (ret) { 540 dev_dbg(crtc->dev->dev, "Mode \"%s\" not valid", mode->name); 541 return -EINVAL; 542 } 543 544 return 0; 545 } 546 547 static const struct drm_crtc_funcs tilcdc_crtc_funcs = { 548 .destroy = tilcdc_crtc_destroy, 549 .set_config = drm_atomic_helper_set_config, 550 .page_flip = drm_atomic_helper_page_flip, 551 .reset = drm_atomic_helper_crtc_reset, 552 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 553 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 554 }; 555 556 static const struct drm_crtc_helper_funcs tilcdc_crtc_helper_funcs = { 557 .mode_fixup = tilcdc_crtc_mode_fixup, 558 .enable = tilcdc_crtc_enable, 559 .disable = tilcdc_crtc_disable, 560 .atomic_check = tilcdc_crtc_atomic_check, 561 .mode_set_nofb = tilcdc_crtc_mode_set_nofb, 562 }; 563 564 int tilcdc_crtc_max_width(struct drm_crtc *crtc) 565 { 566 struct drm_device *dev = crtc->dev; 567 struct tilcdc_drm_private *priv = dev->dev_private; 568 int max_width = 0; 569 570 if (priv->rev == 1) 571 max_width = 1024; 572 else if (priv->rev == 2) 573 max_width = 2048; 574 575 return max_width; 576 } 577 578 int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode) 579 { 580 struct tilcdc_drm_private *priv = crtc->dev->dev_private; 581 unsigned int bandwidth; 582 uint32_t hbp, hfp, hsw, vbp, vfp, vsw; 583 584 /* 585 * check to see if the width is within the range that 586 * the LCD Controller physically supports 587 */ 588 if (mode->hdisplay > tilcdc_crtc_max_width(crtc)) 589 return MODE_VIRTUAL_X; 590 591 /* width must be multiple of 16 */ 592 if (mode->hdisplay & 0xf) 593 return MODE_VIRTUAL_X; 594 595 if (mode->vdisplay > 2048) 596 return MODE_VIRTUAL_Y; 597 598 DBG("Processing mode %dx%d@%d with pixel clock %d", 599 mode->hdisplay, mode->vdisplay, 600 drm_mode_vrefresh(mode), mode->clock); 601 602 hbp = mode->htotal - mode->hsync_end; 603 hfp = mode->hsync_start - mode->hdisplay; 604 hsw = mode->hsync_end - mode->hsync_start; 605 vbp = mode->vtotal - mode->vsync_end; 606 vfp = mode->vsync_start - mode->vdisplay; 607 vsw = mode->vsync_end - mode->vsync_start; 608 609 if ((hbp-1) & ~0x3ff) { 610 DBG("Pruning mode: Horizontal Back Porch out of range"); 611 return MODE_HBLANK_WIDE; 612 } 613 614 if ((hfp-1) & ~0x3ff) { 615 DBG("Pruning mode: Horizontal Front Porch out of range"); 616 return MODE_HBLANK_WIDE; 617 } 618 619 if ((hsw-1) & ~0x3ff) { 620 DBG("Pruning mode: Horizontal Sync Width out of range"); 621 return MODE_HSYNC_WIDE; 622 } 623 624 if (vbp & ~0xff) { 625 DBG("Pruning mode: Vertical Back Porch out of range"); 626 return MODE_VBLANK_WIDE; 627 } 628 629 if (vfp & ~0xff) { 630 DBG("Pruning mode: Vertical Front Porch out of range"); 631 return MODE_VBLANK_WIDE; 632 } 633 634 if ((vsw-1) & ~0x3f) { 635 DBG("Pruning mode: Vertical Sync Width out of range"); 636 return MODE_VSYNC_WIDE; 637 } 638 639 /* 640 * some devices have a maximum allowed pixel clock 641 * configured from the DT 642 */ 643 if (mode->clock > priv->max_pixelclock) { 644 DBG("Pruning mode: pixel clock too high"); 645 return MODE_CLOCK_HIGH; 646 } 647 648 /* 649 * some devices further limit the max horizontal resolution 650 * configured from the DT 651 */ 652 if (mode->hdisplay > priv->max_width) 653 return MODE_BAD_WIDTH; 654 655 /* filter out modes that would require too much memory bandwidth: */ 656 bandwidth = mode->hdisplay * mode->vdisplay * 657 drm_mode_vrefresh(mode); 658 if (bandwidth > priv->max_bandwidth) { 659 DBG("Pruning mode: exceeds defined bandwidth limit"); 660 return MODE_BAD; 661 } 662 663 return MODE_OK; 664 } 665 666 void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc, 667 const struct tilcdc_panel_info *info) 668 { 669 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 670 tilcdc_crtc->info = info; 671 } 672 673 void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc, 674 bool simulate_vesa_sync) 675 { 676 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 677 678 tilcdc_crtc->simulate_vesa_sync = simulate_vesa_sync; 679 } 680 681 void tilcdc_crtc_update_clk(struct drm_crtc *crtc) 682 { 683 struct drm_device *dev = crtc->dev; 684 struct tilcdc_drm_private *priv = dev->dev_private; 685 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 686 687 drm_modeset_lock_crtc(crtc, NULL); 688 if (tilcdc_crtc->lcd_fck_rate != clk_get_rate(priv->clk)) { 689 if (tilcdc_crtc_is_on(crtc)) { 690 pm_runtime_get_sync(dev->dev); 691 tilcdc_crtc_disable(crtc); 692 693 tilcdc_crtc_set_clk(crtc); 694 695 tilcdc_crtc_enable(crtc); 696 pm_runtime_put_sync(dev->dev); 697 } 698 } 699 drm_modeset_unlock_crtc(crtc); 700 } 701 702 #define SYNC_LOST_COUNT_LIMIT 50 703 704 irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc) 705 { 706 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 707 struct drm_device *dev = crtc->dev; 708 struct tilcdc_drm_private *priv = dev->dev_private; 709 uint32_t stat; 710 711 stat = tilcdc_read_irqstatus(dev); 712 tilcdc_clear_irqstatus(dev, stat); 713 714 if (stat & LCDC_END_OF_FRAME0) { 715 unsigned long flags; 716 bool skip_event = false; 717 ktime_t now; 718 719 now = ktime_get(); 720 721 drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq); 722 723 spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags); 724 725 tilcdc_crtc->last_vblank = now; 726 727 if (tilcdc_crtc->next_fb) { 728 set_scanout(crtc, tilcdc_crtc->next_fb); 729 tilcdc_crtc->next_fb = NULL; 730 skip_event = true; 731 } 732 733 spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags); 734 735 drm_crtc_handle_vblank(crtc); 736 737 if (!skip_event) { 738 struct drm_pending_vblank_event *event; 739 740 spin_lock_irqsave(&dev->event_lock, flags); 741 742 event = tilcdc_crtc->event; 743 tilcdc_crtc->event = NULL; 744 if (event) 745 drm_crtc_send_vblank_event(crtc, event); 746 747 spin_unlock_irqrestore(&dev->event_lock, flags); 748 } 749 750 if (tilcdc_crtc->frame_intact) 751 tilcdc_crtc->sync_lost_count = 0; 752 else 753 tilcdc_crtc->frame_intact = true; 754 } 755 756 if (stat & LCDC_FIFO_UNDERFLOW) 757 dev_err_ratelimited(dev->dev, "%s(0x%08x): FIFO underfow", 758 __func__, stat); 759 760 /* For revision 2 only */ 761 if (priv->rev == 2) { 762 if (stat & LCDC_FRAME_DONE) { 763 tilcdc_crtc->frame_done = true; 764 wake_up(&tilcdc_crtc->frame_done_wq); 765 } 766 767 if (stat & LCDC_SYNC_LOST) { 768 dev_err_ratelimited(dev->dev, "%s(0x%08x): Sync lost", 769 __func__, stat); 770 tilcdc_crtc->frame_intact = false; 771 if (tilcdc_crtc->sync_lost_count++ > 772 SYNC_LOST_COUNT_LIMIT) { 773 dev_err(dev->dev, "%s(0x%08x): Sync lost flood detected, disabling the interrupt", __func__, stat); 774 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG, 775 LCDC_SYNC_LOST); 776 } 777 } 778 779 /* Indicate to LCDC that the interrupt service routine has 780 * completed, see 13.3.6.1.6 in AM335x TRM. 781 */ 782 tilcdc_write(dev, LCDC_END_OF_INT_IND_REG, 0); 783 } 784 785 return IRQ_HANDLED; 786 } 787 788 struct drm_crtc *tilcdc_crtc_create(struct drm_device *dev) 789 { 790 struct tilcdc_drm_private *priv = dev->dev_private; 791 struct tilcdc_crtc *tilcdc_crtc; 792 struct drm_crtc *crtc; 793 int ret; 794 795 tilcdc_crtc = devm_kzalloc(dev->dev, sizeof(*tilcdc_crtc), GFP_KERNEL); 796 if (!tilcdc_crtc) { 797 dev_err(dev->dev, "allocation failed\n"); 798 return NULL; 799 } 800 801 crtc = &tilcdc_crtc->base; 802 803 ret = tilcdc_plane_init(dev, &tilcdc_crtc->primary); 804 if (ret < 0) 805 goto fail; 806 807 init_waitqueue_head(&tilcdc_crtc->frame_done_wq); 808 809 drm_flip_work_init(&tilcdc_crtc->unref_work, 810 "unref", unref_worker); 811 812 spin_lock_init(&tilcdc_crtc->irq_lock); 813 814 ret = drm_crtc_init_with_planes(dev, crtc, 815 &tilcdc_crtc->primary, 816 NULL, 817 &tilcdc_crtc_funcs, 818 "tilcdc crtc"); 819 if (ret < 0) 820 goto fail; 821 822 drm_crtc_helper_add(crtc, &tilcdc_crtc_helper_funcs); 823 824 if (priv->is_componentized) { 825 struct device_node *ports = 826 of_get_child_by_name(dev->dev->of_node, "ports"); 827 828 if (ports) { 829 crtc->port = of_get_child_by_name(ports, "port"); 830 of_node_put(ports); 831 } else { 832 crtc->port = 833 of_get_child_by_name(dev->dev->of_node, "port"); 834 } 835 if (!crtc->port) { /* This should never happen */ 836 dev_err(dev->dev, "Port node not found in %s\n", 837 dev->dev->of_node->full_name); 838 goto fail; 839 } 840 } 841 842 return crtc; 843 844 fail: 845 tilcdc_crtc_destroy(crtc); 846 return NULL; 847 } 848