1 /* 2 * Copyright (C) 2012 Texas Instruments 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #include "drm_flip_work.h" 19 #include <drm/drm_plane_helper.h> 20 21 #include "tilcdc_drv.h" 22 #include "tilcdc_regs.h" 23 24 struct tilcdc_crtc { 25 struct drm_crtc base; 26 27 const struct tilcdc_panel_info *info; 28 uint32_t dirty; 29 dma_addr_t start, end; 30 struct drm_pending_vblank_event *event; 31 int dpms; 32 wait_queue_head_t frame_done_wq; 33 bool frame_done; 34 35 /* fb currently set to scanout 0/1: */ 36 struct drm_framebuffer *scanout[2]; 37 38 /* for deferred fb unref's: */ 39 struct drm_flip_work unref_work; 40 41 /* Only set if an external encoder is connected */ 42 bool simulate_vesa_sync; 43 }; 44 #define to_tilcdc_crtc(x) container_of(x, struct tilcdc_crtc, base) 45 46 static void unref_worker(struct drm_flip_work *work, void *val) 47 { 48 struct tilcdc_crtc *tilcdc_crtc = 49 container_of(work, struct tilcdc_crtc, unref_work); 50 struct drm_device *dev = tilcdc_crtc->base.dev; 51 52 mutex_lock(&dev->mode_config.mutex); 53 drm_framebuffer_unreference(val); 54 mutex_unlock(&dev->mode_config.mutex); 55 } 56 57 static void set_scanout(struct drm_crtc *crtc, int n) 58 { 59 static const uint32_t base_reg[] = { 60 LCDC_DMA_FB_BASE_ADDR_0_REG, 61 LCDC_DMA_FB_BASE_ADDR_1_REG, 62 }; 63 static const uint32_t ceil_reg[] = { 64 LCDC_DMA_FB_CEILING_ADDR_0_REG, 65 LCDC_DMA_FB_CEILING_ADDR_1_REG, 66 }; 67 static const uint32_t stat[] = { 68 LCDC_END_OF_FRAME0, LCDC_END_OF_FRAME1, 69 }; 70 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 71 struct drm_device *dev = crtc->dev; 72 struct tilcdc_drm_private *priv = dev->dev_private; 73 74 pm_runtime_get_sync(dev->dev); 75 tilcdc_write(dev, base_reg[n], tilcdc_crtc->start); 76 tilcdc_write(dev, ceil_reg[n], tilcdc_crtc->end); 77 if (tilcdc_crtc->scanout[n]) { 78 drm_flip_work_queue(&tilcdc_crtc->unref_work, tilcdc_crtc->scanout[n]); 79 drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq); 80 } 81 tilcdc_crtc->scanout[n] = crtc->primary->fb; 82 drm_framebuffer_reference(tilcdc_crtc->scanout[n]); 83 tilcdc_crtc->dirty &= ~stat[n]; 84 pm_runtime_put_sync(dev->dev); 85 } 86 87 static void update_scanout(struct drm_crtc *crtc) 88 { 89 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 90 struct drm_device *dev = crtc->dev; 91 struct drm_framebuffer *fb = crtc->primary->fb; 92 struct drm_gem_cma_object *gem; 93 unsigned int depth, bpp; 94 95 drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp); 96 gem = drm_fb_cma_get_gem_obj(fb, 0); 97 98 tilcdc_crtc->start = gem->paddr + fb->offsets[0] + 99 (crtc->y * fb->pitches[0]) + (crtc->x * bpp/8); 100 101 tilcdc_crtc->end = tilcdc_crtc->start + 102 (crtc->mode.vdisplay * fb->pitches[0]); 103 104 if (tilcdc_crtc->dpms == DRM_MODE_DPMS_ON) { 105 /* already enabled, so just mark the frames that need 106 * updating and they will be updated on vblank: 107 */ 108 tilcdc_crtc->dirty |= LCDC_END_OF_FRAME0 | LCDC_END_OF_FRAME1; 109 drm_vblank_get(dev, 0); 110 } else { 111 /* not enabled yet, so update registers immediately: */ 112 set_scanout(crtc, 0); 113 set_scanout(crtc, 1); 114 } 115 } 116 117 static void start(struct drm_crtc *crtc) 118 { 119 struct drm_device *dev = crtc->dev; 120 struct tilcdc_drm_private *priv = dev->dev_private; 121 122 if (priv->rev == 2) { 123 tilcdc_set(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET); 124 msleep(1); 125 tilcdc_clear(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET); 126 msleep(1); 127 } 128 129 tilcdc_set(dev, LCDC_DMA_CTRL_REG, LCDC_DUAL_FRAME_BUFFER_ENABLE); 130 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_PALETTE_LOAD_MODE(DATA_ONLY)); 131 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE); 132 } 133 134 static void stop(struct drm_crtc *crtc) 135 { 136 struct drm_device *dev = crtc->dev; 137 138 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE); 139 } 140 141 static void tilcdc_crtc_dpms(struct drm_crtc *crtc, int mode); 142 static void tilcdc_crtc_destroy(struct drm_crtc *crtc) 143 { 144 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 145 146 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 147 148 drm_crtc_cleanup(crtc); 149 drm_flip_work_cleanup(&tilcdc_crtc->unref_work); 150 151 kfree(tilcdc_crtc); 152 } 153 154 static int tilcdc_crtc_page_flip(struct drm_crtc *crtc, 155 struct drm_framebuffer *fb, 156 struct drm_pending_vblank_event *event, 157 uint32_t page_flip_flags) 158 { 159 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 160 struct drm_device *dev = crtc->dev; 161 162 if (tilcdc_crtc->event) { 163 dev_err(dev->dev, "already pending page flip!\n"); 164 return -EBUSY; 165 } 166 167 crtc->primary->fb = fb; 168 tilcdc_crtc->event = event; 169 update_scanout(crtc); 170 171 return 0; 172 } 173 174 static void tilcdc_crtc_dpms(struct drm_crtc *crtc, int mode) 175 { 176 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 177 struct drm_device *dev = crtc->dev; 178 struct tilcdc_drm_private *priv = dev->dev_private; 179 180 /* we really only care about on or off: */ 181 if (mode != DRM_MODE_DPMS_ON) 182 mode = DRM_MODE_DPMS_OFF; 183 184 if (tilcdc_crtc->dpms == mode) 185 return; 186 187 tilcdc_crtc->dpms = mode; 188 189 pm_runtime_get_sync(dev->dev); 190 191 if (mode == DRM_MODE_DPMS_ON) { 192 pm_runtime_forbid(dev->dev); 193 start(crtc); 194 } else { 195 tilcdc_crtc->frame_done = false; 196 stop(crtc); 197 198 /* 199 * if necessary wait for framedone irq which will still come 200 * before putting things to sleep.. 201 */ 202 if (priv->rev == 2) { 203 int ret = wait_event_timeout( 204 tilcdc_crtc->frame_done_wq, 205 tilcdc_crtc->frame_done, 206 msecs_to_jiffies(50)); 207 if (ret == 0) 208 dev_err(dev->dev, "timeout waiting for framedone\n"); 209 } 210 pm_runtime_allow(dev->dev); 211 } 212 213 pm_runtime_put_sync(dev->dev); 214 } 215 216 static bool tilcdc_crtc_mode_fixup(struct drm_crtc *crtc, 217 const struct drm_display_mode *mode, 218 struct drm_display_mode *adjusted_mode) 219 { 220 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 221 222 if (!tilcdc_crtc->simulate_vesa_sync) 223 return true; 224 225 /* 226 * tilcdc does not generate VESA-compliant sync but aligns 227 * VS on the second edge of HS instead of first edge. 228 * We use adjusted_mode, to fixup sync by aligning both rising 229 * edges and add HSKEW offset to fix the sync. 230 */ 231 adjusted_mode->hskew = mode->hsync_end - mode->hsync_start; 232 adjusted_mode->flags |= DRM_MODE_FLAG_HSKEW; 233 234 if (mode->flags & DRM_MODE_FLAG_NHSYNC) { 235 adjusted_mode->flags |= DRM_MODE_FLAG_PHSYNC; 236 adjusted_mode->flags &= ~DRM_MODE_FLAG_NHSYNC; 237 } else { 238 adjusted_mode->flags |= DRM_MODE_FLAG_NHSYNC; 239 adjusted_mode->flags &= ~DRM_MODE_FLAG_PHSYNC; 240 } 241 242 return true; 243 } 244 245 static void tilcdc_crtc_prepare(struct drm_crtc *crtc) 246 { 247 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 248 } 249 250 static void tilcdc_crtc_commit(struct drm_crtc *crtc) 251 { 252 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 253 } 254 255 static int tilcdc_crtc_mode_set(struct drm_crtc *crtc, 256 struct drm_display_mode *mode, 257 struct drm_display_mode *adjusted_mode, 258 int x, int y, 259 struct drm_framebuffer *old_fb) 260 { 261 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 262 struct drm_device *dev = crtc->dev; 263 struct tilcdc_drm_private *priv = dev->dev_private; 264 const struct tilcdc_panel_info *info = tilcdc_crtc->info; 265 uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw; 266 int ret; 267 268 ret = tilcdc_crtc_mode_valid(crtc, mode); 269 if (WARN_ON(ret)) 270 return ret; 271 272 if (WARN_ON(!info)) 273 return -EINVAL; 274 275 pm_runtime_get_sync(dev->dev); 276 277 /* Configure the Burst Size and fifo threshold of DMA: */ 278 reg = tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x00000770; 279 switch (info->dma_burst_sz) { 280 case 1: 281 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_1); 282 break; 283 case 2: 284 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_2); 285 break; 286 case 4: 287 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_4); 288 break; 289 case 8: 290 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_8); 291 break; 292 case 16: 293 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_16); 294 break; 295 default: 296 return -EINVAL; 297 } 298 reg |= (info->fifo_th << 8); 299 tilcdc_write(dev, LCDC_DMA_CTRL_REG, reg); 300 301 /* Configure timings: */ 302 hbp = mode->htotal - mode->hsync_end; 303 hfp = mode->hsync_start - mode->hdisplay; 304 hsw = mode->hsync_end - mode->hsync_start; 305 vbp = mode->vtotal - mode->vsync_end; 306 vfp = mode->vsync_start - mode->vdisplay; 307 vsw = mode->vsync_end - mode->vsync_start; 308 309 DBG("%dx%d, hbp=%u, hfp=%u, hsw=%u, vbp=%u, vfp=%u, vsw=%u", 310 mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, vfp, vsw); 311 312 /* Configure the AC Bias Period and Number of Transitions per Interrupt: */ 313 reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00; 314 reg |= LCDC_AC_BIAS_FREQUENCY(info->ac_bias) | 315 LCDC_AC_BIAS_TRANSITIONS_PER_INT(info->ac_bias_intrpt); 316 317 /* 318 * subtract one from hfp, hbp, hsw because the hardware uses 319 * a value of 0 as 1 320 */ 321 if (priv->rev == 2) { 322 /* clear bits we're going to set */ 323 reg &= ~0x78000033; 324 reg |= ((hfp-1) & 0x300) >> 8; 325 reg |= ((hbp-1) & 0x300) >> 4; 326 reg |= ((hsw-1) & 0x3c0) << 21; 327 } 328 tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg); 329 330 reg = (((mode->hdisplay >> 4) - 1) << 4) | 331 (((hbp-1) & 0xff) << 24) | 332 (((hfp-1) & 0xff) << 16) | 333 (((hsw-1) & 0x3f) << 10); 334 if (priv->rev == 2) 335 reg |= (((mode->hdisplay >> 4) - 1) & 0x40) >> 3; 336 tilcdc_write(dev, LCDC_RASTER_TIMING_0_REG, reg); 337 338 reg = ((mode->vdisplay - 1) & 0x3ff) | 339 ((vbp & 0xff) << 24) | 340 ((vfp & 0xff) << 16) | 341 (((vsw-1) & 0x3f) << 10); 342 tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg); 343 344 /* 345 * be sure to set Bit 10 for the V2 LCDC controller, 346 * otherwise limited to 1024 pixels width, stopping 347 * 1920x1080 being suppoted. 348 */ 349 if (priv->rev == 2) { 350 if ((mode->vdisplay - 1) & 0x400) { 351 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, 352 LCDC_LPP_B10); 353 } else { 354 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, 355 LCDC_LPP_B10); 356 } 357 } 358 359 /* Configure display type: */ 360 reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) & 361 ~(LCDC_TFT_MODE | LCDC_MONO_8BIT_MODE | LCDC_MONOCHROME_MODE | 362 LCDC_V2_TFT_24BPP_MODE | LCDC_V2_TFT_24BPP_UNPACK | 0x000ff000); 363 reg |= LCDC_TFT_MODE; /* no monochrome/passive support */ 364 if (info->tft_alt_mode) 365 reg |= LCDC_TFT_ALT_ENABLE; 366 if (priv->rev == 2) { 367 unsigned int depth, bpp; 368 369 drm_fb_get_bpp_depth(crtc->primary->fb->pixel_format, &depth, &bpp); 370 switch (bpp) { 371 case 16: 372 break; 373 case 32: 374 reg |= LCDC_V2_TFT_24BPP_UNPACK; 375 /* fallthrough */ 376 case 24: 377 reg |= LCDC_V2_TFT_24BPP_MODE; 378 break; 379 default: 380 dev_err(dev->dev, "invalid pixel format\n"); 381 return -EINVAL; 382 } 383 } 384 reg |= info->fdd < 12; 385 tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg); 386 387 if (info->invert_pxl_clk) 388 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK); 389 else 390 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK); 391 392 if (info->sync_ctrl) 393 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL); 394 else 395 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL); 396 397 if (info->sync_edge) 398 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE); 399 else 400 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE); 401 402 /* 403 * use value from adjusted_mode here as this might have been 404 * changed as part of the fixup for slave encoders to solve the 405 * issue where tilcdc timings are not VESA compliant 406 */ 407 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) 408 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC); 409 else 410 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC); 411 412 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 413 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC); 414 else 415 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC); 416 417 if (info->raster_order) 418 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER); 419 else 420 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER); 421 422 423 update_scanout(crtc); 424 tilcdc_crtc_update_clk(crtc); 425 426 pm_runtime_put_sync(dev->dev); 427 428 return 0; 429 } 430 431 static int tilcdc_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 432 struct drm_framebuffer *old_fb) 433 { 434 update_scanout(crtc); 435 return 0; 436 } 437 438 static const struct drm_crtc_funcs tilcdc_crtc_funcs = { 439 .destroy = tilcdc_crtc_destroy, 440 .set_config = drm_crtc_helper_set_config, 441 .page_flip = tilcdc_crtc_page_flip, 442 }; 443 444 static const struct drm_crtc_helper_funcs tilcdc_crtc_helper_funcs = { 445 .dpms = tilcdc_crtc_dpms, 446 .mode_fixup = tilcdc_crtc_mode_fixup, 447 .prepare = tilcdc_crtc_prepare, 448 .commit = tilcdc_crtc_commit, 449 .mode_set = tilcdc_crtc_mode_set, 450 .mode_set_base = tilcdc_crtc_mode_set_base, 451 }; 452 453 int tilcdc_crtc_max_width(struct drm_crtc *crtc) 454 { 455 struct drm_device *dev = crtc->dev; 456 struct tilcdc_drm_private *priv = dev->dev_private; 457 int max_width = 0; 458 459 if (priv->rev == 1) 460 max_width = 1024; 461 else if (priv->rev == 2) 462 max_width = 2048; 463 464 return max_width; 465 } 466 467 int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode) 468 { 469 struct tilcdc_drm_private *priv = crtc->dev->dev_private; 470 unsigned int bandwidth; 471 uint32_t hbp, hfp, hsw, vbp, vfp, vsw; 472 473 /* 474 * check to see if the width is within the range that 475 * the LCD Controller physically supports 476 */ 477 if (mode->hdisplay > tilcdc_crtc_max_width(crtc)) 478 return MODE_VIRTUAL_X; 479 480 /* width must be multiple of 16 */ 481 if (mode->hdisplay & 0xf) 482 return MODE_VIRTUAL_X; 483 484 if (mode->vdisplay > 2048) 485 return MODE_VIRTUAL_Y; 486 487 DBG("Processing mode %dx%d@%d with pixel clock %d", 488 mode->hdisplay, mode->vdisplay, 489 drm_mode_vrefresh(mode), mode->clock); 490 491 hbp = mode->htotal - mode->hsync_end; 492 hfp = mode->hsync_start - mode->hdisplay; 493 hsw = mode->hsync_end - mode->hsync_start; 494 vbp = mode->vtotal - mode->vsync_end; 495 vfp = mode->vsync_start - mode->vdisplay; 496 vsw = mode->vsync_end - mode->vsync_start; 497 498 if ((hbp-1) & ~0x3ff) { 499 DBG("Pruning mode: Horizontal Back Porch out of range"); 500 return MODE_HBLANK_WIDE; 501 } 502 503 if ((hfp-1) & ~0x3ff) { 504 DBG("Pruning mode: Horizontal Front Porch out of range"); 505 return MODE_HBLANK_WIDE; 506 } 507 508 if ((hsw-1) & ~0x3ff) { 509 DBG("Pruning mode: Horizontal Sync Width out of range"); 510 return MODE_HSYNC_WIDE; 511 } 512 513 if (vbp & ~0xff) { 514 DBG("Pruning mode: Vertical Back Porch out of range"); 515 return MODE_VBLANK_WIDE; 516 } 517 518 if (vfp & ~0xff) { 519 DBG("Pruning mode: Vertical Front Porch out of range"); 520 return MODE_VBLANK_WIDE; 521 } 522 523 if ((vsw-1) & ~0x3f) { 524 DBG("Pruning mode: Vertical Sync Width out of range"); 525 return MODE_VSYNC_WIDE; 526 } 527 528 /* 529 * some devices have a maximum allowed pixel clock 530 * configured from the DT 531 */ 532 if (mode->clock > priv->max_pixelclock) { 533 DBG("Pruning mode: pixel clock too high"); 534 return MODE_CLOCK_HIGH; 535 } 536 537 /* 538 * some devices further limit the max horizontal resolution 539 * configured from the DT 540 */ 541 if (mode->hdisplay > priv->max_width) 542 return MODE_BAD_WIDTH; 543 544 /* filter out modes that would require too much memory bandwidth: */ 545 bandwidth = mode->hdisplay * mode->vdisplay * 546 drm_mode_vrefresh(mode); 547 if (bandwidth > priv->max_bandwidth) { 548 DBG("Pruning mode: exceeds defined bandwidth limit"); 549 return MODE_BAD; 550 } 551 552 return MODE_OK; 553 } 554 555 void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc, 556 const struct tilcdc_panel_info *info) 557 { 558 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 559 tilcdc_crtc->info = info; 560 } 561 562 void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc, 563 bool simulate_vesa_sync) 564 { 565 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 566 567 tilcdc_crtc->simulate_vesa_sync = simulate_vesa_sync; 568 } 569 570 void tilcdc_crtc_update_clk(struct drm_crtc *crtc) 571 { 572 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 573 struct drm_device *dev = crtc->dev; 574 struct tilcdc_drm_private *priv = dev->dev_private; 575 int dpms = tilcdc_crtc->dpms; 576 unsigned int lcd_clk, div; 577 int ret; 578 579 pm_runtime_get_sync(dev->dev); 580 581 if (dpms == DRM_MODE_DPMS_ON) 582 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 583 584 /* in raster mode, minimum divisor is 2: */ 585 ret = clk_set_rate(priv->disp_clk, crtc->mode.clock * 1000 * 2); 586 if (ret) { 587 dev_err(dev->dev, "failed to set display clock rate to: %d\n", 588 crtc->mode.clock); 589 goto out; 590 } 591 592 lcd_clk = clk_get_rate(priv->clk); 593 div = lcd_clk / (crtc->mode.clock * 1000); 594 595 DBG("lcd_clk=%u, mode clock=%d, div=%u", lcd_clk, crtc->mode.clock, div); 596 DBG("fck=%lu, dpll_disp_ck=%lu", clk_get_rate(priv->clk), clk_get_rate(priv->disp_clk)); 597 598 /* Configure the LCD clock divisor. */ 599 tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(div) | 600 LCDC_RASTER_MODE); 601 602 if (priv->rev == 2) 603 tilcdc_set(dev, LCDC_CLK_ENABLE_REG, 604 LCDC_V2_DMA_CLK_EN | LCDC_V2_LIDD_CLK_EN | 605 LCDC_V2_CORE_CLK_EN); 606 607 if (dpms == DRM_MODE_DPMS_ON) 608 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 609 610 out: 611 pm_runtime_put_sync(dev->dev); 612 } 613 614 irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc) 615 { 616 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 617 struct drm_device *dev = crtc->dev; 618 struct tilcdc_drm_private *priv = dev->dev_private; 619 uint32_t stat = tilcdc_read_irqstatus(dev); 620 621 if ((stat & LCDC_SYNC_LOST) && (stat & LCDC_FIFO_UNDERFLOW)) { 622 stop(crtc); 623 dev_err(dev->dev, "error: %08x\n", stat); 624 tilcdc_clear_irqstatus(dev, stat); 625 start(crtc); 626 } else if (stat & LCDC_PL_LOAD_DONE) { 627 tilcdc_clear_irqstatus(dev, stat); 628 } else { 629 struct drm_pending_vblank_event *event; 630 unsigned long flags; 631 uint32_t dirty = tilcdc_crtc->dirty & stat; 632 633 tilcdc_clear_irqstatus(dev, stat); 634 635 if (dirty & LCDC_END_OF_FRAME0) 636 set_scanout(crtc, 0); 637 638 if (dirty & LCDC_END_OF_FRAME1) 639 set_scanout(crtc, 1); 640 641 drm_handle_vblank(dev, 0); 642 643 spin_lock_irqsave(&dev->event_lock, flags); 644 event = tilcdc_crtc->event; 645 tilcdc_crtc->event = NULL; 646 if (event) 647 drm_send_vblank_event(dev, 0, event); 648 spin_unlock_irqrestore(&dev->event_lock, flags); 649 650 if (dirty && !tilcdc_crtc->dirty) 651 drm_vblank_put(dev, 0); 652 } 653 654 if (priv->rev == 2) { 655 if (stat & LCDC_FRAME_DONE) { 656 tilcdc_crtc->frame_done = true; 657 wake_up(&tilcdc_crtc->frame_done_wq); 658 } 659 tilcdc_write(dev, LCDC_END_OF_INT_IND_REG, 0); 660 } 661 662 return IRQ_HANDLED; 663 } 664 665 void tilcdc_crtc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file) 666 { 667 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 668 struct drm_pending_vblank_event *event; 669 struct drm_device *dev = crtc->dev; 670 unsigned long flags; 671 672 /* Destroy the pending vertical blanking event associated with the 673 * pending page flip, if any, and disable vertical blanking interrupts. 674 */ 675 spin_lock_irqsave(&dev->event_lock, flags); 676 event = tilcdc_crtc->event; 677 if (event && event->base.file_priv == file) { 678 tilcdc_crtc->event = NULL; 679 event->base.destroy(&event->base); 680 drm_vblank_put(dev, 0); 681 } 682 spin_unlock_irqrestore(&dev->event_lock, flags); 683 } 684 685 struct drm_crtc *tilcdc_crtc_create(struct drm_device *dev) 686 { 687 struct tilcdc_crtc *tilcdc_crtc; 688 struct drm_crtc *crtc; 689 int ret; 690 691 tilcdc_crtc = kzalloc(sizeof(*tilcdc_crtc), GFP_KERNEL); 692 if (!tilcdc_crtc) { 693 dev_err(dev->dev, "allocation failed\n"); 694 return NULL; 695 } 696 697 crtc = &tilcdc_crtc->base; 698 699 tilcdc_crtc->dpms = DRM_MODE_DPMS_OFF; 700 init_waitqueue_head(&tilcdc_crtc->frame_done_wq); 701 702 drm_flip_work_init(&tilcdc_crtc->unref_work, 703 "unref", unref_worker); 704 705 ret = drm_crtc_init(dev, crtc, &tilcdc_crtc_funcs); 706 if (ret < 0) 707 goto fail; 708 709 drm_crtc_helper_add(crtc, &tilcdc_crtc_helper_funcs); 710 711 return crtc; 712 713 fail: 714 tilcdc_crtc_destroy(crtc); 715 return NULL; 716 } 717