1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012 Texas Instruments 4 * Author: Rob Clark <robdclark@gmail.com> 5 */ 6 7 #include <linux/delay.h> 8 #include <linux/dma-mapping.h> 9 #include <linux/of_graph.h> 10 #include <linux/pm_runtime.h> 11 12 #include <drm/drm_atomic.h> 13 #include <drm/drm_atomic_helper.h> 14 #include <drm/drm_crtc.h> 15 #include <drm/drm_fb_cma_helper.h> 16 #include <drm/drm_fourcc.h> 17 #include <drm/drm_gem_cma_helper.h> 18 #include <drm/drm_modeset_helper_vtables.h> 19 #include <drm/drm_print.h> 20 #include <drm/drm_vblank.h> 21 22 #include "tilcdc_drv.h" 23 #include "tilcdc_regs.h" 24 25 #define TILCDC_VBLANK_SAFETY_THRESHOLD_US 1000 26 #define TILCDC_PALETTE_SIZE 32 27 #define TILCDC_PALETTE_FIRST_ENTRY 0x4000 28 29 struct tilcdc_crtc { 30 struct drm_crtc base; 31 32 struct drm_plane primary; 33 const struct tilcdc_panel_info *info; 34 struct drm_pending_vblank_event *event; 35 struct mutex enable_lock; 36 bool enabled; 37 bool shutdown; 38 wait_queue_head_t frame_done_wq; 39 bool frame_done; 40 spinlock_t irq_lock; 41 42 unsigned int lcd_fck_rate; 43 44 ktime_t last_vblank; 45 unsigned int hvtotal_us; 46 47 struct drm_framebuffer *next_fb; 48 49 /* Only set if an external encoder is connected */ 50 bool simulate_vesa_sync; 51 52 int sync_lost_count; 53 bool frame_intact; 54 struct work_struct recover_work; 55 56 dma_addr_t palette_dma_handle; 57 u16 *palette_base; 58 struct completion palette_loaded; 59 }; 60 #define to_tilcdc_crtc(x) container_of(x, struct tilcdc_crtc, base) 61 62 static void set_scanout(struct drm_crtc *crtc, struct drm_framebuffer *fb) 63 { 64 struct drm_device *dev = crtc->dev; 65 struct tilcdc_drm_private *priv = dev->dev_private; 66 struct drm_gem_cma_object *gem; 67 dma_addr_t start, end; 68 u64 dma_base_and_ceiling; 69 70 gem = drm_fb_cma_get_gem_obj(fb, 0); 71 72 start = gem->paddr + fb->offsets[0] + 73 crtc->y * fb->pitches[0] + 74 crtc->x * fb->format->cpp[0]; 75 76 end = start + (crtc->mode.vdisplay * fb->pitches[0]); 77 78 /* Write LCDC_DMA_FB_BASE_ADDR_0_REG and LCDC_DMA_FB_CEILING_ADDR_0_REG 79 * with a single insruction, if available. This should make it more 80 * unlikely that LCDC would fetch the DMA addresses in the middle of 81 * an update. 82 */ 83 if (priv->rev == 1) 84 end -= 1; 85 86 dma_base_and_ceiling = (u64)end << 32 | start; 87 tilcdc_write64(dev, LCDC_DMA_FB_BASE_ADDR_0_REG, dma_base_and_ceiling); 88 } 89 90 /* 91 * The driver currently only supports only true color formats. For 92 * true color the palette block is bypassed, but a 32 byte palette 93 * should still be loaded. The first 16-bit entry must be 0x4000 while 94 * all other entries must be zeroed. 95 */ 96 static void tilcdc_crtc_load_palette(struct drm_crtc *crtc) 97 { 98 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 99 struct drm_device *dev = crtc->dev; 100 struct tilcdc_drm_private *priv = dev->dev_private; 101 int ret; 102 103 reinit_completion(&tilcdc_crtc->palette_loaded); 104 105 /* Tell the LCDC where the palette is located. */ 106 tilcdc_write(dev, LCDC_DMA_FB_BASE_ADDR_0_REG, 107 tilcdc_crtc->palette_dma_handle); 108 tilcdc_write(dev, LCDC_DMA_FB_CEILING_ADDR_0_REG, 109 (u32) tilcdc_crtc->palette_dma_handle + 110 TILCDC_PALETTE_SIZE - 1); 111 112 /* Set dma load mode for palette loading only. */ 113 tilcdc_write_mask(dev, LCDC_RASTER_CTRL_REG, 114 LCDC_PALETTE_LOAD_MODE(PALETTE_ONLY), 115 LCDC_PALETTE_LOAD_MODE_MASK); 116 117 /* Enable DMA Palette Loaded Interrupt */ 118 if (priv->rev == 1) 119 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_PL_INT_ENA); 120 else 121 tilcdc_write(dev, LCDC_INT_ENABLE_SET_REG, LCDC_V2_PL_INT_ENA); 122 123 /* Enable LCDC DMA and wait for palette to be loaded. */ 124 tilcdc_clear_irqstatus(dev, 0xffffffff); 125 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE); 126 127 ret = wait_for_completion_timeout(&tilcdc_crtc->palette_loaded, 128 msecs_to_jiffies(50)); 129 if (ret == 0) 130 dev_err(dev->dev, "%s: Palette loading timeout", __func__); 131 132 /* Disable LCDC DMA and DMA Palette Loaded Interrupt. */ 133 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE); 134 if (priv->rev == 1) 135 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_PL_INT_ENA); 136 else 137 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG, LCDC_V2_PL_INT_ENA); 138 } 139 140 static void tilcdc_crtc_enable_irqs(struct drm_device *dev) 141 { 142 struct tilcdc_drm_private *priv = dev->dev_private; 143 144 tilcdc_clear_irqstatus(dev, 0xffffffff); 145 146 if (priv->rev == 1) { 147 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, 148 LCDC_V1_SYNC_LOST_INT_ENA | LCDC_V1_FRAME_DONE_INT_ENA | 149 LCDC_V1_UNDERFLOW_INT_ENA); 150 tilcdc_set(dev, LCDC_DMA_CTRL_REG, 151 LCDC_V1_END_OF_FRAME_INT_ENA); 152 } else { 153 tilcdc_write(dev, LCDC_INT_ENABLE_SET_REG, 154 LCDC_V2_UNDERFLOW_INT_ENA | 155 LCDC_V2_END_OF_FRAME0_INT_ENA | 156 LCDC_FRAME_DONE | LCDC_SYNC_LOST); 157 } 158 } 159 160 static void tilcdc_crtc_disable_irqs(struct drm_device *dev) 161 { 162 struct tilcdc_drm_private *priv = dev->dev_private; 163 164 /* disable irqs that we might have enabled: */ 165 if (priv->rev == 1) { 166 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, 167 LCDC_V1_SYNC_LOST_INT_ENA | LCDC_V1_FRAME_DONE_INT_ENA | 168 LCDC_V1_UNDERFLOW_INT_ENA | LCDC_V1_PL_INT_ENA); 169 tilcdc_clear(dev, LCDC_DMA_CTRL_REG, 170 LCDC_V1_END_OF_FRAME_INT_ENA); 171 } else { 172 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG, 173 LCDC_V2_UNDERFLOW_INT_ENA | LCDC_V2_PL_INT_ENA | 174 LCDC_V2_END_OF_FRAME0_INT_ENA | 175 LCDC_FRAME_DONE | LCDC_SYNC_LOST); 176 } 177 } 178 179 static void reset(struct drm_crtc *crtc) 180 { 181 struct drm_device *dev = crtc->dev; 182 struct tilcdc_drm_private *priv = dev->dev_private; 183 184 if (priv->rev != 2) 185 return; 186 187 tilcdc_set(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET); 188 usleep_range(250, 1000); 189 tilcdc_clear(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET); 190 } 191 192 /* 193 * Calculate the percentage difference between the requested pixel clock rate 194 * and the effective rate resulting from calculating the clock divider value. 195 */ 196 static unsigned int tilcdc_pclk_diff(unsigned long rate, 197 unsigned long real_rate) 198 { 199 int r = rate / 100, rr = real_rate / 100; 200 201 return (unsigned int)(abs(((rr - r) * 100) / r)); 202 } 203 204 static void tilcdc_crtc_set_clk(struct drm_crtc *crtc) 205 { 206 struct drm_device *dev = crtc->dev; 207 struct tilcdc_drm_private *priv = dev->dev_private; 208 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 209 unsigned long clk_rate, real_rate, req_rate; 210 unsigned int clkdiv; 211 int ret; 212 213 clkdiv = 2; /* first try using a standard divider of 2 */ 214 215 /* mode.clock is in KHz, set_rate wants parameter in Hz */ 216 req_rate = crtc->mode.clock * 1000; 217 218 ret = clk_set_rate(priv->clk, req_rate * clkdiv); 219 clk_rate = clk_get_rate(priv->clk); 220 if (ret < 0 || tilcdc_pclk_diff(req_rate, clk_rate) > 5) { 221 /* 222 * If we fail to set the clock rate (some architectures don't 223 * use the common clock framework yet and may not implement 224 * all the clk API calls for every clock), try the next best 225 * thing: adjusting the clock divider, unless clk_get_rate() 226 * failed as well. 227 */ 228 if (!clk_rate) { 229 /* Nothing more we can do. Just bail out. */ 230 dev_err(dev->dev, 231 "failed to set the pixel clock - unable to read current lcdc clock rate\n"); 232 return; 233 } 234 235 clkdiv = DIV_ROUND_CLOSEST(clk_rate, req_rate); 236 237 /* 238 * Emit a warning if the real clock rate resulting from the 239 * calculated divider differs much from the requested rate. 240 * 241 * 5% is an arbitrary value - LCDs are usually quite tolerant 242 * about pixel clock rates. 243 */ 244 real_rate = clkdiv * req_rate; 245 246 if (tilcdc_pclk_diff(clk_rate, real_rate) > 5) { 247 dev_warn(dev->dev, 248 "effective pixel clock rate (%luHz) differs from the calculated rate (%luHz)\n", 249 clk_rate, real_rate); 250 } 251 } 252 253 tilcdc_crtc->lcd_fck_rate = clk_rate; 254 255 DBG("lcd_clk=%u, mode clock=%d, div=%u", 256 tilcdc_crtc->lcd_fck_rate, crtc->mode.clock, clkdiv); 257 258 /* Configure the LCD clock divisor. */ 259 tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(clkdiv) | 260 LCDC_RASTER_MODE); 261 262 if (priv->rev == 2) 263 tilcdc_set(dev, LCDC_CLK_ENABLE_REG, 264 LCDC_V2_DMA_CLK_EN | LCDC_V2_LIDD_CLK_EN | 265 LCDC_V2_CORE_CLK_EN); 266 } 267 268 static uint tilcdc_mode_hvtotal(const struct drm_display_mode *mode) 269 { 270 return (uint) div_u64(1000llu * mode->htotal * mode->vtotal, 271 mode->clock); 272 } 273 274 static void tilcdc_crtc_set_mode(struct drm_crtc *crtc) 275 { 276 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 277 struct drm_device *dev = crtc->dev; 278 struct tilcdc_drm_private *priv = dev->dev_private; 279 const struct tilcdc_panel_info *info = tilcdc_crtc->info; 280 uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw; 281 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 282 struct drm_framebuffer *fb = crtc->primary->state->fb; 283 284 if (WARN_ON(!info)) 285 return; 286 287 if (WARN_ON(!fb)) 288 return; 289 290 /* Configure the Burst Size and fifo threshold of DMA: */ 291 reg = tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x00000770; 292 switch (info->dma_burst_sz) { 293 case 1: 294 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_1); 295 break; 296 case 2: 297 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_2); 298 break; 299 case 4: 300 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_4); 301 break; 302 case 8: 303 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_8); 304 break; 305 case 16: 306 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_16); 307 break; 308 default: 309 dev_err(dev->dev, "invalid burst size\n"); 310 return; 311 } 312 reg |= (info->fifo_th << 8); 313 tilcdc_write(dev, LCDC_DMA_CTRL_REG, reg); 314 315 /* Configure timings: */ 316 hbp = mode->htotal - mode->hsync_end; 317 hfp = mode->hsync_start - mode->hdisplay; 318 hsw = mode->hsync_end - mode->hsync_start; 319 vbp = mode->vtotal - mode->vsync_end; 320 vfp = mode->vsync_start - mode->vdisplay; 321 vsw = mode->vsync_end - mode->vsync_start; 322 323 DBG("%dx%d, hbp=%u, hfp=%u, hsw=%u, vbp=%u, vfp=%u, vsw=%u", 324 mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, vfp, vsw); 325 326 /* Set AC Bias Period and Number of Transitions per Interrupt: */ 327 reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00; 328 reg |= LCDC_AC_BIAS_FREQUENCY(info->ac_bias) | 329 LCDC_AC_BIAS_TRANSITIONS_PER_INT(info->ac_bias_intrpt); 330 331 /* 332 * subtract one from hfp, hbp, hsw because the hardware uses 333 * a value of 0 as 1 334 */ 335 if (priv->rev == 2) { 336 /* clear bits we're going to set */ 337 reg &= ~0x78000033; 338 reg |= ((hfp-1) & 0x300) >> 8; 339 reg |= ((hbp-1) & 0x300) >> 4; 340 reg |= ((hsw-1) & 0x3c0) << 21; 341 } 342 tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg); 343 344 reg = (((mode->hdisplay >> 4) - 1) << 4) | 345 (((hbp-1) & 0xff) << 24) | 346 (((hfp-1) & 0xff) << 16) | 347 (((hsw-1) & 0x3f) << 10); 348 if (priv->rev == 2) 349 reg |= (((mode->hdisplay >> 4) - 1) & 0x40) >> 3; 350 tilcdc_write(dev, LCDC_RASTER_TIMING_0_REG, reg); 351 352 reg = ((mode->vdisplay - 1) & 0x3ff) | 353 ((vbp & 0xff) << 24) | 354 ((vfp & 0xff) << 16) | 355 (((vsw-1) & 0x3f) << 10); 356 tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg); 357 358 /* 359 * be sure to set Bit 10 for the V2 LCDC controller, 360 * otherwise limited to 1024 pixels width, stopping 361 * 1920x1080 being supported. 362 */ 363 if (priv->rev == 2) { 364 if ((mode->vdisplay - 1) & 0x400) { 365 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, 366 LCDC_LPP_B10); 367 } else { 368 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, 369 LCDC_LPP_B10); 370 } 371 } 372 373 /* Configure display type: */ 374 reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) & 375 ~(LCDC_TFT_MODE | LCDC_MONO_8BIT_MODE | LCDC_MONOCHROME_MODE | 376 LCDC_V2_TFT_24BPP_MODE | LCDC_V2_TFT_24BPP_UNPACK | 377 0x000ff000 /* Palette Loading Delay bits */); 378 reg |= LCDC_TFT_MODE; /* no monochrome/passive support */ 379 if (info->tft_alt_mode) 380 reg |= LCDC_TFT_ALT_ENABLE; 381 if (priv->rev == 2) { 382 switch (fb->format->format) { 383 case DRM_FORMAT_BGR565: 384 case DRM_FORMAT_RGB565: 385 break; 386 case DRM_FORMAT_XBGR8888: 387 case DRM_FORMAT_XRGB8888: 388 reg |= LCDC_V2_TFT_24BPP_UNPACK; 389 /* fallthrough */ 390 case DRM_FORMAT_BGR888: 391 case DRM_FORMAT_RGB888: 392 reg |= LCDC_V2_TFT_24BPP_MODE; 393 break; 394 default: 395 dev_err(dev->dev, "invalid pixel format\n"); 396 return; 397 } 398 } 399 reg |= info->fdd < 12; 400 tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg); 401 402 if (info->invert_pxl_clk) 403 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK); 404 else 405 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK); 406 407 if (info->sync_ctrl) 408 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL); 409 else 410 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL); 411 412 if (info->sync_edge) 413 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE); 414 else 415 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE); 416 417 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 418 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC); 419 else 420 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC); 421 422 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 423 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC); 424 else 425 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC); 426 427 if (info->raster_order) 428 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER); 429 else 430 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER); 431 432 tilcdc_crtc_set_clk(crtc); 433 434 tilcdc_crtc_load_palette(crtc); 435 436 set_scanout(crtc, fb); 437 438 crtc->hwmode = crtc->state->adjusted_mode; 439 440 tilcdc_crtc->hvtotal_us = 441 tilcdc_mode_hvtotal(&crtc->hwmode); 442 } 443 444 static void tilcdc_crtc_enable(struct drm_crtc *crtc) 445 { 446 struct drm_device *dev = crtc->dev; 447 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 448 unsigned long flags; 449 450 mutex_lock(&tilcdc_crtc->enable_lock); 451 if (tilcdc_crtc->enabled || tilcdc_crtc->shutdown) { 452 mutex_unlock(&tilcdc_crtc->enable_lock); 453 return; 454 } 455 456 pm_runtime_get_sync(dev->dev); 457 458 reset(crtc); 459 460 tilcdc_crtc_set_mode(crtc); 461 462 tilcdc_crtc_enable_irqs(dev); 463 464 tilcdc_clear(dev, LCDC_DMA_CTRL_REG, LCDC_DUAL_FRAME_BUFFER_ENABLE); 465 tilcdc_write_mask(dev, LCDC_RASTER_CTRL_REG, 466 LCDC_PALETTE_LOAD_MODE(DATA_ONLY), 467 LCDC_PALETTE_LOAD_MODE_MASK); 468 469 /* There is no real chance for a race here as the time stamp 470 * is taken before the raster DMA is started. The spin-lock is 471 * taken to have a memory barrier after taking the time-stamp 472 * and to avoid a context switch between taking the stamp and 473 * enabling the raster. 474 */ 475 spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags); 476 tilcdc_crtc->last_vblank = ktime_get(); 477 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE); 478 spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags); 479 480 drm_crtc_vblank_on(crtc); 481 482 tilcdc_crtc->enabled = true; 483 mutex_unlock(&tilcdc_crtc->enable_lock); 484 } 485 486 static void tilcdc_crtc_atomic_enable(struct drm_crtc *crtc, 487 struct drm_crtc_state *old_state) 488 { 489 tilcdc_crtc_enable(crtc); 490 } 491 492 static void tilcdc_crtc_off(struct drm_crtc *crtc, bool shutdown) 493 { 494 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 495 struct drm_device *dev = crtc->dev; 496 int ret; 497 498 mutex_lock(&tilcdc_crtc->enable_lock); 499 if (shutdown) 500 tilcdc_crtc->shutdown = true; 501 if (!tilcdc_crtc->enabled) { 502 mutex_unlock(&tilcdc_crtc->enable_lock); 503 return; 504 } 505 tilcdc_crtc->frame_done = false; 506 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE); 507 508 /* 509 * Wait for framedone irq which will still come before putting 510 * things to sleep.. 511 */ 512 ret = wait_event_timeout(tilcdc_crtc->frame_done_wq, 513 tilcdc_crtc->frame_done, 514 msecs_to_jiffies(500)); 515 if (ret == 0) 516 dev_err(dev->dev, "%s: timeout waiting for framedone\n", 517 __func__); 518 519 drm_crtc_vblank_off(crtc); 520 521 tilcdc_crtc_disable_irqs(dev); 522 523 pm_runtime_put_sync(dev->dev); 524 525 tilcdc_crtc->enabled = false; 526 mutex_unlock(&tilcdc_crtc->enable_lock); 527 } 528 529 static void tilcdc_crtc_disable(struct drm_crtc *crtc) 530 { 531 tilcdc_crtc_off(crtc, false); 532 } 533 534 static void tilcdc_crtc_atomic_disable(struct drm_crtc *crtc, 535 struct drm_crtc_state *old_state) 536 { 537 tilcdc_crtc_disable(crtc); 538 } 539 540 void tilcdc_crtc_shutdown(struct drm_crtc *crtc) 541 { 542 tilcdc_crtc_off(crtc, true); 543 } 544 545 static bool tilcdc_crtc_is_on(struct drm_crtc *crtc) 546 { 547 return crtc->state && crtc->state->enable && crtc->state->active; 548 } 549 550 static void tilcdc_crtc_recover_work(struct work_struct *work) 551 { 552 struct tilcdc_crtc *tilcdc_crtc = 553 container_of(work, struct tilcdc_crtc, recover_work); 554 struct drm_crtc *crtc = &tilcdc_crtc->base; 555 556 dev_info(crtc->dev->dev, "%s: Reset CRTC", __func__); 557 558 drm_modeset_lock(&crtc->mutex, NULL); 559 560 if (!tilcdc_crtc_is_on(crtc)) 561 goto out; 562 563 tilcdc_crtc_disable(crtc); 564 tilcdc_crtc_enable(crtc); 565 out: 566 drm_modeset_unlock(&crtc->mutex); 567 } 568 569 static void tilcdc_crtc_destroy(struct drm_crtc *crtc) 570 { 571 struct tilcdc_drm_private *priv = crtc->dev->dev_private; 572 573 tilcdc_crtc_shutdown(crtc); 574 575 flush_workqueue(priv->wq); 576 577 of_node_put(crtc->port); 578 drm_crtc_cleanup(crtc); 579 } 580 581 int tilcdc_crtc_update_fb(struct drm_crtc *crtc, 582 struct drm_framebuffer *fb, 583 struct drm_pending_vblank_event *event) 584 { 585 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 586 struct drm_device *dev = crtc->dev; 587 588 if (tilcdc_crtc->event) { 589 dev_err(dev->dev, "already pending page flip!\n"); 590 return -EBUSY; 591 } 592 593 tilcdc_crtc->event = event; 594 595 mutex_lock(&tilcdc_crtc->enable_lock); 596 597 if (tilcdc_crtc->enabled) { 598 unsigned long flags; 599 ktime_t next_vblank; 600 s64 tdiff; 601 602 spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags); 603 604 next_vblank = ktime_add_us(tilcdc_crtc->last_vblank, 605 tilcdc_crtc->hvtotal_us); 606 tdiff = ktime_to_us(ktime_sub(next_vblank, ktime_get())); 607 608 if (tdiff < TILCDC_VBLANK_SAFETY_THRESHOLD_US) 609 tilcdc_crtc->next_fb = fb; 610 else 611 set_scanout(crtc, fb); 612 613 spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags); 614 } 615 616 mutex_unlock(&tilcdc_crtc->enable_lock); 617 618 return 0; 619 } 620 621 static bool tilcdc_crtc_mode_fixup(struct drm_crtc *crtc, 622 const struct drm_display_mode *mode, 623 struct drm_display_mode *adjusted_mode) 624 { 625 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 626 627 if (!tilcdc_crtc->simulate_vesa_sync) 628 return true; 629 630 /* 631 * tilcdc does not generate VESA-compliant sync but aligns 632 * VS on the second edge of HS instead of first edge. 633 * We use adjusted_mode, to fixup sync by aligning both rising 634 * edges and add HSKEW offset to fix the sync. 635 */ 636 adjusted_mode->hskew = mode->hsync_end - mode->hsync_start; 637 adjusted_mode->flags |= DRM_MODE_FLAG_HSKEW; 638 639 if (mode->flags & DRM_MODE_FLAG_NHSYNC) { 640 adjusted_mode->flags |= DRM_MODE_FLAG_PHSYNC; 641 adjusted_mode->flags &= ~DRM_MODE_FLAG_NHSYNC; 642 } else { 643 adjusted_mode->flags |= DRM_MODE_FLAG_NHSYNC; 644 adjusted_mode->flags &= ~DRM_MODE_FLAG_PHSYNC; 645 } 646 647 return true; 648 } 649 650 static int tilcdc_crtc_atomic_check(struct drm_crtc *crtc, 651 struct drm_crtc_state *state) 652 { 653 /* If we are not active we don't care */ 654 if (!state->active) 655 return 0; 656 657 if (state->state->planes[0].ptr != crtc->primary || 658 state->state->planes[0].state == NULL || 659 state->state->planes[0].state->crtc != crtc) { 660 dev_dbg(crtc->dev->dev, "CRTC primary plane must be present"); 661 return -EINVAL; 662 } 663 664 return 0; 665 } 666 667 static int tilcdc_crtc_enable_vblank(struct drm_crtc *crtc) 668 { 669 return 0; 670 } 671 672 static void tilcdc_crtc_disable_vblank(struct drm_crtc *crtc) 673 { 674 } 675 676 static void tilcdc_crtc_reset(struct drm_crtc *crtc) 677 { 678 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 679 struct drm_device *dev = crtc->dev; 680 int ret; 681 682 drm_atomic_helper_crtc_reset(crtc); 683 684 /* Turn the raster off if it for some reason is on. */ 685 pm_runtime_get_sync(dev->dev); 686 if (tilcdc_read(dev, LCDC_RASTER_CTRL_REG) & LCDC_RASTER_ENABLE) { 687 /* Enable DMA Frame Done Interrupt */ 688 tilcdc_write(dev, LCDC_INT_ENABLE_SET_REG, LCDC_FRAME_DONE); 689 tilcdc_clear_irqstatus(dev, 0xffffffff); 690 691 tilcdc_crtc->frame_done = false; 692 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE); 693 694 ret = wait_event_timeout(tilcdc_crtc->frame_done_wq, 695 tilcdc_crtc->frame_done, 696 msecs_to_jiffies(500)); 697 if (ret == 0) 698 dev_err(dev->dev, "%s: timeout waiting for framedone\n", 699 __func__); 700 } 701 pm_runtime_put_sync(dev->dev); 702 } 703 704 static const struct drm_crtc_funcs tilcdc_crtc_funcs = { 705 .destroy = tilcdc_crtc_destroy, 706 .set_config = drm_atomic_helper_set_config, 707 .page_flip = drm_atomic_helper_page_flip, 708 .reset = tilcdc_crtc_reset, 709 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 710 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 711 .enable_vblank = tilcdc_crtc_enable_vblank, 712 .disable_vblank = tilcdc_crtc_disable_vblank, 713 }; 714 715 int tilcdc_crtc_max_width(struct drm_crtc *crtc) 716 { 717 struct drm_device *dev = crtc->dev; 718 struct tilcdc_drm_private *priv = dev->dev_private; 719 int max_width = 0; 720 721 if (priv->rev == 1) 722 max_width = 1024; 723 else if (priv->rev == 2) 724 max_width = 2048; 725 726 return max_width; 727 } 728 729 static enum drm_mode_status 730 tilcdc_crtc_mode_valid(struct drm_crtc *crtc, 731 const struct drm_display_mode *mode) 732 { 733 struct tilcdc_drm_private *priv = crtc->dev->dev_private; 734 unsigned int bandwidth; 735 uint32_t hbp, hfp, hsw, vbp, vfp, vsw; 736 737 /* 738 * check to see if the width is within the range that 739 * the LCD Controller physically supports 740 */ 741 if (mode->hdisplay > tilcdc_crtc_max_width(crtc)) 742 return MODE_VIRTUAL_X; 743 744 /* width must be multiple of 16 */ 745 if (mode->hdisplay & 0xf) 746 return MODE_VIRTUAL_X; 747 748 if (mode->vdisplay > 2048) 749 return MODE_VIRTUAL_Y; 750 751 DBG("Processing mode %dx%d@%d with pixel clock %d", 752 mode->hdisplay, mode->vdisplay, 753 drm_mode_vrefresh(mode), mode->clock); 754 755 hbp = mode->htotal - mode->hsync_end; 756 hfp = mode->hsync_start - mode->hdisplay; 757 hsw = mode->hsync_end - mode->hsync_start; 758 vbp = mode->vtotal - mode->vsync_end; 759 vfp = mode->vsync_start - mode->vdisplay; 760 vsw = mode->vsync_end - mode->vsync_start; 761 762 if ((hbp-1) & ~0x3ff) { 763 DBG("Pruning mode: Horizontal Back Porch out of range"); 764 return MODE_HBLANK_WIDE; 765 } 766 767 if ((hfp-1) & ~0x3ff) { 768 DBG("Pruning mode: Horizontal Front Porch out of range"); 769 return MODE_HBLANK_WIDE; 770 } 771 772 if ((hsw-1) & ~0x3ff) { 773 DBG("Pruning mode: Horizontal Sync Width out of range"); 774 return MODE_HSYNC_WIDE; 775 } 776 777 if (vbp & ~0xff) { 778 DBG("Pruning mode: Vertical Back Porch out of range"); 779 return MODE_VBLANK_WIDE; 780 } 781 782 if (vfp & ~0xff) { 783 DBG("Pruning mode: Vertical Front Porch out of range"); 784 return MODE_VBLANK_WIDE; 785 } 786 787 if ((vsw-1) & ~0x3f) { 788 DBG("Pruning mode: Vertical Sync Width out of range"); 789 return MODE_VSYNC_WIDE; 790 } 791 792 /* 793 * some devices have a maximum allowed pixel clock 794 * configured from the DT 795 */ 796 if (mode->clock > priv->max_pixelclock) { 797 DBG("Pruning mode: pixel clock too high"); 798 return MODE_CLOCK_HIGH; 799 } 800 801 /* 802 * some devices further limit the max horizontal resolution 803 * configured from the DT 804 */ 805 if (mode->hdisplay > priv->max_width) 806 return MODE_BAD_WIDTH; 807 808 /* filter out modes that would require too much memory bandwidth: */ 809 bandwidth = mode->hdisplay * mode->vdisplay * 810 drm_mode_vrefresh(mode); 811 if (bandwidth > priv->max_bandwidth) { 812 DBG("Pruning mode: exceeds defined bandwidth limit"); 813 return MODE_BAD; 814 } 815 816 return MODE_OK; 817 } 818 819 static const struct drm_crtc_helper_funcs tilcdc_crtc_helper_funcs = { 820 .mode_valid = tilcdc_crtc_mode_valid, 821 .mode_fixup = tilcdc_crtc_mode_fixup, 822 .atomic_check = tilcdc_crtc_atomic_check, 823 .atomic_enable = tilcdc_crtc_atomic_enable, 824 .atomic_disable = tilcdc_crtc_atomic_disable, 825 }; 826 827 void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc, 828 const struct tilcdc_panel_info *info) 829 { 830 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 831 tilcdc_crtc->info = info; 832 } 833 834 void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc, 835 bool simulate_vesa_sync) 836 { 837 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 838 839 tilcdc_crtc->simulate_vesa_sync = simulate_vesa_sync; 840 } 841 842 void tilcdc_crtc_update_clk(struct drm_crtc *crtc) 843 { 844 struct drm_device *dev = crtc->dev; 845 struct tilcdc_drm_private *priv = dev->dev_private; 846 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 847 848 drm_modeset_lock(&crtc->mutex, NULL); 849 if (tilcdc_crtc->lcd_fck_rate != clk_get_rate(priv->clk)) { 850 if (tilcdc_crtc_is_on(crtc)) { 851 pm_runtime_get_sync(dev->dev); 852 tilcdc_crtc_disable(crtc); 853 854 tilcdc_crtc_set_clk(crtc); 855 856 tilcdc_crtc_enable(crtc); 857 pm_runtime_put_sync(dev->dev); 858 } 859 } 860 drm_modeset_unlock(&crtc->mutex); 861 } 862 863 #define SYNC_LOST_COUNT_LIMIT 50 864 865 irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc) 866 { 867 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 868 struct drm_device *dev = crtc->dev; 869 struct tilcdc_drm_private *priv = dev->dev_private; 870 uint32_t stat, reg; 871 872 stat = tilcdc_read_irqstatus(dev); 873 tilcdc_clear_irqstatus(dev, stat); 874 875 if (stat & LCDC_END_OF_FRAME0) { 876 unsigned long flags; 877 bool skip_event = false; 878 ktime_t now; 879 880 now = ktime_get(); 881 882 spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags); 883 884 tilcdc_crtc->last_vblank = now; 885 886 if (tilcdc_crtc->next_fb) { 887 set_scanout(crtc, tilcdc_crtc->next_fb); 888 tilcdc_crtc->next_fb = NULL; 889 skip_event = true; 890 } 891 892 spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags); 893 894 drm_crtc_handle_vblank(crtc); 895 896 if (!skip_event) { 897 struct drm_pending_vblank_event *event; 898 899 spin_lock_irqsave(&dev->event_lock, flags); 900 901 event = tilcdc_crtc->event; 902 tilcdc_crtc->event = NULL; 903 if (event) 904 drm_crtc_send_vblank_event(crtc, event); 905 906 spin_unlock_irqrestore(&dev->event_lock, flags); 907 } 908 909 if (tilcdc_crtc->frame_intact) 910 tilcdc_crtc->sync_lost_count = 0; 911 else 912 tilcdc_crtc->frame_intact = true; 913 } 914 915 if (stat & LCDC_FIFO_UNDERFLOW) 916 dev_err_ratelimited(dev->dev, "%s(0x%08x): FIFO underflow", 917 __func__, stat); 918 919 if (stat & LCDC_PL_LOAD_DONE) { 920 complete(&tilcdc_crtc->palette_loaded); 921 if (priv->rev == 1) 922 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, 923 LCDC_V1_PL_INT_ENA); 924 else 925 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG, 926 LCDC_V2_PL_INT_ENA); 927 } 928 929 if (stat & LCDC_SYNC_LOST) { 930 dev_err_ratelimited(dev->dev, "%s(0x%08x): Sync lost", 931 __func__, stat); 932 tilcdc_crtc->frame_intact = false; 933 if (priv->rev == 1) { 934 reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG); 935 if (reg & LCDC_RASTER_ENABLE) { 936 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, 937 LCDC_RASTER_ENABLE); 938 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, 939 LCDC_RASTER_ENABLE); 940 } 941 } else { 942 if (tilcdc_crtc->sync_lost_count++ > 943 SYNC_LOST_COUNT_LIMIT) { 944 dev_err(dev->dev, 945 "%s(0x%08x): Sync lost flood detected, recovering", 946 __func__, stat); 947 queue_work(system_wq, 948 &tilcdc_crtc->recover_work); 949 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG, 950 LCDC_SYNC_LOST); 951 tilcdc_crtc->sync_lost_count = 0; 952 } 953 } 954 } 955 956 if (stat & LCDC_FRAME_DONE) { 957 tilcdc_crtc->frame_done = true; 958 wake_up(&tilcdc_crtc->frame_done_wq); 959 /* rev 1 lcdc appears to hang if irq is not disbaled here */ 960 if (priv->rev == 1) 961 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, 962 LCDC_V1_FRAME_DONE_INT_ENA); 963 } 964 965 /* For revision 2 only */ 966 if (priv->rev == 2) { 967 /* Indicate to LCDC that the interrupt service routine has 968 * completed, see 13.3.6.1.6 in AM335x TRM. 969 */ 970 tilcdc_write(dev, LCDC_END_OF_INT_IND_REG, 0); 971 } 972 973 return IRQ_HANDLED; 974 } 975 976 int tilcdc_crtc_create(struct drm_device *dev) 977 { 978 struct tilcdc_drm_private *priv = dev->dev_private; 979 struct tilcdc_crtc *tilcdc_crtc; 980 struct drm_crtc *crtc; 981 int ret; 982 983 tilcdc_crtc = devm_kzalloc(dev->dev, sizeof(*tilcdc_crtc), GFP_KERNEL); 984 if (!tilcdc_crtc) 985 return -ENOMEM; 986 987 init_completion(&tilcdc_crtc->palette_loaded); 988 tilcdc_crtc->palette_base = dmam_alloc_coherent(dev->dev, 989 TILCDC_PALETTE_SIZE, 990 &tilcdc_crtc->palette_dma_handle, 991 GFP_KERNEL | __GFP_ZERO); 992 if (!tilcdc_crtc->palette_base) 993 return -ENOMEM; 994 *tilcdc_crtc->palette_base = TILCDC_PALETTE_FIRST_ENTRY; 995 996 crtc = &tilcdc_crtc->base; 997 998 ret = tilcdc_plane_init(dev, &tilcdc_crtc->primary); 999 if (ret < 0) 1000 goto fail; 1001 1002 mutex_init(&tilcdc_crtc->enable_lock); 1003 1004 init_waitqueue_head(&tilcdc_crtc->frame_done_wq); 1005 1006 spin_lock_init(&tilcdc_crtc->irq_lock); 1007 INIT_WORK(&tilcdc_crtc->recover_work, tilcdc_crtc_recover_work); 1008 1009 ret = drm_crtc_init_with_planes(dev, crtc, 1010 &tilcdc_crtc->primary, 1011 NULL, 1012 &tilcdc_crtc_funcs, 1013 "tilcdc crtc"); 1014 if (ret < 0) 1015 goto fail; 1016 1017 drm_crtc_helper_add(crtc, &tilcdc_crtc_helper_funcs); 1018 1019 if (priv->is_componentized) { 1020 crtc->port = of_graph_get_port_by_id(dev->dev->of_node, 0); 1021 if (!crtc->port) { /* This should never happen */ 1022 dev_err(dev->dev, "Port node not found in %pOF\n", 1023 dev->dev->of_node); 1024 ret = -EINVAL; 1025 goto fail; 1026 } 1027 } 1028 1029 priv->crtc = crtc; 1030 return 0; 1031 1032 fail: 1033 tilcdc_crtc_destroy(crtc); 1034 return ret; 1035 } 1036