1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ 4 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> 5 */ 6 7 #include <drm/drm_atomic.h> 8 #include <drm/drm_atomic_helper.h> 9 #include <drm/drm_bridge.h> 10 #include <drm/drm_gem_framebuffer_helper.h> 11 #include <drm/drm_of.h> 12 #include <drm/drm_panel.h> 13 #include <drm/drm_vblank.h> 14 15 #include "tidss_crtc.h" 16 #include "tidss_dispc.h" 17 #include "tidss_drv.h" 18 #include "tidss_encoder.h" 19 #include "tidss_kms.h" 20 #include "tidss_plane.h" 21 22 static void tidss_atomic_commit_tail(struct drm_atomic_state *old_state) 23 { 24 struct drm_device *ddev = old_state->dev; 25 struct tidss_device *tidss = to_tidss(ddev); 26 27 tidss_runtime_get(tidss); 28 29 drm_atomic_helper_commit_modeset_disables(ddev, old_state); 30 drm_atomic_helper_commit_planes(ddev, old_state, DRM_PLANE_COMMIT_ACTIVE_ONLY); 31 drm_atomic_helper_commit_modeset_enables(ddev, old_state); 32 33 drm_atomic_helper_commit_hw_done(old_state); 34 drm_atomic_helper_wait_for_flip_done(ddev, old_state); 35 36 drm_atomic_helper_cleanup_planes(ddev, old_state); 37 38 tidss_runtime_put(tidss); 39 } 40 41 static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = { 42 .atomic_commit_tail = tidss_atomic_commit_tail, 43 }; 44 45 static int tidss_atomic_check(struct drm_device *ddev, 46 struct drm_atomic_state *state) 47 { 48 struct drm_plane_state *opstate; 49 struct drm_plane_state *npstate; 50 struct drm_plane *plane; 51 struct drm_crtc_state *cstate; 52 struct drm_crtc *crtc; 53 int ret, i; 54 55 ret = drm_atomic_helper_check(ddev, state); 56 if (ret) 57 return ret; 58 59 /* 60 * Add all active planes on a CRTC to the atomic state, if 61 * x/y/z position or activity of any plane on that CRTC 62 * changes. This is needed for updating the plane positions in 63 * tidss_crtc_position_planes() which is called from 64 * crtc_atomic_enable() and crtc_atomic_flush(). We have an 65 * extra flag to mark x,y-position changes and together 66 * with zpos_changed the condition recognizes all the above 67 * cases. 68 */ 69 for_each_oldnew_plane_in_state(state, plane, opstate, npstate, i) { 70 if (!npstate->crtc || !npstate->visible) 71 continue; 72 73 if (!opstate->crtc || opstate->crtc_x != npstate->crtc_x || 74 opstate->crtc_y != npstate->crtc_y) { 75 cstate = drm_atomic_get_crtc_state(state, 76 npstate->crtc); 77 if (IS_ERR(cstate)) 78 return PTR_ERR(cstate); 79 to_tidss_crtc_state(cstate)->plane_pos_changed = true; 80 } 81 } 82 83 for_each_new_crtc_in_state(state, crtc, cstate, i) { 84 if (to_tidss_crtc_state(cstate)->plane_pos_changed || 85 cstate->zpos_changed) { 86 ret = drm_atomic_add_affected_planes(state, crtc); 87 if (ret) 88 return ret; 89 } 90 } 91 92 return 0; 93 } 94 95 static const struct drm_mode_config_funcs mode_config_funcs = { 96 .fb_create = drm_gem_fb_create, 97 .atomic_check = tidss_atomic_check, 98 .atomic_commit = drm_atomic_helper_commit, 99 }; 100 101 static int tidss_dispc_modeset_init(struct tidss_device *tidss) 102 { 103 struct device *dev = tidss->dev; 104 unsigned int fourccs_len; 105 const u32 *fourccs = dispc_plane_formats(tidss->dispc, &fourccs_len); 106 unsigned int i; 107 108 struct pipe { 109 u32 hw_videoport; 110 struct drm_bridge *bridge; 111 u32 enc_type; 112 }; 113 114 const struct dispc_features *feat = tidss->feat; 115 u32 max_vps = feat->num_vps; 116 u32 max_planes = feat->num_vids; 117 118 struct pipe pipes[TIDSS_MAX_PORTS]; 119 u32 num_pipes = 0; 120 u32 crtc_mask; 121 122 /* first find all the connected panels & bridges */ 123 124 for (i = 0; i < max_vps; i++) { 125 struct drm_panel *panel; 126 struct drm_bridge *bridge; 127 u32 enc_type = DRM_MODE_ENCODER_NONE; 128 int ret; 129 130 ret = drm_of_find_panel_or_bridge(dev->of_node, i, 0, 131 &panel, &bridge); 132 if (ret == -ENODEV) { 133 dev_dbg(dev, "no panel/bridge for port %d\n", i); 134 continue; 135 } else if (ret) { 136 return dev_err_probe(dev, ret, "port %d probe failed\n", i); 137 } 138 139 if (panel) { 140 u32 conn_type; 141 142 dev_dbg(dev, "Setting up panel for port %d\n", i); 143 144 switch (feat->vp_bus_type[i]) { 145 case DISPC_VP_OLDI_AM65X: 146 enc_type = DRM_MODE_ENCODER_LVDS; 147 conn_type = DRM_MODE_CONNECTOR_LVDS; 148 break; 149 case DISPC_VP_DPI: 150 enc_type = DRM_MODE_ENCODER_DPI; 151 conn_type = DRM_MODE_CONNECTOR_DPI; 152 break; 153 default: 154 WARN_ON(1); 155 return -EINVAL; 156 } 157 158 if (panel->connector_type != conn_type) { 159 dev_err(dev, 160 "%s: Panel %s has incompatible connector type for vp%d (%d != %d)\n", 161 __func__, dev_name(panel->dev), i, 162 panel->connector_type, conn_type); 163 return -EINVAL; 164 } 165 166 bridge = devm_drm_panel_bridge_add(dev, panel); 167 if (IS_ERR(bridge)) { 168 dev_err(dev, 169 "failed to set up panel bridge for port %d\n", 170 i); 171 return PTR_ERR(bridge); 172 } 173 } 174 175 pipes[num_pipes].hw_videoport = i; 176 pipes[num_pipes].bridge = bridge; 177 pipes[num_pipes].enc_type = enc_type; 178 num_pipes++; 179 } 180 181 /* all planes can be on any crtc */ 182 crtc_mask = (1 << num_pipes) - 1; 183 184 /* then create a plane, a crtc and an encoder for each panel/bridge */ 185 186 for (i = 0; i < num_pipes; ++i) { 187 struct tidss_plane *tplane; 188 struct tidss_crtc *tcrtc; 189 u32 hw_plane_id = feat->vid_order[tidss->num_planes]; 190 int ret; 191 192 tplane = tidss_plane_create(tidss, hw_plane_id, 193 DRM_PLANE_TYPE_PRIMARY, crtc_mask, 194 fourccs, fourccs_len); 195 if (IS_ERR(tplane)) { 196 dev_err(tidss->dev, "plane create failed\n"); 197 return PTR_ERR(tplane); 198 } 199 200 tidss->planes[tidss->num_planes++] = &tplane->plane; 201 202 tcrtc = tidss_crtc_create(tidss, pipes[i].hw_videoport, 203 &tplane->plane); 204 if (IS_ERR(tcrtc)) { 205 dev_err(tidss->dev, "crtc create failed\n"); 206 return PTR_ERR(tcrtc); 207 } 208 209 tidss->crtcs[tidss->num_crtcs++] = &tcrtc->crtc; 210 211 ret = tidss_encoder_create(tidss, pipes[i].bridge, 212 pipes[i].enc_type, 213 1 << tcrtc->crtc.index); 214 if (ret) { 215 dev_err(tidss->dev, "encoder create failed\n"); 216 return ret; 217 } 218 } 219 220 /* create overlay planes of the leftover planes */ 221 222 while (tidss->num_planes < max_planes) { 223 struct tidss_plane *tplane; 224 u32 hw_plane_id = feat->vid_order[tidss->num_planes]; 225 226 tplane = tidss_plane_create(tidss, hw_plane_id, 227 DRM_PLANE_TYPE_OVERLAY, crtc_mask, 228 fourccs, fourccs_len); 229 230 if (IS_ERR(tplane)) { 231 dev_err(tidss->dev, "plane create failed\n"); 232 return PTR_ERR(tplane); 233 } 234 235 tidss->planes[tidss->num_planes++] = &tplane->plane; 236 } 237 238 return 0; 239 } 240 241 int tidss_modeset_init(struct tidss_device *tidss) 242 { 243 struct drm_device *ddev = &tidss->ddev; 244 int ret; 245 246 ret = drmm_mode_config_init(ddev); 247 if (ret) 248 return ret; 249 250 ddev->mode_config.min_width = 8; 251 ddev->mode_config.min_height = 8; 252 ddev->mode_config.max_width = 8096; 253 ddev->mode_config.max_height = 8096; 254 ddev->mode_config.normalize_zpos = true; 255 ddev->mode_config.funcs = &mode_config_funcs; 256 ddev->mode_config.helper_private = &mode_config_helper_funcs; 257 258 ret = tidss_dispc_modeset_init(tidss); 259 if (ret) 260 return ret; 261 262 ret = drm_vblank_init(ddev, tidss->num_crtcs); 263 if (ret) 264 return ret; 265 266 drm_mode_config_reset(ddev); 267 268 dev_dbg(tidss->dev, "%s done\n", __func__); 269 270 return 0; 271 } 272