1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ 4 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> 5 */ 6 7 #ifndef __TIDSS_DISPC_H__ 8 #define __TIDSS_DISPC_H__ 9 10 #include "tidss_drv.h" 11 12 struct dispc_device; 13 14 struct drm_crtc_state; 15 16 enum tidss_gamma_type { TIDSS_GAMMA_8BIT, TIDSS_GAMMA_10BIT }; 17 18 struct tidss_vp_feat { 19 struct tidss_vp_color_feat { 20 u32 gamma_size; 21 enum tidss_gamma_type gamma_type; 22 bool has_ctm; 23 } color; 24 }; 25 26 struct tidss_plane_feat { 27 struct tidss_plane_color_feat { 28 u32 encodings; 29 u32 ranges; 30 enum drm_color_encoding default_encoding; 31 enum drm_color_range default_range; 32 } color; 33 struct tidss_plane_blend_feat { 34 bool global_alpha; 35 } blend; 36 }; 37 38 struct dispc_features_scaling { 39 u32 in_width_max_5tap_rgb; 40 u32 in_width_max_3tap_rgb; 41 u32 in_width_max_5tap_yuv; 42 u32 in_width_max_3tap_yuv; 43 u32 upscale_limit; 44 u32 downscale_limit_5tap; 45 u32 downscale_limit_3tap; 46 u32 xinc_max; 47 }; 48 49 struct dispc_vid_info { 50 const char *name; /* Should match dt reg names */ 51 u32 hw_id; 52 bool is_lite; 53 }; 54 55 struct dispc_errata { 56 bool i2000; /* DSS Does Not Support YUV Pixel Data Formats */ 57 }; 58 59 enum dispc_vp_bus_type { 60 DISPC_VP_DPI, /* DPI output */ 61 DISPC_VP_OLDI, /* OLDI (LVDS) output */ 62 DISPC_VP_INTERNAL, /* SoC internal routing */ 63 DISPC_VP_TIED_OFF, /* Tied off / Unavailable */ 64 DISPC_VP_MAX_BUS_TYPE, 65 }; 66 67 enum dispc_dss_subrevision { 68 DISPC_K2G, 69 DISPC_AM625, 70 DISPC_AM62L, 71 DISPC_AM62A7, 72 DISPC_AM65X, 73 DISPC_J721E, 74 }; 75 76 struct dispc_features { 77 int min_pclk_khz; 78 int max_pclk_khz[DISPC_VP_MAX_BUS_TYPE]; 79 80 struct dispc_features_scaling scaling; 81 82 enum dispc_dss_subrevision subrev; 83 84 const char *common; 85 const u16 *common_regs; 86 u32 num_vps; 87 const char *vp_name[TIDSS_MAX_PORTS]; /* Should match dt reg names */ 88 const char *ovr_name[TIDSS_MAX_PORTS]; /* Should match dt reg names */ 89 const char *vpclk_name[TIDSS_MAX_PORTS]; /* Should match dt clk names */ 90 const enum dispc_vp_bus_type vp_bus_type[TIDSS_MAX_PORTS]; 91 struct tidss_vp_feat vp_feat; 92 u32 num_vids; 93 struct dispc_vid_info vid_info[TIDSS_MAX_PLANES]; 94 u32 vid_order[TIDSS_MAX_PLANES]; 95 }; 96 97 extern const struct dispc_features dispc_k2g_feats; 98 extern const struct dispc_features dispc_am625_feats; 99 extern const struct dispc_features dispc_am62a7_feats; 100 extern const struct dispc_features dispc_am62l_feats; 101 extern const struct dispc_features dispc_am65x_feats; 102 extern const struct dispc_features dispc_j721e_feats; 103 104 void dispc_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask); 105 dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc_device *dispc); 106 107 void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane, 108 u32 hw_videoport, u32 x, u32 y, u32 layer); 109 void dispc_ovr_enable_layer(struct dispc_device *dispc, 110 u32 hw_videoport, u32 layer, bool enable); 111 112 void dispc_vp_prepare(struct dispc_device *dispc, u32 hw_videoport, 113 const struct drm_crtc_state *state); 114 void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport, 115 const struct drm_crtc_state *state); 116 void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport); 117 void dispc_vp_unprepare(struct dispc_device *dispc, u32 hw_videoport); 118 bool dispc_vp_go_busy(struct dispc_device *dispc, u32 hw_videoport); 119 void dispc_vp_go(struct dispc_device *dispc, u32 hw_videoport); 120 int dispc_vp_bus_check(struct dispc_device *dispc, u32 hw_videoport, 121 const struct drm_crtc_state *state); 122 enum drm_mode_status dispc_vp_mode_valid(struct dispc_device *dispc, 123 u32 hw_videoport, 124 const struct drm_display_mode *mode); 125 int dispc_vp_enable_clk(struct dispc_device *dispc, u32 hw_videoport); 126 void dispc_vp_disable_clk(struct dispc_device *dispc, u32 hw_videoport); 127 int dispc_vp_set_clk_rate(struct dispc_device *dispc, u32 hw_videoport, 128 unsigned long rate); 129 void dispc_vp_setup(struct dispc_device *dispc, u32 hw_videoport, 130 const struct drm_crtc_state *state, bool newmodeset); 131 132 int dispc_runtime_suspend(struct dispc_device *dispc); 133 int dispc_runtime_resume(struct dispc_device *dispc); 134 135 int dispc_plane_check(struct dispc_device *dispc, u32 hw_plane, 136 const struct drm_plane_state *state, 137 u32 hw_videoport); 138 void dispc_plane_setup(struct dispc_device *dispc, u32 hw_plane, 139 const struct drm_plane_state *state, 140 u32 hw_videoport); 141 void dispc_plane_enable(struct dispc_device *dispc, u32 hw_plane, bool enable); 142 const u32 *dispc_plane_formats(struct dispc_device *dispc, unsigned int *len); 143 144 int dispc_init(struct tidss_device *tidss); 145 void dispc_remove(struct tidss_device *tidss); 146 147 #endif 148