1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2015, NVIDIA Corporation. 4 */ 5 6 #ifndef TEGRA_VIC_H 7 #define TEGRA_VIC_H 8 9 /* VIC methods */ 10 11 #define VIC_SET_FCE_UCODE_SIZE 0x0000071C 12 #define VIC_SET_FCE_UCODE_OFFSET 0x0000072C 13 14 /* VIC registers */ 15 16 #define VIC_THI_STREAMID0 0x00000030 17 #define VIC_THI_STREAMID1 0x00000034 18 19 #define NV_PVIC_MISC_PRI_VIC_CG 0x000016d0 20 #define CG_IDLE_CG_DLY_CNT(val) ((val & 0x3f) << 0) 21 #define CG_IDLE_CG_EN (1 << 6) 22 #define CG_WAKEUP_DLY_CNT(val) ((val & 0xf) << 16) 23 24 #define TRANSCFG_ATT(i, v) (((v) & 0x3) << ((i) * 4)) 25 #define TRANSCFG_SID_HW 0 26 #define TRANSCFG_SID_PHY 1 27 #define TRANSCFG_SID_FALCON 2 28 29 /* Firmware offsets */ 30 31 #define VIC_UCODE_FCE_HEADER_OFFSET (6*4) 32 #define VIC_UCODE_FCE_DATA_OFFSET (7*4) 33 #define FCE_UCODE_SIZE_OFFSET (2*4) 34 35 #endif /* TEGRA_VIC_H */ 36