1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 20ae797a8SArto Merilainen /* 30ae797a8SArto Merilainen * Copyright (c) 2015, NVIDIA Corporation. 40ae797a8SArto Merilainen */ 50ae797a8SArto Merilainen 60ae797a8SArto Merilainen #include <linux/clk.h> 7eb1df694SSam Ravnborg #include <linux/delay.h> 85566174cSRobin Murphy #include <linux/dma-mapping.h> 90ae797a8SArto Merilainen #include <linux/host1x.h> 100ae797a8SArto Merilainen #include <linux/iommu.h> 110ae797a8SArto Merilainen #include <linux/module.h> 120ae797a8SArto Merilainen #include <linux/of.h> 130ae797a8SArto Merilainen #include <linux/of_device.h> 140ae797a8SArto Merilainen #include <linux/of_platform.h> 150ae797a8SArto Merilainen #include <linux/platform_device.h> 160ae797a8SArto Merilainen #include <linux/pm_runtime.h> 170ae797a8SArto Merilainen #include <linux/reset.h> 180ae797a8SArto Merilainen 190ae797a8SArto Merilainen #include <soc/tegra/pmc.h> 200ae797a8SArto Merilainen 210ae797a8SArto Merilainen #include "drm.h" 220ae797a8SArto Merilainen #include "falcon.h" 230ae797a8SArto Merilainen #include "vic.h" 240ae797a8SArto Merilainen 250ae797a8SArto Merilainen struct vic_config { 260ae797a8SArto Merilainen const char *firmware; 27acae8a9dSThierry Reding unsigned int version; 28f3779cb1SThierry Reding bool supports_sid; 290ae797a8SArto Merilainen }; 300ae797a8SArto Merilainen 310ae797a8SArto Merilainen struct vic { 320ae797a8SArto Merilainen struct falcon falcon; 330ae797a8SArto Merilainen 340ae797a8SArto Merilainen void __iomem *regs; 350ae797a8SArto Merilainen struct tegra_drm_client client; 360ae797a8SArto Merilainen struct host1x_channel *channel; 370ae797a8SArto Merilainen struct device *dev; 380ae797a8SArto Merilainen struct clk *clk; 390dc34e19SThierry Reding struct reset_control *rst; 400ae797a8SArto Merilainen 41bf0297acSMikko Perttunen bool can_use_context; 42bf0297acSMikko Perttunen 430ae797a8SArto Merilainen /* Platform configuration */ 440ae797a8SArto Merilainen const struct vic_config *config; 450ae797a8SArto Merilainen }; 460ae797a8SArto Merilainen 470ae797a8SArto Merilainen static inline struct vic *to_vic(struct tegra_drm_client *client) 480ae797a8SArto Merilainen { 490ae797a8SArto Merilainen return container_of(client, struct vic, client); 500ae797a8SArto Merilainen } 510ae797a8SArto Merilainen 520ae797a8SArto Merilainen static void vic_writel(struct vic *vic, u32 value, unsigned int offset) 530ae797a8SArto Merilainen { 540ae797a8SArto Merilainen writel(value, vic->regs + offset); 550ae797a8SArto Merilainen } 560ae797a8SArto Merilainen 570ae797a8SArto Merilainen static int vic_boot(struct vic *vic) 580ae797a8SArto Merilainen { 59*b50ad38dSThierry Reding u32 fce_ucode_size, fce_bin_data_offset, stream_id; 600ae797a8SArto Merilainen void *hdr; 610ae797a8SArto Merilainen int err = 0; 620ae797a8SArto Merilainen 63*b50ad38dSThierry Reding if (vic->config->supports_sid && tegra_dev_iommu_get_stream_id(vic->dev, &stream_id)) { 64f3779cb1SThierry Reding u32 value; 65f3779cb1SThierry Reding 66f3779cb1SThierry Reding value = TRANSCFG_ATT(1, TRANSCFG_SID_FALCON) | 67f3779cb1SThierry Reding TRANSCFG_ATT(0, TRANSCFG_SID_HW); 68f3779cb1SThierry Reding vic_writel(vic, value, VIC_TFBIF_TRANSCFG); 69f3779cb1SThierry Reding 7059e520a6SMikko Perttunen /* 71*b50ad38dSThierry Reding * STREAMID0 is used for input/output buffers. Initialize it to SID_VIC in case 72*b50ad38dSThierry Reding * context isolation is not enabled, and SID_VIC is used for both firmware and 73*b50ad38dSThierry Reding * data buffers. 7459e520a6SMikko Perttunen * 75*b50ad38dSThierry Reding * If context isolation is enabled, it will be overridden by the SETSTREAMID 76*b50ad38dSThierry Reding * opcode as part of each job. 7759e520a6SMikko Perttunen */ 78*b50ad38dSThierry Reding vic_writel(vic, stream_id, VIC_THI_STREAMID0); 7959e520a6SMikko Perttunen 8059e520a6SMikko Perttunen /* STREAMID1 is used for firmware loading. */ 81*b50ad38dSThierry Reding vic_writel(vic, stream_id, VIC_THI_STREAMID1); 82f3779cb1SThierry Reding } 83f3779cb1SThierry Reding 840ae797a8SArto Merilainen /* setup clockgating registers */ 850ae797a8SArto Merilainen vic_writel(vic, CG_IDLE_CG_DLY_CNT(4) | 860ae797a8SArto Merilainen CG_IDLE_CG_EN | 870ae797a8SArto Merilainen CG_WAKEUP_DLY_CNT(4), 880ae797a8SArto Merilainen NV_PVIC_MISC_PRI_VIC_CG); 890ae797a8SArto Merilainen 900ae797a8SArto Merilainen err = falcon_boot(&vic->falcon); 910ae797a8SArto Merilainen if (err < 0) 920ae797a8SArto Merilainen return err; 930ae797a8SArto Merilainen 94d972d624SThierry Reding hdr = vic->falcon.firmware.virt; 950ae797a8SArto Merilainen fce_bin_data_offset = *(u32 *)(hdr + VIC_UCODE_FCE_DATA_OFFSET); 9658ef3aebSMikko Perttunen 9758ef3aebSMikko Perttunen /* Old VIC firmware needs kernel help with setting up FCE microcode. */ 9858ef3aebSMikko Perttunen if (fce_bin_data_offset != 0x0 && fce_bin_data_offset != 0xa5a5a5a5) { 99d972d624SThierry Reding hdr = vic->falcon.firmware.virt + 1000ae797a8SArto Merilainen *(u32 *)(hdr + VIC_UCODE_FCE_HEADER_OFFSET); 1010ae797a8SArto Merilainen fce_ucode_size = *(u32 *)(hdr + FCE_UCODE_SIZE_OFFSET); 1020ae797a8SArto Merilainen 1030ae797a8SArto Merilainen falcon_execute_method(&vic->falcon, VIC_SET_FCE_UCODE_SIZE, 1040ae797a8SArto Merilainen fce_ucode_size); 10558ef3aebSMikko Perttunen falcon_execute_method( 10658ef3aebSMikko Perttunen &vic->falcon, VIC_SET_FCE_UCODE_OFFSET, 10758ef3aebSMikko Perttunen (vic->falcon.firmware.iova + fce_bin_data_offset) >> 8); 10858ef3aebSMikko Perttunen } 1090ae797a8SArto Merilainen 1100ae797a8SArto Merilainen err = falcon_wait_idle(&vic->falcon); 1110ae797a8SArto Merilainen if (err < 0) { 1120ae797a8SArto Merilainen dev_err(vic->dev, 1130ae797a8SArto Merilainen "failed to set application ID and FCE base\n"); 1140ae797a8SArto Merilainen return err; 1150ae797a8SArto Merilainen } 1160ae797a8SArto Merilainen 1170ae797a8SArto Merilainen return 0; 1180ae797a8SArto Merilainen } 1190ae797a8SArto Merilainen 1200ae797a8SArto Merilainen static int vic_init(struct host1x_client *client) 1210ae797a8SArto Merilainen { 1220ae797a8SArto Merilainen struct tegra_drm_client *drm = host1x_to_drm_client(client); 123608f43adSThierry Reding struct drm_device *dev = dev_get_drvdata(client->host); 1240ae797a8SArto Merilainen struct tegra_drm *tegra = dev->dev_private; 1250ae797a8SArto Merilainen struct vic *vic = to_vic(drm); 1260ae797a8SArto Merilainen int err; 1270ae797a8SArto Merilainen 1287edd7961SThierry Reding err = host1x_client_iommu_attach(client); 129a8817489SThierry Reding if (err < 0 && err != -ENODEV) { 1307baa943eSThierry Reding dev_err(vic->dev, "failed to attach to domain: %d\n", err); 1310ae797a8SArto Merilainen return err; 1320ae797a8SArto Merilainen } 1330ae797a8SArto Merilainen 134caccddcfSThierry Reding vic->channel = host1x_channel_request(client); 1350ae797a8SArto Merilainen if (!vic->channel) { 1360ae797a8SArto Merilainen err = -ENOMEM; 137bc8828bdSThierry Reding goto detach; 1380ae797a8SArto Merilainen } 1390ae797a8SArto Merilainen 140617dd7ccSThierry Reding client->syncpts[0] = host1x_syncpt_request(client, 0); 1410ae797a8SArto Merilainen if (!client->syncpts[0]) { 1420ae797a8SArto Merilainen err = -ENOMEM; 1430ae797a8SArto Merilainen goto free_channel; 1440ae797a8SArto Merilainen } 1450ae797a8SArto Merilainen 1461e15f5b9SDmitry Osipenko pm_runtime_enable(client->dev); 1471e15f5b9SDmitry Osipenko pm_runtime_use_autosuspend(client->dev); 1481e15f5b9SDmitry Osipenko pm_runtime_set_autosuspend_delay(client->dev, 500); 1491e15f5b9SDmitry Osipenko 1500ae797a8SArto Merilainen err = tegra_drm_register_client(tegra, drm); 1510ae797a8SArto Merilainen if (err < 0) 1521e15f5b9SDmitry Osipenko goto disable_rpm; 1530ae797a8SArto Merilainen 15447b15779SThierry Reding /* 15547b15779SThierry Reding * Inherit the DMA parameters (such as maximum segment size) from the 156608f43adSThierry Reding * parent host1x device. 15747b15779SThierry Reding */ 158608f43adSThierry Reding client->dev->dma_parms = client->host->dma_parms; 15947b15779SThierry Reding 1600ae797a8SArto Merilainen return 0; 1610ae797a8SArto Merilainen 1621e15f5b9SDmitry Osipenko disable_rpm: 1631e15f5b9SDmitry Osipenko pm_runtime_dont_use_autosuspend(client->dev); 1641e15f5b9SDmitry Osipenko pm_runtime_force_suspend(client->dev); 1651e15f5b9SDmitry Osipenko 1662aed4f5aSMikko Perttunen host1x_syncpt_put(client->syncpts[0]); 1670ae797a8SArto Merilainen free_channel: 1688474b025SMikko Perttunen host1x_channel_put(vic->channel); 169bc8828bdSThierry Reding detach: 170aacdf198SThierry Reding host1x_client_iommu_detach(client); 1710ae797a8SArto Merilainen 1720ae797a8SArto Merilainen return err; 1730ae797a8SArto Merilainen } 1740ae797a8SArto Merilainen 1750ae797a8SArto Merilainen static int vic_exit(struct host1x_client *client) 1760ae797a8SArto Merilainen { 1770ae797a8SArto Merilainen struct tegra_drm_client *drm = host1x_to_drm_client(client); 178608f43adSThierry Reding struct drm_device *dev = dev_get_drvdata(client->host); 1790ae797a8SArto Merilainen struct tegra_drm *tegra = dev->dev_private; 1800ae797a8SArto Merilainen struct vic *vic = to_vic(drm); 1810ae797a8SArto Merilainen int err; 1820ae797a8SArto Merilainen 18347b15779SThierry Reding /* avoid a dangling pointer just in case this disappears */ 18447b15779SThierry Reding client->dev->dma_parms = NULL; 18547b15779SThierry Reding 1860ae797a8SArto Merilainen err = tegra_drm_unregister_client(tegra, drm); 1870ae797a8SArto Merilainen if (err < 0) 1880ae797a8SArto Merilainen return err; 1890ae797a8SArto Merilainen 1901e15f5b9SDmitry Osipenko pm_runtime_dont_use_autosuspend(client->dev); 1911e15f5b9SDmitry Osipenko pm_runtime_force_suspend(client->dev); 1921e15f5b9SDmitry Osipenko 1932aed4f5aSMikko Perttunen host1x_syncpt_put(client->syncpts[0]); 1948474b025SMikko Perttunen host1x_channel_put(vic->channel); 195aacdf198SThierry Reding host1x_client_iommu_detach(client); 1960ae797a8SArto Merilainen 1971e15f5b9SDmitry Osipenko vic->channel = NULL; 1981e15f5b9SDmitry Osipenko 199d972d624SThierry Reding if (client->group) { 200d972d624SThierry Reding dma_unmap_single(vic->dev, vic->falcon.firmware.phys, 201d972d624SThierry Reding vic->falcon.firmware.size, DMA_TO_DEVICE); 20220e7dce2SThierry Reding tegra_drm_free(tegra, vic->falcon.firmware.size, 203d972d624SThierry Reding vic->falcon.firmware.virt, 204d972d624SThierry Reding vic->falcon.firmware.iova); 205d972d624SThierry Reding } else { 20620e7dce2SThierry Reding dma_free_coherent(vic->dev, vic->falcon.firmware.size, 207d972d624SThierry Reding vic->falcon.firmware.virt, 208d972d624SThierry Reding vic->falcon.firmware.iova); 209d972d624SThierry Reding } 21020e7dce2SThierry Reding 2110ae797a8SArto Merilainen return 0; 2120ae797a8SArto Merilainen } 2130ae797a8SArto Merilainen 2140ae797a8SArto Merilainen static const struct host1x_client_ops vic_client_ops = { 2150ae797a8SArto Merilainen .init = vic_init, 2160ae797a8SArto Merilainen .exit = vic_exit, 2170ae797a8SArto Merilainen }; 2180ae797a8SArto Merilainen 21977a0b09dSThierry Reding static int vic_load_firmware(struct vic *vic) 22077a0b09dSThierry Reding { 22120e7dce2SThierry Reding struct host1x_client *client = &vic->client.base; 22220e7dce2SThierry Reding struct tegra_drm *tegra = vic->client.drm; 223bf0297acSMikko Perttunen static DEFINE_MUTEX(lock); 224bf0297acSMikko Perttunen u32 fce_bin_data_offset; 225d972d624SThierry Reding dma_addr_t iova; 22620e7dce2SThierry Reding size_t size; 22720e7dce2SThierry Reding void *virt; 22877a0b09dSThierry Reding int err; 22977a0b09dSThierry Reding 230bf0297acSMikko Perttunen mutex_lock(&lock); 231bf0297acSMikko Perttunen 232bf0297acSMikko Perttunen if (vic->falcon.firmware.virt) { 233bf0297acSMikko Perttunen err = 0; 234bf0297acSMikko Perttunen goto unlock; 235bf0297acSMikko Perttunen } 23677a0b09dSThierry Reding 23777a0b09dSThierry Reding err = falcon_read_firmware(&vic->falcon, vic->config->firmware); 23877a0b09dSThierry Reding if (err < 0) 239bf0297acSMikko Perttunen goto unlock; 24020e7dce2SThierry Reding 24120e7dce2SThierry Reding size = vic->falcon.firmware.size; 24220e7dce2SThierry Reding 24320e7dce2SThierry Reding if (!client->group) { 244d972d624SThierry Reding virt = dma_alloc_coherent(vic->dev, size, &iova, GFP_KERNEL); 245bf0297acSMikko Perttunen if (!virt) { 246bf0297acSMikko Perttunen err = -ENOMEM; 247bf0297acSMikko Perttunen goto unlock; 248bf0297acSMikko Perttunen } 24920e7dce2SThierry Reding } else { 250d972d624SThierry Reding virt = tegra_drm_alloc(tegra, size, &iova); 251bf0297acSMikko Perttunen if (IS_ERR(virt)) { 252bf0297acSMikko Perttunen err = PTR_ERR(virt); 253bf0297acSMikko Perttunen goto unlock; 254bf0297acSMikko Perttunen } 25520e7dce2SThierry Reding } 25620e7dce2SThierry Reding 257d972d624SThierry Reding vic->falcon.firmware.virt = virt; 258d972d624SThierry Reding vic->falcon.firmware.iova = iova; 25977a0b09dSThierry Reding 26077a0b09dSThierry Reding err = falcon_load_firmware(&vic->falcon); 26177a0b09dSThierry Reding if (err < 0) 26277a0b09dSThierry Reding goto cleanup; 26377a0b09dSThierry Reding 26420e7dce2SThierry Reding /* 26520e7dce2SThierry Reding * In this case we have received an IOVA from the shared domain, so we 26620e7dce2SThierry Reding * need to make sure to get the physical address so that the DMA API 26720e7dce2SThierry Reding * knows what memory pages to flush the cache for. 26820e7dce2SThierry Reding */ 26920e7dce2SThierry Reding if (client->group) { 270d972d624SThierry Reding dma_addr_t phys; 271d972d624SThierry Reding 27220e7dce2SThierry Reding phys = dma_map_single(vic->dev, virt, size, DMA_TO_DEVICE); 27320e7dce2SThierry Reding 27420e7dce2SThierry Reding err = dma_mapping_error(vic->dev, phys); 27520e7dce2SThierry Reding if (err < 0) 27620e7dce2SThierry Reding goto cleanup; 27720e7dce2SThierry Reding 278d972d624SThierry Reding vic->falcon.firmware.phys = phys; 27920e7dce2SThierry Reding } 28020e7dce2SThierry Reding 281bf0297acSMikko Perttunen /* 282bf0297acSMikko Perttunen * Check if firmware is new enough to not require mapping firmware 283bf0297acSMikko Perttunen * to data buffer domains. 284bf0297acSMikko Perttunen */ 285bf0297acSMikko Perttunen fce_bin_data_offset = *(u32 *)(virt + VIC_UCODE_FCE_DATA_OFFSET); 286bf0297acSMikko Perttunen 287bf0297acSMikko Perttunen if (!vic->config->supports_sid) { 288bf0297acSMikko Perttunen vic->can_use_context = false; 289bf0297acSMikko Perttunen } else if (fce_bin_data_offset != 0x0 && fce_bin_data_offset != 0xa5a5a5a5) { 290bf0297acSMikko Perttunen /* 291bf0297acSMikko Perttunen * Firmware will access FCE through STREAMID0, so context 292bf0297acSMikko Perttunen * isolation cannot be used. 293bf0297acSMikko Perttunen */ 294bf0297acSMikko Perttunen vic->can_use_context = false; 295bf0297acSMikko Perttunen dev_warn_once(vic->dev, "context isolation disabled due to old firmware\n"); 296bf0297acSMikko Perttunen } else { 297bf0297acSMikko Perttunen vic->can_use_context = true; 298bf0297acSMikko Perttunen } 299bf0297acSMikko Perttunen 300bf0297acSMikko Perttunen unlock: 301bf0297acSMikko Perttunen mutex_unlock(&lock); 302bf0297acSMikko Perttunen return err; 30377a0b09dSThierry Reding 30477a0b09dSThierry Reding cleanup: 30520e7dce2SThierry Reding if (!client->group) 306d972d624SThierry Reding dma_free_coherent(vic->dev, size, virt, iova); 30720e7dce2SThierry Reding else 308d972d624SThierry Reding tegra_drm_free(tegra, size, virt, iova); 30920e7dce2SThierry Reding 310bf0297acSMikko Perttunen mutex_unlock(&lock); 31177a0b09dSThierry Reding return err; 31277a0b09dSThierry Reding } 31377a0b09dSThierry Reding 31499166123SMikko Perttunen 315b5d5288aSYueHaibing static int __maybe_unused vic_runtime_resume(struct device *dev) 31699166123SMikko Perttunen { 31799166123SMikko Perttunen struct vic *vic = dev_get_drvdata(dev); 31899166123SMikko Perttunen int err; 31999166123SMikko Perttunen 32099166123SMikko Perttunen err = clk_prepare_enable(vic->clk); 32199166123SMikko Perttunen if (err < 0) 32299166123SMikko Perttunen return err; 32399166123SMikko Perttunen 32499166123SMikko Perttunen usleep_range(10, 20); 32599166123SMikko Perttunen 32699166123SMikko Perttunen err = reset_control_deassert(vic->rst); 32799166123SMikko Perttunen if (err < 0) 32899166123SMikko Perttunen goto disable; 32999166123SMikko Perttunen 33099166123SMikko Perttunen usleep_range(10, 20); 33199166123SMikko Perttunen 33299166123SMikko Perttunen err = vic_load_firmware(vic); 33399166123SMikko Perttunen if (err < 0) 33499166123SMikko Perttunen goto assert; 33599166123SMikko Perttunen 33699166123SMikko Perttunen err = vic_boot(vic); 33799166123SMikko Perttunen if (err < 0) 33899166123SMikko Perttunen goto assert; 33999166123SMikko Perttunen 34099166123SMikko Perttunen return 0; 34199166123SMikko Perttunen 34299166123SMikko Perttunen assert: 34399166123SMikko Perttunen reset_control_assert(vic->rst); 34499166123SMikko Perttunen disable: 34599166123SMikko Perttunen clk_disable_unprepare(vic->clk); 34699166123SMikko Perttunen return err; 34799166123SMikko Perttunen } 34899166123SMikko Perttunen 349b5d5288aSYueHaibing static int __maybe_unused vic_runtime_suspend(struct device *dev) 35099166123SMikko Perttunen { 35199166123SMikko Perttunen struct vic *vic = dev_get_drvdata(dev); 35299166123SMikko Perttunen int err; 35399166123SMikko Perttunen 3541e15f5b9SDmitry Osipenko host1x_channel_stop(vic->channel); 3551e15f5b9SDmitry Osipenko 35699166123SMikko Perttunen err = reset_control_assert(vic->rst); 35799166123SMikko Perttunen if (err < 0) 35899166123SMikko Perttunen return err; 35999166123SMikko Perttunen 36099166123SMikko Perttunen usleep_range(2000, 4000); 36199166123SMikko Perttunen 36299166123SMikko Perttunen clk_disable_unprepare(vic->clk); 36399166123SMikko Perttunen 36499166123SMikko Perttunen return 0; 36599166123SMikko Perttunen } 36699166123SMikko Perttunen 3670ae797a8SArto Merilainen static int vic_open_channel(struct tegra_drm_client *client, 3680ae797a8SArto Merilainen struct tegra_drm_context *context) 3690ae797a8SArto Merilainen { 3700ae797a8SArto Merilainen struct vic *vic = to_vic(client); 3710ae797a8SArto Merilainen 3720ae797a8SArto Merilainen context->channel = host1x_channel_get(vic->channel); 37358ed47adSDmitry Osipenko if (!context->channel) 37499166123SMikko Perttunen return -ENOMEM; 3750ae797a8SArto Merilainen 3760ae797a8SArto Merilainen return 0; 3770ae797a8SArto Merilainen } 3780ae797a8SArto Merilainen 3790ae797a8SArto Merilainen static void vic_close_channel(struct tegra_drm_context *context) 3800ae797a8SArto Merilainen { 3810ae797a8SArto Merilainen host1x_channel_put(context->channel); 3820ae797a8SArto Merilainen } 3830ae797a8SArto Merilainen 384bf0297acSMikko Perttunen static int vic_can_use_memory_ctx(struct tegra_drm_client *client, bool *supported) 385bf0297acSMikko Perttunen { 386bf0297acSMikko Perttunen struct vic *vic = to_vic(client); 387bf0297acSMikko Perttunen int err; 388bf0297acSMikko Perttunen 389bf0297acSMikko Perttunen /* This doesn't access HW so it's safe to call without powering up. */ 390bf0297acSMikko Perttunen err = vic_load_firmware(vic); 391bf0297acSMikko Perttunen if (err < 0) 392bf0297acSMikko Perttunen return err; 393bf0297acSMikko Perttunen 394bf0297acSMikko Perttunen *supported = vic->can_use_context; 395bf0297acSMikko Perttunen 396bf0297acSMikko Perttunen return 0; 397bf0297acSMikko Perttunen } 398bf0297acSMikko Perttunen 3990ae797a8SArto Merilainen static const struct tegra_drm_client_ops vic_ops = { 4000ae797a8SArto Merilainen .open_channel = vic_open_channel, 4010ae797a8SArto Merilainen .close_channel = vic_close_channel, 4020ae797a8SArto Merilainen .submit = tegra_drm_submit, 403bf0297acSMikko Perttunen .get_streamid_offset = tegra_drm_get_streamid_offset_thi, 404bf0297acSMikko Perttunen .can_use_memory_ctx = vic_can_use_memory_ctx, 4050ae797a8SArto Merilainen }; 4060ae797a8SArto Merilainen 407788ff4b6SNicolas Chauvet #define NVIDIA_TEGRA_124_VIC_FIRMWARE "nvidia/tegra124/vic03_ucode.bin" 408788ff4b6SNicolas Chauvet 4090ae797a8SArto Merilainen static const struct vic_config vic_t124_config = { 410788ff4b6SNicolas Chauvet .firmware = NVIDIA_TEGRA_124_VIC_FIRMWARE, 411acae8a9dSThierry Reding .version = 0x40, 412f3779cb1SThierry Reding .supports_sid = false, 4130ae797a8SArto Merilainen }; 4140ae797a8SArto Merilainen 415788ff4b6SNicolas Chauvet #define NVIDIA_TEGRA_210_VIC_FIRMWARE "nvidia/tegra210/vic04_ucode.bin" 416788ff4b6SNicolas Chauvet 4170ae797a8SArto Merilainen static const struct vic_config vic_t210_config = { 418788ff4b6SNicolas Chauvet .firmware = NVIDIA_TEGRA_210_VIC_FIRMWARE, 419acae8a9dSThierry Reding .version = 0x21, 420f3779cb1SThierry Reding .supports_sid = false, 4210ae797a8SArto Merilainen }; 4220ae797a8SArto Merilainen 4236e44b9adSMikko Perttunen #define NVIDIA_TEGRA_186_VIC_FIRMWARE "nvidia/tegra186/vic04_ucode.bin" 4246e44b9adSMikko Perttunen 4256e44b9adSMikko Perttunen static const struct vic_config vic_t186_config = { 4266e44b9adSMikko Perttunen .firmware = NVIDIA_TEGRA_186_VIC_FIRMWARE, 427acae8a9dSThierry Reding .version = 0x18, 428f3779cb1SThierry Reding .supports_sid = true, 4296e44b9adSMikko Perttunen }; 4306e44b9adSMikko Perttunen 431d6b9bc02SThierry Reding #define NVIDIA_TEGRA_194_VIC_FIRMWARE "nvidia/tegra194/vic.bin" 432d6b9bc02SThierry Reding 433d6b9bc02SThierry Reding static const struct vic_config vic_t194_config = { 434d6b9bc02SThierry Reding .firmware = NVIDIA_TEGRA_194_VIC_FIRMWARE, 435d6b9bc02SThierry Reding .version = 0x19, 436f3779cb1SThierry Reding .supports_sid = true, 437d6b9bc02SThierry Reding }; 438d6b9bc02SThierry Reding 4399550669cSMikko Perttunen #define NVIDIA_TEGRA_234_VIC_FIRMWARE "nvidia/tegra234/vic.bin" 4409550669cSMikko Perttunen 4419550669cSMikko Perttunen static const struct vic_config vic_t234_config = { 4429550669cSMikko Perttunen .firmware = NVIDIA_TEGRA_234_VIC_FIRMWARE, 4439550669cSMikko Perttunen .version = 0x23, 4449550669cSMikko Perttunen .supports_sid = true, 4459550669cSMikko Perttunen }; 4469550669cSMikko Perttunen 44782d73874SThierry Reding static const struct of_device_id tegra_vic_of_match[] = { 4480ae797a8SArto Merilainen { .compatible = "nvidia,tegra124-vic", .data = &vic_t124_config }, 4490ae797a8SArto Merilainen { .compatible = "nvidia,tegra210-vic", .data = &vic_t210_config }, 4506e44b9adSMikko Perttunen { .compatible = "nvidia,tegra186-vic", .data = &vic_t186_config }, 451d6b9bc02SThierry Reding { .compatible = "nvidia,tegra194-vic", .data = &vic_t194_config }, 4529550669cSMikko Perttunen { .compatible = "nvidia,tegra234-vic", .data = &vic_t234_config }, 4530ae797a8SArto Merilainen { }, 4540ae797a8SArto Merilainen }; 45582d73874SThierry Reding MODULE_DEVICE_TABLE(of, tegra_vic_of_match); 4560ae797a8SArto Merilainen 4570ae797a8SArto Merilainen static int vic_probe(struct platform_device *pdev) 4580ae797a8SArto Merilainen { 4590ae797a8SArto Merilainen struct device *dev = &pdev->dev; 4600ae797a8SArto Merilainen struct host1x_syncpt **syncpts; 4610ae797a8SArto Merilainen struct vic *vic; 4620ae797a8SArto Merilainen int err; 4630ae797a8SArto Merilainen 464d5ad0e3dSThierry Reding /* inherit DMA mask from host1x parent */ 465d5ad0e3dSThierry Reding err = dma_coerce_mask_and_coherent(dev, *dev->parent->dma_mask); 466d5ad0e3dSThierry Reding if (err < 0) { 467d5ad0e3dSThierry Reding dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err); 468d5ad0e3dSThierry Reding return err; 469d5ad0e3dSThierry Reding } 470d5ad0e3dSThierry Reding 4710ae797a8SArto Merilainen vic = devm_kzalloc(dev, sizeof(*vic), GFP_KERNEL); 4720ae797a8SArto Merilainen if (!vic) 4730ae797a8SArto Merilainen return -ENOMEM; 4740ae797a8SArto Merilainen 475829ce7a6SThierry Reding vic->config = of_device_get_match_data(dev); 476829ce7a6SThierry Reding 4770ae797a8SArto Merilainen syncpts = devm_kzalloc(dev, sizeof(*syncpts), GFP_KERNEL); 4780ae797a8SArto Merilainen if (!syncpts) 4790ae797a8SArto Merilainen return -ENOMEM; 4800ae797a8SArto Merilainen 481135f4c55SLv Ruyi vic->regs = devm_platform_ioremap_resource(pdev, 0); 4820ae797a8SArto Merilainen if (IS_ERR(vic->regs)) 4830ae797a8SArto Merilainen return PTR_ERR(vic->regs); 4840ae797a8SArto Merilainen 4850ae797a8SArto Merilainen vic->clk = devm_clk_get(dev, NULL); 4860ae797a8SArto Merilainen if (IS_ERR(vic->clk)) { 4870ae797a8SArto Merilainen dev_err(&pdev->dev, "failed to get clock\n"); 4880ae797a8SArto Merilainen return PTR_ERR(vic->clk); 4890ae797a8SArto Merilainen } 4900ae797a8SArto Merilainen 491e97a951fSMikko Perttunen err = clk_set_rate(vic->clk, ULONG_MAX); 492e97a951fSMikko Perttunen if (err < 0) { 493e97a951fSMikko Perttunen dev_err(&pdev->dev, "failed to set clock rate\n"); 494e97a951fSMikko Perttunen return err; 495e97a951fSMikko Perttunen } 496e97a951fSMikko Perttunen 4970dc34e19SThierry Reding if (!dev->pm_domain) { 4980dc34e19SThierry Reding vic->rst = devm_reset_control_get(dev, "vic"); 4990dc34e19SThierry Reding if (IS_ERR(vic->rst)) { 5000dc34e19SThierry Reding dev_err(&pdev->dev, "failed to get reset\n"); 5010dc34e19SThierry Reding return PTR_ERR(vic->rst); 5020dc34e19SThierry Reding } 5030dc34e19SThierry Reding } 5040dc34e19SThierry Reding 5050ae797a8SArto Merilainen vic->falcon.dev = dev; 5060ae797a8SArto Merilainen vic->falcon.regs = vic->regs; 5070ae797a8SArto Merilainen 5080ae797a8SArto Merilainen err = falcon_init(&vic->falcon); 5090ae797a8SArto Merilainen if (err < 0) 5100ae797a8SArto Merilainen return err; 5110ae797a8SArto Merilainen 5120ae797a8SArto Merilainen platform_set_drvdata(pdev, vic); 5130ae797a8SArto Merilainen 5140ae797a8SArto Merilainen INIT_LIST_HEAD(&vic->client.base.list); 5150ae797a8SArto Merilainen vic->client.base.ops = &vic_client_ops; 5160ae797a8SArto Merilainen vic->client.base.dev = dev; 5170ae797a8SArto Merilainen vic->client.base.class = HOST1X_CLASS_VIC; 5180ae797a8SArto Merilainen vic->client.base.syncpts = syncpts; 5190ae797a8SArto Merilainen vic->client.base.num_syncpts = 1; 5200ae797a8SArto Merilainen vic->dev = dev; 5210ae797a8SArto Merilainen 5220ae797a8SArto Merilainen INIT_LIST_HEAD(&vic->client.list); 523acae8a9dSThierry Reding vic->client.version = vic->config->version; 5240ae797a8SArto Merilainen vic->client.ops = &vic_ops; 5250ae797a8SArto Merilainen 5260ae797a8SArto Merilainen err = host1x_client_register(&vic->client.base); 5270ae797a8SArto Merilainen if (err < 0) { 5280ae797a8SArto Merilainen dev_err(dev, "failed to register host1x client: %d\n", err); 5290ae797a8SArto Merilainen goto exit_falcon; 5300ae797a8SArto Merilainen } 5310ae797a8SArto Merilainen 5320ae797a8SArto Merilainen return 0; 5330ae797a8SArto Merilainen 5340ae797a8SArto Merilainen exit_falcon: 5350ae797a8SArto Merilainen falcon_exit(&vic->falcon); 5360ae797a8SArto Merilainen 5370ae797a8SArto Merilainen return err; 5380ae797a8SArto Merilainen } 5390ae797a8SArto Merilainen 5400ae797a8SArto Merilainen static int vic_remove(struct platform_device *pdev) 5410ae797a8SArto Merilainen { 5420ae797a8SArto Merilainen struct vic *vic = platform_get_drvdata(pdev); 5430ae797a8SArto Merilainen int err; 5440ae797a8SArto Merilainen 5450ae797a8SArto Merilainen err = host1x_client_unregister(&vic->client.base); 5460ae797a8SArto Merilainen if (err < 0) { 5470ae797a8SArto Merilainen dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", 5480ae797a8SArto Merilainen err); 5490ae797a8SArto Merilainen return err; 5500ae797a8SArto Merilainen } 5510ae797a8SArto Merilainen 5520ae797a8SArto Merilainen falcon_exit(&vic->falcon); 5530ae797a8SArto Merilainen 5540ae797a8SArto Merilainen return 0; 5550ae797a8SArto Merilainen } 5560ae797a8SArto Merilainen 5570ae797a8SArto Merilainen static const struct dev_pm_ops vic_pm_ops = { 55842457494SArnd Bergmann RUNTIME_PM_OPS(vic_runtime_suspend, vic_runtime_resume, NULL) 55942457494SArnd Bergmann SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 5600ae797a8SArto Merilainen }; 5610ae797a8SArto Merilainen 5620ae797a8SArto Merilainen struct platform_driver tegra_vic_driver = { 5630ae797a8SArto Merilainen .driver = { 5640ae797a8SArto Merilainen .name = "tegra-vic", 56582d73874SThierry Reding .of_match_table = tegra_vic_of_match, 5660ae797a8SArto Merilainen .pm = &vic_pm_ops 5670ae797a8SArto Merilainen }, 5680ae797a8SArto Merilainen .probe = vic_probe, 5690ae797a8SArto Merilainen .remove = vic_remove, 5700ae797a8SArto Merilainen }; 571788ff4b6SNicolas Chauvet 572788ff4b6SNicolas Chauvet #if IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC) 573788ff4b6SNicolas Chauvet MODULE_FIRMWARE(NVIDIA_TEGRA_124_VIC_FIRMWARE); 574788ff4b6SNicolas Chauvet #endif 575788ff4b6SNicolas Chauvet #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) 576788ff4b6SNicolas Chauvet MODULE_FIRMWARE(NVIDIA_TEGRA_210_VIC_FIRMWARE); 577788ff4b6SNicolas Chauvet #endif 5786e44b9adSMikko Perttunen #if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC) 5796e44b9adSMikko Perttunen MODULE_FIRMWARE(NVIDIA_TEGRA_186_VIC_FIRMWARE); 5806e44b9adSMikko Perttunen #endif 581d6b9bc02SThierry Reding #if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) 582d6b9bc02SThierry Reding MODULE_FIRMWARE(NVIDIA_TEGRA_194_VIC_FIRMWARE); 583d6b9bc02SThierry Reding #endif 5849550669cSMikko Perttunen #if IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC) 5859550669cSMikko Perttunen MODULE_FIRMWARE(NVIDIA_TEGRA_234_VIC_FIRMWARE); 5869550669cSMikko Perttunen #endif 587