1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 20ae797a8SArto Merilainen /* 30ae797a8SArto Merilainen * Copyright (c) 2015, NVIDIA Corporation. 40ae797a8SArto Merilainen */ 50ae797a8SArto Merilainen 60ae797a8SArto Merilainen #include <linux/clk.h> 7eb1df694SSam Ravnborg #include <linux/delay.h> 80ae797a8SArto Merilainen #include <linux/host1x.h> 90ae797a8SArto Merilainen #include <linux/iommu.h> 100ae797a8SArto Merilainen #include <linux/module.h> 110ae797a8SArto Merilainen #include <linux/of.h> 120ae797a8SArto Merilainen #include <linux/of_device.h> 130ae797a8SArto Merilainen #include <linux/of_platform.h> 140ae797a8SArto Merilainen #include <linux/platform_device.h> 150ae797a8SArto Merilainen #include <linux/pm_runtime.h> 160ae797a8SArto Merilainen #include <linux/reset.h> 170ae797a8SArto Merilainen 180ae797a8SArto Merilainen #include <soc/tegra/pmc.h> 190ae797a8SArto Merilainen 200ae797a8SArto Merilainen #include "drm.h" 210ae797a8SArto Merilainen #include "falcon.h" 220ae797a8SArto Merilainen #include "vic.h" 230ae797a8SArto Merilainen 240ae797a8SArto Merilainen struct vic_config { 250ae797a8SArto Merilainen const char *firmware; 26acae8a9dSThierry Reding unsigned int version; 27f3779cb1SThierry Reding bool supports_sid; 280ae797a8SArto Merilainen }; 290ae797a8SArto Merilainen 300ae797a8SArto Merilainen struct vic { 310ae797a8SArto Merilainen struct falcon falcon; 320ae797a8SArto Merilainen bool booted; 330ae797a8SArto Merilainen 340ae797a8SArto Merilainen void __iomem *regs; 350ae797a8SArto Merilainen struct tegra_drm_client client; 360ae797a8SArto Merilainen struct host1x_channel *channel; 37*7baa943eSThierry Reding struct iommu_group *group; 380ae797a8SArto Merilainen struct device *dev; 390ae797a8SArto Merilainen struct clk *clk; 400dc34e19SThierry Reding struct reset_control *rst; 410ae797a8SArto Merilainen 420ae797a8SArto Merilainen /* Platform configuration */ 430ae797a8SArto Merilainen const struct vic_config *config; 440ae797a8SArto Merilainen }; 450ae797a8SArto Merilainen 460ae797a8SArto Merilainen static inline struct vic *to_vic(struct tegra_drm_client *client) 470ae797a8SArto Merilainen { 480ae797a8SArto Merilainen return container_of(client, struct vic, client); 490ae797a8SArto Merilainen } 500ae797a8SArto Merilainen 510ae797a8SArto Merilainen static void vic_writel(struct vic *vic, u32 value, unsigned int offset) 520ae797a8SArto Merilainen { 530ae797a8SArto Merilainen writel(value, vic->regs + offset); 540ae797a8SArto Merilainen } 550ae797a8SArto Merilainen 560ae797a8SArto Merilainen static int vic_runtime_resume(struct device *dev) 570ae797a8SArto Merilainen { 580ae797a8SArto Merilainen struct vic *vic = dev_get_drvdata(dev); 590dc34e19SThierry Reding int err; 600ae797a8SArto Merilainen 610dc34e19SThierry Reding err = clk_prepare_enable(vic->clk); 620dc34e19SThierry Reding if (err < 0) 630dc34e19SThierry Reding return err; 640dc34e19SThierry Reding 650dc34e19SThierry Reding usleep_range(10, 20); 660dc34e19SThierry Reding 670dc34e19SThierry Reding err = reset_control_deassert(vic->rst); 680dc34e19SThierry Reding if (err < 0) 690dc34e19SThierry Reding goto disable; 700dc34e19SThierry Reding 710dc34e19SThierry Reding usleep_range(10, 20); 720dc34e19SThierry Reding 730dc34e19SThierry Reding return 0; 740dc34e19SThierry Reding 750dc34e19SThierry Reding disable: 760dc34e19SThierry Reding clk_disable_unprepare(vic->clk); 770dc34e19SThierry Reding return err; 780ae797a8SArto Merilainen } 790ae797a8SArto Merilainen 800ae797a8SArto Merilainen static int vic_runtime_suspend(struct device *dev) 810ae797a8SArto Merilainen { 820ae797a8SArto Merilainen struct vic *vic = dev_get_drvdata(dev); 830dc34e19SThierry Reding int err; 840dc34e19SThierry Reding 850dc34e19SThierry Reding err = reset_control_assert(vic->rst); 860dc34e19SThierry Reding if (err < 0) 870dc34e19SThierry Reding return err; 880dc34e19SThierry Reding 890dc34e19SThierry Reding usleep_range(2000, 4000); 900ae797a8SArto Merilainen 910ae797a8SArto Merilainen clk_disable_unprepare(vic->clk); 920ae797a8SArto Merilainen 930ae797a8SArto Merilainen vic->booted = false; 940ae797a8SArto Merilainen 950ae797a8SArto Merilainen return 0; 960ae797a8SArto Merilainen } 970ae797a8SArto Merilainen 980ae797a8SArto Merilainen static int vic_boot(struct vic *vic) 990ae797a8SArto Merilainen { 100dd631e8aSThierry Reding #ifdef CONFIG_IOMMU_API 101dd631e8aSThierry Reding struct iommu_fwspec *spec = dev_iommu_fwspec_get(vic->dev); 102dd631e8aSThierry Reding #endif 1030ae797a8SArto Merilainen u32 fce_ucode_size, fce_bin_data_offset; 1040ae797a8SArto Merilainen void *hdr; 1050ae797a8SArto Merilainen int err = 0; 1060ae797a8SArto Merilainen 1070ae797a8SArto Merilainen if (vic->booted) 1080ae797a8SArto Merilainen return 0; 1090ae797a8SArto Merilainen 110509869a2SAnders Roxell #ifdef CONFIG_IOMMU_API 111dd631e8aSThierry Reding if (vic->config->supports_sid && spec) { 112f3779cb1SThierry Reding u32 value; 113f3779cb1SThierry Reding 114f3779cb1SThierry Reding value = TRANSCFG_ATT(1, TRANSCFG_SID_FALCON) | 115f3779cb1SThierry Reding TRANSCFG_ATT(0, TRANSCFG_SID_HW); 116f3779cb1SThierry Reding vic_writel(vic, value, VIC_TFBIF_TRANSCFG); 117f3779cb1SThierry Reding 118dd631e8aSThierry Reding if (spec->num_ids > 0) { 119f3779cb1SThierry Reding value = spec->ids[0] & 0xffff; 120f3779cb1SThierry Reding 121f3779cb1SThierry Reding vic_writel(vic, value, VIC_THI_STREAMID0); 122f3779cb1SThierry Reding vic_writel(vic, value, VIC_THI_STREAMID1); 123f3779cb1SThierry Reding } 124f3779cb1SThierry Reding } 125509869a2SAnders Roxell #endif 126f3779cb1SThierry Reding 1270ae797a8SArto Merilainen /* setup clockgating registers */ 1280ae797a8SArto Merilainen vic_writel(vic, CG_IDLE_CG_DLY_CNT(4) | 1290ae797a8SArto Merilainen CG_IDLE_CG_EN | 1300ae797a8SArto Merilainen CG_WAKEUP_DLY_CNT(4), 1310ae797a8SArto Merilainen NV_PVIC_MISC_PRI_VIC_CG); 1320ae797a8SArto Merilainen 1330ae797a8SArto Merilainen err = falcon_boot(&vic->falcon); 1340ae797a8SArto Merilainen if (err < 0) 1350ae797a8SArto Merilainen return err; 1360ae797a8SArto Merilainen 1370ae797a8SArto Merilainen hdr = vic->falcon.firmware.vaddr; 1380ae797a8SArto Merilainen fce_bin_data_offset = *(u32 *)(hdr + VIC_UCODE_FCE_DATA_OFFSET); 1390ae797a8SArto Merilainen hdr = vic->falcon.firmware.vaddr + 1400ae797a8SArto Merilainen *(u32 *)(hdr + VIC_UCODE_FCE_HEADER_OFFSET); 1410ae797a8SArto Merilainen fce_ucode_size = *(u32 *)(hdr + FCE_UCODE_SIZE_OFFSET); 1420ae797a8SArto Merilainen 1430ae797a8SArto Merilainen falcon_execute_method(&vic->falcon, VIC_SET_APPLICATION_ID, 1); 1440ae797a8SArto Merilainen falcon_execute_method(&vic->falcon, VIC_SET_FCE_UCODE_SIZE, 1450ae797a8SArto Merilainen fce_ucode_size); 1460ae797a8SArto Merilainen falcon_execute_method(&vic->falcon, VIC_SET_FCE_UCODE_OFFSET, 1470ae797a8SArto Merilainen (vic->falcon.firmware.paddr + fce_bin_data_offset) 1480ae797a8SArto Merilainen >> 8); 1490ae797a8SArto Merilainen 1500ae797a8SArto Merilainen err = falcon_wait_idle(&vic->falcon); 1510ae797a8SArto Merilainen if (err < 0) { 1520ae797a8SArto Merilainen dev_err(vic->dev, 1530ae797a8SArto Merilainen "failed to set application ID and FCE base\n"); 1540ae797a8SArto Merilainen return err; 1550ae797a8SArto Merilainen } 1560ae797a8SArto Merilainen 1570ae797a8SArto Merilainen vic->booted = true; 1580ae797a8SArto Merilainen 1590ae797a8SArto Merilainen return 0; 1600ae797a8SArto Merilainen } 1610ae797a8SArto Merilainen 1620ae797a8SArto Merilainen static void *vic_falcon_alloc(struct falcon *falcon, size_t size, 1630ae797a8SArto Merilainen dma_addr_t *iova) 1640ae797a8SArto Merilainen { 1650ae797a8SArto Merilainen struct tegra_drm *tegra = falcon->data; 1660ae797a8SArto Merilainen 1670ae797a8SArto Merilainen return tegra_drm_alloc(tegra, size, iova); 1680ae797a8SArto Merilainen } 1690ae797a8SArto Merilainen 1700ae797a8SArto Merilainen static void vic_falcon_free(struct falcon *falcon, size_t size, 1710ae797a8SArto Merilainen dma_addr_t iova, void *va) 1720ae797a8SArto Merilainen { 1730ae797a8SArto Merilainen struct tegra_drm *tegra = falcon->data; 1740ae797a8SArto Merilainen 1750ae797a8SArto Merilainen return tegra_drm_free(tegra, size, va, iova); 1760ae797a8SArto Merilainen } 1770ae797a8SArto Merilainen 1780ae797a8SArto Merilainen static const struct falcon_ops vic_falcon_ops = { 1790ae797a8SArto Merilainen .alloc = vic_falcon_alloc, 1800ae797a8SArto Merilainen .free = vic_falcon_free 1810ae797a8SArto Merilainen }; 1820ae797a8SArto Merilainen 1830ae797a8SArto Merilainen static int vic_init(struct host1x_client *client) 1840ae797a8SArto Merilainen { 1850ae797a8SArto Merilainen struct tegra_drm_client *drm = host1x_to_drm_client(client); 1860ae797a8SArto Merilainen struct drm_device *dev = dev_get_drvdata(client->parent); 1870ae797a8SArto Merilainen struct tegra_drm *tegra = dev->dev_private; 1880ae797a8SArto Merilainen struct vic *vic = to_vic(drm); 1890ae797a8SArto Merilainen int err; 1900ae797a8SArto Merilainen 191*7baa943eSThierry Reding vic->group = host1x_client_iommu_attach(client, false); 192*7baa943eSThierry Reding if (IS_ERR(vic->group)) { 193*7baa943eSThierry Reding err = PTR_ERR(vic->group); 194*7baa943eSThierry Reding dev_err(vic->dev, "failed to attach to domain: %d\n", err); 1950ae797a8SArto Merilainen return err; 1960ae797a8SArto Merilainen } 1970ae797a8SArto Merilainen 198caccddcfSThierry Reding vic->channel = host1x_channel_request(client); 1990ae797a8SArto Merilainen if (!vic->channel) { 2000ae797a8SArto Merilainen err = -ENOMEM; 201bc8828bdSThierry Reding goto detach; 2020ae797a8SArto Merilainen } 2030ae797a8SArto Merilainen 204617dd7ccSThierry Reding client->syncpts[0] = host1x_syncpt_request(client, 0); 2050ae797a8SArto Merilainen if (!client->syncpts[0]) { 2060ae797a8SArto Merilainen err = -ENOMEM; 2070ae797a8SArto Merilainen goto free_channel; 2080ae797a8SArto Merilainen } 2090ae797a8SArto Merilainen 2100ae797a8SArto Merilainen err = tegra_drm_register_client(tegra, drm); 2110ae797a8SArto Merilainen if (err < 0) 2120ae797a8SArto Merilainen goto free_syncpt; 2130ae797a8SArto Merilainen 21447b15779SThierry Reding /* 21547b15779SThierry Reding * Inherit the DMA parameters (such as maximum segment size) from the 21647b15779SThierry Reding * parent device. 21747b15779SThierry Reding */ 21847b15779SThierry Reding client->dev->dma_parms = client->parent->dma_parms; 21947b15779SThierry Reding 2200ae797a8SArto Merilainen return 0; 2210ae797a8SArto Merilainen 2220ae797a8SArto Merilainen free_syncpt: 2230ae797a8SArto Merilainen host1x_syncpt_free(client->syncpts[0]); 2240ae797a8SArto Merilainen free_channel: 2258474b025SMikko Perttunen host1x_channel_put(vic->channel); 226bc8828bdSThierry Reding detach: 227*7baa943eSThierry Reding host1x_client_iommu_detach(client, vic->group); 2280ae797a8SArto Merilainen 2290ae797a8SArto Merilainen return err; 2300ae797a8SArto Merilainen } 2310ae797a8SArto Merilainen 2320ae797a8SArto Merilainen static int vic_exit(struct host1x_client *client) 2330ae797a8SArto Merilainen { 2340ae797a8SArto Merilainen struct tegra_drm_client *drm = host1x_to_drm_client(client); 2350ae797a8SArto Merilainen struct drm_device *dev = dev_get_drvdata(client->parent); 2360ae797a8SArto Merilainen struct tegra_drm *tegra = dev->dev_private; 2370ae797a8SArto Merilainen struct vic *vic = to_vic(drm); 2380ae797a8SArto Merilainen int err; 2390ae797a8SArto Merilainen 24047b15779SThierry Reding /* avoid a dangling pointer just in case this disappears */ 24147b15779SThierry Reding client->dev->dma_parms = NULL; 24247b15779SThierry Reding 2430ae797a8SArto Merilainen err = tegra_drm_unregister_client(tegra, drm); 2440ae797a8SArto Merilainen if (err < 0) 2450ae797a8SArto Merilainen return err; 2460ae797a8SArto Merilainen 2470ae797a8SArto Merilainen host1x_syncpt_free(client->syncpts[0]); 2488474b025SMikko Perttunen host1x_channel_put(vic->channel); 249*7baa943eSThierry Reding host1x_client_iommu_detach(client, vic->group); 2500ae797a8SArto Merilainen 2510ae797a8SArto Merilainen return 0; 2520ae797a8SArto Merilainen } 2530ae797a8SArto Merilainen 2540ae797a8SArto Merilainen static const struct host1x_client_ops vic_client_ops = { 2550ae797a8SArto Merilainen .init = vic_init, 2560ae797a8SArto Merilainen .exit = vic_exit, 2570ae797a8SArto Merilainen }; 2580ae797a8SArto Merilainen 25977a0b09dSThierry Reding static int vic_load_firmware(struct vic *vic) 26077a0b09dSThierry Reding { 26177a0b09dSThierry Reding int err; 26277a0b09dSThierry Reding 26377a0b09dSThierry Reding if (vic->falcon.data) 26477a0b09dSThierry Reding return 0; 26577a0b09dSThierry Reding 26677a0b09dSThierry Reding vic->falcon.data = vic->client.drm; 26777a0b09dSThierry Reding 26877a0b09dSThierry Reding err = falcon_read_firmware(&vic->falcon, vic->config->firmware); 26977a0b09dSThierry Reding if (err < 0) 27077a0b09dSThierry Reding goto cleanup; 27177a0b09dSThierry Reding 27277a0b09dSThierry Reding err = falcon_load_firmware(&vic->falcon); 27377a0b09dSThierry Reding if (err < 0) 27477a0b09dSThierry Reding goto cleanup; 27577a0b09dSThierry Reding 27677a0b09dSThierry Reding return 0; 27777a0b09dSThierry Reding 27877a0b09dSThierry Reding cleanup: 27977a0b09dSThierry Reding vic->falcon.data = NULL; 28077a0b09dSThierry Reding return err; 28177a0b09dSThierry Reding } 28277a0b09dSThierry Reding 2830ae797a8SArto Merilainen static int vic_open_channel(struct tegra_drm_client *client, 2840ae797a8SArto Merilainen struct tegra_drm_context *context) 2850ae797a8SArto Merilainen { 2860ae797a8SArto Merilainen struct vic *vic = to_vic(client); 2870ae797a8SArto Merilainen int err; 2880ae797a8SArto Merilainen 2890ae797a8SArto Merilainen err = pm_runtime_get_sync(vic->dev); 2900ae797a8SArto Merilainen if (err < 0) 2910ae797a8SArto Merilainen return err; 2920ae797a8SArto Merilainen 29377a0b09dSThierry Reding err = vic_load_firmware(vic); 29477a0b09dSThierry Reding if (err < 0) 29577a0b09dSThierry Reding goto rpm_put; 29677a0b09dSThierry Reding 2970ae797a8SArto Merilainen err = vic_boot(vic); 29877a0b09dSThierry Reding if (err < 0) 29977a0b09dSThierry Reding goto rpm_put; 3000ae797a8SArto Merilainen 3010ae797a8SArto Merilainen context->channel = host1x_channel_get(vic->channel); 3020ae797a8SArto Merilainen if (!context->channel) { 30377a0b09dSThierry Reding err = -ENOMEM; 30477a0b09dSThierry Reding goto rpm_put; 3050ae797a8SArto Merilainen } 3060ae797a8SArto Merilainen 3070ae797a8SArto Merilainen return 0; 30877a0b09dSThierry Reding 30977a0b09dSThierry Reding rpm_put: 31077a0b09dSThierry Reding pm_runtime_put(vic->dev); 31177a0b09dSThierry Reding return err; 3120ae797a8SArto Merilainen } 3130ae797a8SArto Merilainen 3140ae797a8SArto Merilainen static void vic_close_channel(struct tegra_drm_context *context) 3150ae797a8SArto Merilainen { 3160ae797a8SArto Merilainen struct vic *vic = to_vic(context->client); 3170ae797a8SArto Merilainen 3180ae797a8SArto Merilainen host1x_channel_put(context->channel); 3190ae797a8SArto Merilainen 3200ae797a8SArto Merilainen pm_runtime_put(vic->dev); 3210ae797a8SArto Merilainen } 3220ae797a8SArto Merilainen 3230ae797a8SArto Merilainen static const struct tegra_drm_client_ops vic_ops = { 3240ae797a8SArto Merilainen .open_channel = vic_open_channel, 3250ae797a8SArto Merilainen .close_channel = vic_close_channel, 3260ae797a8SArto Merilainen .submit = tegra_drm_submit, 3270ae797a8SArto Merilainen }; 3280ae797a8SArto Merilainen 329788ff4b6SNicolas Chauvet #define NVIDIA_TEGRA_124_VIC_FIRMWARE "nvidia/tegra124/vic03_ucode.bin" 330788ff4b6SNicolas Chauvet 3310ae797a8SArto Merilainen static const struct vic_config vic_t124_config = { 332788ff4b6SNicolas Chauvet .firmware = NVIDIA_TEGRA_124_VIC_FIRMWARE, 333acae8a9dSThierry Reding .version = 0x40, 334f3779cb1SThierry Reding .supports_sid = false, 3350ae797a8SArto Merilainen }; 3360ae797a8SArto Merilainen 337788ff4b6SNicolas Chauvet #define NVIDIA_TEGRA_210_VIC_FIRMWARE "nvidia/tegra210/vic04_ucode.bin" 338788ff4b6SNicolas Chauvet 3390ae797a8SArto Merilainen static const struct vic_config vic_t210_config = { 340788ff4b6SNicolas Chauvet .firmware = NVIDIA_TEGRA_210_VIC_FIRMWARE, 341acae8a9dSThierry Reding .version = 0x21, 342f3779cb1SThierry Reding .supports_sid = false, 3430ae797a8SArto Merilainen }; 3440ae797a8SArto Merilainen 3456e44b9adSMikko Perttunen #define NVIDIA_TEGRA_186_VIC_FIRMWARE "nvidia/tegra186/vic04_ucode.bin" 3466e44b9adSMikko Perttunen 3476e44b9adSMikko Perttunen static const struct vic_config vic_t186_config = { 3486e44b9adSMikko Perttunen .firmware = NVIDIA_TEGRA_186_VIC_FIRMWARE, 349acae8a9dSThierry Reding .version = 0x18, 350f3779cb1SThierry Reding .supports_sid = true, 3516e44b9adSMikko Perttunen }; 3526e44b9adSMikko Perttunen 353d6b9bc02SThierry Reding #define NVIDIA_TEGRA_194_VIC_FIRMWARE "nvidia/tegra194/vic.bin" 354d6b9bc02SThierry Reding 355d6b9bc02SThierry Reding static const struct vic_config vic_t194_config = { 356d6b9bc02SThierry Reding .firmware = NVIDIA_TEGRA_194_VIC_FIRMWARE, 357d6b9bc02SThierry Reding .version = 0x19, 358f3779cb1SThierry Reding .supports_sid = true, 359d6b9bc02SThierry Reding }; 360d6b9bc02SThierry Reding 3610ae797a8SArto Merilainen static const struct of_device_id vic_match[] = { 3620ae797a8SArto Merilainen { .compatible = "nvidia,tegra124-vic", .data = &vic_t124_config }, 3630ae797a8SArto Merilainen { .compatible = "nvidia,tegra210-vic", .data = &vic_t210_config }, 3646e44b9adSMikko Perttunen { .compatible = "nvidia,tegra186-vic", .data = &vic_t186_config }, 365d6b9bc02SThierry Reding { .compatible = "nvidia,tegra194-vic", .data = &vic_t194_config }, 3660ae797a8SArto Merilainen { }, 3670ae797a8SArto Merilainen }; 3680ae797a8SArto Merilainen 3690ae797a8SArto Merilainen static int vic_probe(struct platform_device *pdev) 3700ae797a8SArto Merilainen { 3710ae797a8SArto Merilainen struct device *dev = &pdev->dev; 3720ae797a8SArto Merilainen struct host1x_syncpt **syncpts; 3730ae797a8SArto Merilainen struct resource *regs; 3740ae797a8SArto Merilainen struct vic *vic; 3750ae797a8SArto Merilainen int err; 3760ae797a8SArto Merilainen 377d5ad0e3dSThierry Reding /* inherit DMA mask from host1x parent */ 378d5ad0e3dSThierry Reding err = dma_coerce_mask_and_coherent(dev, *dev->parent->dma_mask); 379d5ad0e3dSThierry Reding if (err < 0) { 380d5ad0e3dSThierry Reding dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err); 381d5ad0e3dSThierry Reding return err; 382d5ad0e3dSThierry Reding } 383d5ad0e3dSThierry Reding 3840ae797a8SArto Merilainen vic = devm_kzalloc(dev, sizeof(*vic), GFP_KERNEL); 3850ae797a8SArto Merilainen if (!vic) 3860ae797a8SArto Merilainen return -ENOMEM; 3870ae797a8SArto Merilainen 388829ce7a6SThierry Reding vic->config = of_device_get_match_data(dev); 389829ce7a6SThierry Reding 3900ae797a8SArto Merilainen syncpts = devm_kzalloc(dev, sizeof(*syncpts), GFP_KERNEL); 3910ae797a8SArto Merilainen if (!syncpts) 3920ae797a8SArto Merilainen return -ENOMEM; 3930ae797a8SArto Merilainen 3940ae797a8SArto Merilainen regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3950ae797a8SArto Merilainen if (!regs) { 3960ae797a8SArto Merilainen dev_err(&pdev->dev, "failed to get registers\n"); 3970ae797a8SArto Merilainen return -ENXIO; 3980ae797a8SArto Merilainen } 3990ae797a8SArto Merilainen 4000ae797a8SArto Merilainen vic->regs = devm_ioremap_resource(dev, regs); 4010ae797a8SArto Merilainen if (IS_ERR(vic->regs)) 4020ae797a8SArto Merilainen return PTR_ERR(vic->regs); 4030ae797a8SArto Merilainen 4040ae797a8SArto Merilainen vic->clk = devm_clk_get(dev, NULL); 4050ae797a8SArto Merilainen if (IS_ERR(vic->clk)) { 4060ae797a8SArto Merilainen dev_err(&pdev->dev, "failed to get clock\n"); 4070ae797a8SArto Merilainen return PTR_ERR(vic->clk); 4080ae797a8SArto Merilainen } 4090ae797a8SArto Merilainen 4100dc34e19SThierry Reding if (!dev->pm_domain) { 4110dc34e19SThierry Reding vic->rst = devm_reset_control_get(dev, "vic"); 4120dc34e19SThierry Reding if (IS_ERR(vic->rst)) { 4130dc34e19SThierry Reding dev_err(&pdev->dev, "failed to get reset\n"); 4140dc34e19SThierry Reding return PTR_ERR(vic->rst); 4150dc34e19SThierry Reding } 4160dc34e19SThierry Reding } 4170dc34e19SThierry Reding 4180ae797a8SArto Merilainen vic->falcon.dev = dev; 4190ae797a8SArto Merilainen vic->falcon.regs = vic->regs; 4200ae797a8SArto Merilainen vic->falcon.ops = &vic_falcon_ops; 4210ae797a8SArto Merilainen 4220ae797a8SArto Merilainen err = falcon_init(&vic->falcon); 4230ae797a8SArto Merilainen if (err < 0) 4240ae797a8SArto Merilainen return err; 4250ae797a8SArto Merilainen 4260ae797a8SArto Merilainen platform_set_drvdata(pdev, vic); 4270ae797a8SArto Merilainen 4280ae797a8SArto Merilainen INIT_LIST_HEAD(&vic->client.base.list); 4290ae797a8SArto Merilainen vic->client.base.ops = &vic_client_ops; 4300ae797a8SArto Merilainen vic->client.base.dev = dev; 4310ae797a8SArto Merilainen vic->client.base.class = HOST1X_CLASS_VIC; 4320ae797a8SArto Merilainen vic->client.base.syncpts = syncpts; 4330ae797a8SArto Merilainen vic->client.base.num_syncpts = 1; 4340ae797a8SArto Merilainen vic->dev = dev; 4350ae797a8SArto Merilainen 4360ae797a8SArto Merilainen INIT_LIST_HEAD(&vic->client.list); 437acae8a9dSThierry Reding vic->client.version = vic->config->version; 4380ae797a8SArto Merilainen vic->client.ops = &vic_ops; 4390ae797a8SArto Merilainen 4400ae797a8SArto Merilainen err = host1x_client_register(&vic->client.base); 4410ae797a8SArto Merilainen if (err < 0) { 4420ae797a8SArto Merilainen dev_err(dev, "failed to register host1x client: %d\n", err); 4430ae797a8SArto Merilainen goto exit_falcon; 4440ae797a8SArto Merilainen } 4450ae797a8SArto Merilainen 4460ae797a8SArto Merilainen pm_runtime_enable(&pdev->dev); 4470ae797a8SArto Merilainen if (!pm_runtime_enabled(&pdev->dev)) { 4480ae797a8SArto Merilainen err = vic_runtime_resume(&pdev->dev); 4490ae797a8SArto Merilainen if (err < 0) 4500ae797a8SArto Merilainen goto unregister_client; 4510ae797a8SArto Merilainen } 4520ae797a8SArto Merilainen 4530ae797a8SArto Merilainen return 0; 4540ae797a8SArto Merilainen 4550ae797a8SArto Merilainen unregister_client: 4560ae797a8SArto Merilainen host1x_client_unregister(&vic->client.base); 4570ae797a8SArto Merilainen exit_falcon: 4580ae797a8SArto Merilainen falcon_exit(&vic->falcon); 4590ae797a8SArto Merilainen 4600ae797a8SArto Merilainen return err; 4610ae797a8SArto Merilainen } 4620ae797a8SArto Merilainen 4630ae797a8SArto Merilainen static int vic_remove(struct platform_device *pdev) 4640ae797a8SArto Merilainen { 4650ae797a8SArto Merilainen struct vic *vic = platform_get_drvdata(pdev); 4660ae797a8SArto Merilainen int err; 4670ae797a8SArto Merilainen 4680ae797a8SArto Merilainen err = host1x_client_unregister(&vic->client.base); 4690ae797a8SArto Merilainen if (err < 0) { 4700ae797a8SArto Merilainen dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", 4710ae797a8SArto Merilainen err); 4720ae797a8SArto Merilainen return err; 4730ae797a8SArto Merilainen } 4740ae797a8SArto Merilainen 4750ae797a8SArto Merilainen if (pm_runtime_enabled(&pdev->dev)) 4760ae797a8SArto Merilainen pm_runtime_disable(&pdev->dev); 4770ae797a8SArto Merilainen else 4780ae797a8SArto Merilainen vic_runtime_suspend(&pdev->dev); 4790ae797a8SArto Merilainen 4800ae797a8SArto Merilainen falcon_exit(&vic->falcon); 4810ae797a8SArto Merilainen 4820ae797a8SArto Merilainen return 0; 4830ae797a8SArto Merilainen } 4840ae797a8SArto Merilainen 4850ae797a8SArto Merilainen static const struct dev_pm_ops vic_pm_ops = { 4860ae797a8SArto Merilainen SET_RUNTIME_PM_OPS(vic_runtime_suspend, vic_runtime_resume, NULL) 4870ae797a8SArto Merilainen }; 4880ae797a8SArto Merilainen 4890ae797a8SArto Merilainen struct platform_driver tegra_vic_driver = { 4900ae797a8SArto Merilainen .driver = { 4910ae797a8SArto Merilainen .name = "tegra-vic", 4920ae797a8SArto Merilainen .of_match_table = vic_match, 4930ae797a8SArto Merilainen .pm = &vic_pm_ops 4940ae797a8SArto Merilainen }, 4950ae797a8SArto Merilainen .probe = vic_probe, 4960ae797a8SArto Merilainen .remove = vic_remove, 4970ae797a8SArto Merilainen }; 498788ff4b6SNicolas Chauvet 499788ff4b6SNicolas Chauvet #if IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC) 500788ff4b6SNicolas Chauvet MODULE_FIRMWARE(NVIDIA_TEGRA_124_VIC_FIRMWARE); 501788ff4b6SNicolas Chauvet #endif 502788ff4b6SNicolas Chauvet #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) 503788ff4b6SNicolas Chauvet MODULE_FIRMWARE(NVIDIA_TEGRA_210_VIC_FIRMWARE); 504788ff4b6SNicolas Chauvet #endif 5056e44b9adSMikko Perttunen #if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC) 5066e44b9adSMikko Perttunen MODULE_FIRMWARE(NVIDIA_TEGRA_186_VIC_FIRMWARE); 5076e44b9adSMikko Perttunen #endif 508d6b9bc02SThierry Reding #if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) 509d6b9bc02SThierry Reding MODULE_FIRMWARE(NVIDIA_TEGRA_194_VIC_FIRMWARE); 510d6b9bc02SThierry Reding #endif 511