1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 20ae797a8SArto Merilainen /* 30ae797a8SArto Merilainen * Copyright (c) 2015, NVIDIA Corporation. 40ae797a8SArto Merilainen */ 50ae797a8SArto Merilainen 60ae797a8SArto Merilainen #include <linux/clk.h> 7eb1df694SSam Ravnborg #include <linux/delay.h> 80ae797a8SArto Merilainen #include <linux/host1x.h> 90ae797a8SArto Merilainen #include <linux/iommu.h> 100ae797a8SArto Merilainen #include <linux/module.h> 110ae797a8SArto Merilainen #include <linux/of.h> 120ae797a8SArto Merilainen #include <linux/of_device.h> 130ae797a8SArto Merilainen #include <linux/of_platform.h> 140ae797a8SArto Merilainen #include <linux/platform_device.h> 150ae797a8SArto Merilainen #include <linux/pm_runtime.h> 160ae797a8SArto Merilainen #include <linux/reset.h> 170ae797a8SArto Merilainen 180ae797a8SArto Merilainen #include <soc/tegra/pmc.h> 190ae797a8SArto Merilainen 200ae797a8SArto Merilainen #include "drm.h" 210ae797a8SArto Merilainen #include "falcon.h" 220ae797a8SArto Merilainen #include "vic.h" 230ae797a8SArto Merilainen 240ae797a8SArto Merilainen struct vic_config { 250ae797a8SArto Merilainen const char *firmware; 26acae8a9dSThierry Reding unsigned int version; 27f3779cb1SThierry Reding bool supports_sid; 280ae797a8SArto Merilainen }; 290ae797a8SArto Merilainen 300ae797a8SArto Merilainen struct vic { 310ae797a8SArto Merilainen struct falcon falcon; 320ae797a8SArto Merilainen bool booted; 330ae797a8SArto Merilainen 340ae797a8SArto Merilainen void __iomem *regs; 350ae797a8SArto Merilainen struct tegra_drm_client client; 360ae797a8SArto Merilainen struct host1x_channel *channel; 370ae797a8SArto Merilainen struct device *dev; 380ae797a8SArto Merilainen struct clk *clk; 390dc34e19SThierry Reding struct reset_control *rst; 400ae797a8SArto Merilainen 410ae797a8SArto Merilainen /* Platform configuration */ 420ae797a8SArto Merilainen const struct vic_config *config; 430ae797a8SArto Merilainen }; 440ae797a8SArto Merilainen 450ae797a8SArto Merilainen static inline struct vic *to_vic(struct tegra_drm_client *client) 460ae797a8SArto Merilainen { 470ae797a8SArto Merilainen return container_of(client, struct vic, client); 480ae797a8SArto Merilainen } 490ae797a8SArto Merilainen 500ae797a8SArto Merilainen static void vic_writel(struct vic *vic, u32 value, unsigned int offset) 510ae797a8SArto Merilainen { 520ae797a8SArto Merilainen writel(value, vic->regs + offset); 530ae797a8SArto Merilainen } 540ae797a8SArto Merilainen 550ae797a8SArto Merilainen static int vic_runtime_resume(struct device *dev) 560ae797a8SArto Merilainen { 570ae797a8SArto Merilainen struct vic *vic = dev_get_drvdata(dev); 580dc34e19SThierry Reding int err; 590ae797a8SArto Merilainen 600dc34e19SThierry Reding err = clk_prepare_enable(vic->clk); 610dc34e19SThierry Reding if (err < 0) 620dc34e19SThierry Reding return err; 630dc34e19SThierry Reding 640dc34e19SThierry Reding usleep_range(10, 20); 650dc34e19SThierry Reding 660dc34e19SThierry Reding err = reset_control_deassert(vic->rst); 670dc34e19SThierry Reding if (err < 0) 680dc34e19SThierry Reding goto disable; 690dc34e19SThierry Reding 700dc34e19SThierry Reding usleep_range(10, 20); 710dc34e19SThierry Reding 720dc34e19SThierry Reding return 0; 730dc34e19SThierry Reding 740dc34e19SThierry Reding disable: 750dc34e19SThierry Reding clk_disable_unprepare(vic->clk); 760dc34e19SThierry Reding return err; 770ae797a8SArto Merilainen } 780ae797a8SArto Merilainen 790ae797a8SArto Merilainen static int vic_runtime_suspend(struct device *dev) 800ae797a8SArto Merilainen { 810ae797a8SArto Merilainen struct vic *vic = dev_get_drvdata(dev); 820dc34e19SThierry Reding int err; 830dc34e19SThierry Reding 840dc34e19SThierry Reding err = reset_control_assert(vic->rst); 850dc34e19SThierry Reding if (err < 0) 860dc34e19SThierry Reding return err; 870dc34e19SThierry Reding 880dc34e19SThierry Reding usleep_range(2000, 4000); 890ae797a8SArto Merilainen 900ae797a8SArto Merilainen clk_disable_unprepare(vic->clk); 910ae797a8SArto Merilainen 920ae797a8SArto Merilainen vic->booted = false; 930ae797a8SArto Merilainen 940ae797a8SArto Merilainen return 0; 950ae797a8SArto Merilainen } 960ae797a8SArto Merilainen 970ae797a8SArto Merilainen static int vic_boot(struct vic *vic) 980ae797a8SArto Merilainen { 99dd631e8aSThierry Reding #ifdef CONFIG_IOMMU_API 100dd631e8aSThierry Reding struct iommu_fwspec *spec = dev_iommu_fwspec_get(vic->dev); 101dd631e8aSThierry Reding #endif 1020ae797a8SArto Merilainen u32 fce_ucode_size, fce_bin_data_offset; 1030ae797a8SArto Merilainen void *hdr; 1040ae797a8SArto Merilainen int err = 0; 1050ae797a8SArto Merilainen 1060ae797a8SArto Merilainen if (vic->booted) 1070ae797a8SArto Merilainen return 0; 1080ae797a8SArto Merilainen 109509869a2SAnders Roxell #ifdef CONFIG_IOMMU_API 110dd631e8aSThierry Reding if (vic->config->supports_sid && spec) { 111f3779cb1SThierry Reding u32 value; 112f3779cb1SThierry Reding 113f3779cb1SThierry Reding value = TRANSCFG_ATT(1, TRANSCFG_SID_FALCON) | 114f3779cb1SThierry Reding TRANSCFG_ATT(0, TRANSCFG_SID_HW); 115f3779cb1SThierry Reding vic_writel(vic, value, VIC_TFBIF_TRANSCFG); 116f3779cb1SThierry Reding 117dd631e8aSThierry Reding if (spec->num_ids > 0) { 118f3779cb1SThierry Reding value = spec->ids[0] & 0xffff; 119f3779cb1SThierry Reding 120*59e520a6SMikko Perttunen /* 121*59e520a6SMikko Perttunen * STREAMID0 is used for input/output buffers. 122*59e520a6SMikko Perttunen * Initialize it to SID_VIC in case context isolation 123*59e520a6SMikko Perttunen * is not enabled, and SID_VIC is used for both firmware 124*59e520a6SMikko Perttunen * and data buffers. 125*59e520a6SMikko Perttunen * 126*59e520a6SMikko Perttunen * If context isolation is enabled, it will be 127*59e520a6SMikko Perttunen * overridden by the SETSTREAMID opcode as part of 128*59e520a6SMikko Perttunen * each job. 129*59e520a6SMikko Perttunen */ 130f3779cb1SThierry Reding vic_writel(vic, value, VIC_THI_STREAMID0); 131*59e520a6SMikko Perttunen 132*59e520a6SMikko Perttunen /* STREAMID1 is used for firmware loading. */ 133f3779cb1SThierry Reding vic_writel(vic, value, VIC_THI_STREAMID1); 134f3779cb1SThierry Reding } 135f3779cb1SThierry Reding } 136509869a2SAnders Roxell #endif 137f3779cb1SThierry Reding 1380ae797a8SArto Merilainen /* setup clockgating registers */ 1390ae797a8SArto Merilainen vic_writel(vic, CG_IDLE_CG_DLY_CNT(4) | 1400ae797a8SArto Merilainen CG_IDLE_CG_EN | 1410ae797a8SArto Merilainen CG_WAKEUP_DLY_CNT(4), 1420ae797a8SArto Merilainen NV_PVIC_MISC_PRI_VIC_CG); 1430ae797a8SArto Merilainen 1440ae797a8SArto Merilainen err = falcon_boot(&vic->falcon); 1450ae797a8SArto Merilainen if (err < 0) 1460ae797a8SArto Merilainen return err; 1470ae797a8SArto Merilainen 148d972d624SThierry Reding hdr = vic->falcon.firmware.virt; 1490ae797a8SArto Merilainen fce_bin_data_offset = *(u32 *)(hdr + VIC_UCODE_FCE_DATA_OFFSET); 15058ef3aebSMikko Perttunen 15158ef3aebSMikko Perttunen falcon_execute_method(&vic->falcon, VIC_SET_APPLICATION_ID, 1); 15258ef3aebSMikko Perttunen 15358ef3aebSMikko Perttunen /* Old VIC firmware needs kernel help with setting up FCE microcode. */ 15458ef3aebSMikko Perttunen if (fce_bin_data_offset != 0x0 && fce_bin_data_offset != 0xa5a5a5a5) { 155d972d624SThierry Reding hdr = vic->falcon.firmware.virt + 1560ae797a8SArto Merilainen *(u32 *)(hdr + VIC_UCODE_FCE_HEADER_OFFSET); 1570ae797a8SArto Merilainen fce_ucode_size = *(u32 *)(hdr + FCE_UCODE_SIZE_OFFSET); 1580ae797a8SArto Merilainen 1590ae797a8SArto Merilainen falcon_execute_method(&vic->falcon, VIC_SET_FCE_UCODE_SIZE, 1600ae797a8SArto Merilainen fce_ucode_size); 16158ef3aebSMikko Perttunen falcon_execute_method( 16258ef3aebSMikko Perttunen &vic->falcon, VIC_SET_FCE_UCODE_OFFSET, 16358ef3aebSMikko Perttunen (vic->falcon.firmware.iova + fce_bin_data_offset) >> 8); 16458ef3aebSMikko Perttunen } 1650ae797a8SArto Merilainen 1660ae797a8SArto Merilainen err = falcon_wait_idle(&vic->falcon); 1670ae797a8SArto Merilainen if (err < 0) { 1680ae797a8SArto Merilainen dev_err(vic->dev, 1690ae797a8SArto Merilainen "failed to set application ID and FCE base\n"); 1700ae797a8SArto Merilainen return err; 1710ae797a8SArto Merilainen } 1720ae797a8SArto Merilainen 1730ae797a8SArto Merilainen vic->booted = true; 1740ae797a8SArto Merilainen 1750ae797a8SArto Merilainen return 0; 1760ae797a8SArto Merilainen } 1770ae797a8SArto Merilainen 1780ae797a8SArto Merilainen static int vic_init(struct host1x_client *client) 1790ae797a8SArto Merilainen { 1800ae797a8SArto Merilainen struct tegra_drm_client *drm = host1x_to_drm_client(client); 181608f43adSThierry Reding struct drm_device *dev = dev_get_drvdata(client->host); 1820ae797a8SArto Merilainen struct tegra_drm *tegra = dev->dev_private; 1830ae797a8SArto Merilainen struct vic *vic = to_vic(drm); 1840ae797a8SArto Merilainen int err; 1850ae797a8SArto Merilainen 1867edd7961SThierry Reding err = host1x_client_iommu_attach(client); 187a8817489SThierry Reding if (err < 0 && err != -ENODEV) { 1887baa943eSThierry Reding dev_err(vic->dev, "failed to attach to domain: %d\n", err); 1890ae797a8SArto Merilainen return err; 1900ae797a8SArto Merilainen } 1910ae797a8SArto Merilainen 192caccddcfSThierry Reding vic->channel = host1x_channel_request(client); 1930ae797a8SArto Merilainen if (!vic->channel) { 1940ae797a8SArto Merilainen err = -ENOMEM; 195bc8828bdSThierry Reding goto detach; 1960ae797a8SArto Merilainen } 1970ae797a8SArto Merilainen 198617dd7ccSThierry Reding client->syncpts[0] = host1x_syncpt_request(client, 0); 1990ae797a8SArto Merilainen if (!client->syncpts[0]) { 2000ae797a8SArto Merilainen err = -ENOMEM; 2010ae797a8SArto Merilainen goto free_channel; 2020ae797a8SArto Merilainen } 2030ae797a8SArto Merilainen 2040ae797a8SArto Merilainen err = tegra_drm_register_client(tegra, drm); 2050ae797a8SArto Merilainen if (err < 0) 2060ae797a8SArto Merilainen goto free_syncpt; 2070ae797a8SArto Merilainen 20847b15779SThierry Reding /* 20947b15779SThierry Reding * Inherit the DMA parameters (such as maximum segment size) from the 210608f43adSThierry Reding * parent host1x device. 21147b15779SThierry Reding */ 212608f43adSThierry Reding client->dev->dma_parms = client->host->dma_parms; 21347b15779SThierry Reding 2140ae797a8SArto Merilainen return 0; 2150ae797a8SArto Merilainen 2160ae797a8SArto Merilainen free_syncpt: 2170ae797a8SArto Merilainen host1x_syncpt_free(client->syncpts[0]); 2180ae797a8SArto Merilainen free_channel: 2198474b025SMikko Perttunen host1x_channel_put(vic->channel); 220bc8828bdSThierry Reding detach: 221aacdf198SThierry Reding host1x_client_iommu_detach(client); 2220ae797a8SArto Merilainen 2230ae797a8SArto Merilainen return err; 2240ae797a8SArto Merilainen } 2250ae797a8SArto Merilainen 2260ae797a8SArto Merilainen static int vic_exit(struct host1x_client *client) 2270ae797a8SArto Merilainen { 2280ae797a8SArto Merilainen struct tegra_drm_client *drm = host1x_to_drm_client(client); 229608f43adSThierry Reding struct drm_device *dev = dev_get_drvdata(client->host); 2300ae797a8SArto Merilainen struct tegra_drm *tegra = dev->dev_private; 2310ae797a8SArto Merilainen struct vic *vic = to_vic(drm); 2320ae797a8SArto Merilainen int err; 2330ae797a8SArto Merilainen 23447b15779SThierry Reding /* avoid a dangling pointer just in case this disappears */ 23547b15779SThierry Reding client->dev->dma_parms = NULL; 23647b15779SThierry Reding 2370ae797a8SArto Merilainen err = tegra_drm_unregister_client(tegra, drm); 2380ae797a8SArto Merilainen if (err < 0) 2390ae797a8SArto Merilainen return err; 2400ae797a8SArto Merilainen 2410ae797a8SArto Merilainen host1x_syncpt_free(client->syncpts[0]); 2428474b025SMikko Perttunen host1x_channel_put(vic->channel); 243aacdf198SThierry Reding host1x_client_iommu_detach(client); 2440ae797a8SArto Merilainen 245d972d624SThierry Reding if (client->group) { 246d972d624SThierry Reding dma_unmap_single(vic->dev, vic->falcon.firmware.phys, 247d972d624SThierry Reding vic->falcon.firmware.size, DMA_TO_DEVICE); 24820e7dce2SThierry Reding tegra_drm_free(tegra, vic->falcon.firmware.size, 249d972d624SThierry Reding vic->falcon.firmware.virt, 250d972d624SThierry Reding vic->falcon.firmware.iova); 251d972d624SThierry Reding } else { 25220e7dce2SThierry Reding dma_free_coherent(vic->dev, vic->falcon.firmware.size, 253d972d624SThierry Reding vic->falcon.firmware.virt, 254d972d624SThierry Reding vic->falcon.firmware.iova); 255d972d624SThierry Reding } 25620e7dce2SThierry Reding 2570ae797a8SArto Merilainen return 0; 2580ae797a8SArto Merilainen } 2590ae797a8SArto Merilainen 2600ae797a8SArto Merilainen static const struct host1x_client_ops vic_client_ops = { 2610ae797a8SArto Merilainen .init = vic_init, 2620ae797a8SArto Merilainen .exit = vic_exit, 2630ae797a8SArto Merilainen }; 2640ae797a8SArto Merilainen 26577a0b09dSThierry Reding static int vic_load_firmware(struct vic *vic) 26677a0b09dSThierry Reding { 26720e7dce2SThierry Reding struct host1x_client *client = &vic->client.base; 26820e7dce2SThierry Reding struct tegra_drm *tegra = vic->client.drm; 269d972d624SThierry Reding dma_addr_t iova; 27020e7dce2SThierry Reding size_t size; 27120e7dce2SThierry Reding void *virt; 27277a0b09dSThierry Reding int err; 27377a0b09dSThierry Reding 274d972d624SThierry Reding if (vic->falcon.firmware.virt) 27577a0b09dSThierry Reding return 0; 27677a0b09dSThierry Reding 27777a0b09dSThierry Reding err = falcon_read_firmware(&vic->falcon, vic->config->firmware); 27877a0b09dSThierry Reding if (err < 0) 27920e7dce2SThierry Reding return err; 28020e7dce2SThierry Reding 28120e7dce2SThierry Reding size = vic->falcon.firmware.size; 28220e7dce2SThierry Reding 28320e7dce2SThierry Reding if (!client->group) { 284d972d624SThierry Reding virt = dma_alloc_coherent(vic->dev, size, &iova, GFP_KERNEL); 28520e7dce2SThierry Reding 286d972d624SThierry Reding err = dma_mapping_error(vic->dev, iova); 28720e7dce2SThierry Reding if (err < 0) 28820e7dce2SThierry Reding return err; 28920e7dce2SThierry Reding } else { 290d972d624SThierry Reding virt = tegra_drm_alloc(tegra, size, &iova); 29120e7dce2SThierry Reding } 29220e7dce2SThierry Reding 293d972d624SThierry Reding vic->falcon.firmware.virt = virt; 294d972d624SThierry Reding vic->falcon.firmware.iova = iova; 29577a0b09dSThierry Reding 29677a0b09dSThierry Reding err = falcon_load_firmware(&vic->falcon); 29777a0b09dSThierry Reding if (err < 0) 29877a0b09dSThierry Reding goto cleanup; 29977a0b09dSThierry Reding 30020e7dce2SThierry Reding /* 30120e7dce2SThierry Reding * In this case we have received an IOVA from the shared domain, so we 30220e7dce2SThierry Reding * need to make sure to get the physical address so that the DMA API 30320e7dce2SThierry Reding * knows what memory pages to flush the cache for. 30420e7dce2SThierry Reding */ 30520e7dce2SThierry Reding if (client->group) { 306d972d624SThierry Reding dma_addr_t phys; 307d972d624SThierry Reding 30820e7dce2SThierry Reding phys = dma_map_single(vic->dev, virt, size, DMA_TO_DEVICE); 30920e7dce2SThierry Reding 31020e7dce2SThierry Reding err = dma_mapping_error(vic->dev, phys); 31120e7dce2SThierry Reding if (err < 0) 31220e7dce2SThierry Reding goto cleanup; 31320e7dce2SThierry Reding 314d972d624SThierry Reding vic->falcon.firmware.phys = phys; 31520e7dce2SThierry Reding } 31620e7dce2SThierry Reding 31777a0b09dSThierry Reding return 0; 31877a0b09dSThierry Reding 31977a0b09dSThierry Reding cleanup: 32020e7dce2SThierry Reding if (!client->group) 321d972d624SThierry Reding dma_free_coherent(vic->dev, size, virt, iova); 32220e7dce2SThierry Reding else 323d972d624SThierry Reding tegra_drm_free(tegra, size, virt, iova); 32420e7dce2SThierry Reding 32577a0b09dSThierry Reding return err; 32677a0b09dSThierry Reding } 32777a0b09dSThierry Reding 3280ae797a8SArto Merilainen static int vic_open_channel(struct tegra_drm_client *client, 3290ae797a8SArto Merilainen struct tegra_drm_context *context) 3300ae797a8SArto Merilainen { 3310ae797a8SArto Merilainen struct vic *vic = to_vic(client); 3320ae797a8SArto Merilainen int err; 3330ae797a8SArto Merilainen 3340ae797a8SArto Merilainen err = pm_runtime_get_sync(vic->dev); 3350ae797a8SArto Merilainen if (err < 0) 3360ae797a8SArto Merilainen return err; 3370ae797a8SArto Merilainen 33877a0b09dSThierry Reding err = vic_load_firmware(vic); 33977a0b09dSThierry Reding if (err < 0) 34077a0b09dSThierry Reding goto rpm_put; 34177a0b09dSThierry Reding 3420ae797a8SArto Merilainen err = vic_boot(vic); 34377a0b09dSThierry Reding if (err < 0) 34477a0b09dSThierry Reding goto rpm_put; 3450ae797a8SArto Merilainen 3460ae797a8SArto Merilainen context->channel = host1x_channel_get(vic->channel); 3470ae797a8SArto Merilainen if (!context->channel) { 34877a0b09dSThierry Reding err = -ENOMEM; 34977a0b09dSThierry Reding goto rpm_put; 3500ae797a8SArto Merilainen } 3510ae797a8SArto Merilainen 3520ae797a8SArto Merilainen return 0; 35377a0b09dSThierry Reding 35477a0b09dSThierry Reding rpm_put: 35577a0b09dSThierry Reding pm_runtime_put(vic->dev); 35677a0b09dSThierry Reding return err; 3570ae797a8SArto Merilainen } 3580ae797a8SArto Merilainen 3590ae797a8SArto Merilainen static void vic_close_channel(struct tegra_drm_context *context) 3600ae797a8SArto Merilainen { 3610ae797a8SArto Merilainen struct vic *vic = to_vic(context->client); 3620ae797a8SArto Merilainen 3630ae797a8SArto Merilainen host1x_channel_put(context->channel); 3640ae797a8SArto Merilainen 3650ae797a8SArto Merilainen pm_runtime_put(vic->dev); 3660ae797a8SArto Merilainen } 3670ae797a8SArto Merilainen 3680ae797a8SArto Merilainen static const struct tegra_drm_client_ops vic_ops = { 3690ae797a8SArto Merilainen .open_channel = vic_open_channel, 3700ae797a8SArto Merilainen .close_channel = vic_close_channel, 3710ae797a8SArto Merilainen .submit = tegra_drm_submit, 3720ae797a8SArto Merilainen }; 3730ae797a8SArto Merilainen 374788ff4b6SNicolas Chauvet #define NVIDIA_TEGRA_124_VIC_FIRMWARE "nvidia/tegra124/vic03_ucode.bin" 375788ff4b6SNicolas Chauvet 3760ae797a8SArto Merilainen static const struct vic_config vic_t124_config = { 377788ff4b6SNicolas Chauvet .firmware = NVIDIA_TEGRA_124_VIC_FIRMWARE, 378acae8a9dSThierry Reding .version = 0x40, 379f3779cb1SThierry Reding .supports_sid = false, 3800ae797a8SArto Merilainen }; 3810ae797a8SArto Merilainen 382788ff4b6SNicolas Chauvet #define NVIDIA_TEGRA_210_VIC_FIRMWARE "nvidia/tegra210/vic04_ucode.bin" 383788ff4b6SNicolas Chauvet 3840ae797a8SArto Merilainen static const struct vic_config vic_t210_config = { 385788ff4b6SNicolas Chauvet .firmware = NVIDIA_TEGRA_210_VIC_FIRMWARE, 386acae8a9dSThierry Reding .version = 0x21, 387f3779cb1SThierry Reding .supports_sid = false, 3880ae797a8SArto Merilainen }; 3890ae797a8SArto Merilainen 3906e44b9adSMikko Perttunen #define NVIDIA_TEGRA_186_VIC_FIRMWARE "nvidia/tegra186/vic04_ucode.bin" 3916e44b9adSMikko Perttunen 3926e44b9adSMikko Perttunen static const struct vic_config vic_t186_config = { 3936e44b9adSMikko Perttunen .firmware = NVIDIA_TEGRA_186_VIC_FIRMWARE, 394acae8a9dSThierry Reding .version = 0x18, 395f3779cb1SThierry Reding .supports_sid = true, 3966e44b9adSMikko Perttunen }; 3976e44b9adSMikko Perttunen 398d6b9bc02SThierry Reding #define NVIDIA_TEGRA_194_VIC_FIRMWARE "nvidia/tegra194/vic.bin" 399d6b9bc02SThierry Reding 400d6b9bc02SThierry Reding static const struct vic_config vic_t194_config = { 401d6b9bc02SThierry Reding .firmware = NVIDIA_TEGRA_194_VIC_FIRMWARE, 402d6b9bc02SThierry Reding .version = 0x19, 403f3779cb1SThierry Reding .supports_sid = true, 404d6b9bc02SThierry Reding }; 405d6b9bc02SThierry Reding 40682d73874SThierry Reding static const struct of_device_id tegra_vic_of_match[] = { 4070ae797a8SArto Merilainen { .compatible = "nvidia,tegra124-vic", .data = &vic_t124_config }, 4080ae797a8SArto Merilainen { .compatible = "nvidia,tegra210-vic", .data = &vic_t210_config }, 4096e44b9adSMikko Perttunen { .compatible = "nvidia,tegra186-vic", .data = &vic_t186_config }, 410d6b9bc02SThierry Reding { .compatible = "nvidia,tegra194-vic", .data = &vic_t194_config }, 4110ae797a8SArto Merilainen { }, 4120ae797a8SArto Merilainen }; 41382d73874SThierry Reding MODULE_DEVICE_TABLE(of, tegra_vic_of_match); 4140ae797a8SArto Merilainen 4150ae797a8SArto Merilainen static int vic_probe(struct platform_device *pdev) 4160ae797a8SArto Merilainen { 4170ae797a8SArto Merilainen struct device *dev = &pdev->dev; 4180ae797a8SArto Merilainen struct host1x_syncpt **syncpts; 4190ae797a8SArto Merilainen struct resource *regs; 4200ae797a8SArto Merilainen struct vic *vic; 4210ae797a8SArto Merilainen int err; 4220ae797a8SArto Merilainen 423d5ad0e3dSThierry Reding /* inherit DMA mask from host1x parent */ 424d5ad0e3dSThierry Reding err = dma_coerce_mask_and_coherent(dev, *dev->parent->dma_mask); 425d5ad0e3dSThierry Reding if (err < 0) { 426d5ad0e3dSThierry Reding dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err); 427d5ad0e3dSThierry Reding return err; 428d5ad0e3dSThierry Reding } 429d5ad0e3dSThierry Reding 4300ae797a8SArto Merilainen vic = devm_kzalloc(dev, sizeof(*vic), GFP_KERNEL); 4310ae797a8SArto Merilainen if (!vic) 4320ae797a8SArto Merilainen return -ENOMEM; 4330ae797a8SArto Merilainen 434829ce7a6SThierry Reding vic->config = of_device_get_match_data(dev); 435829ce7a6SThierry Reding 4360ae797a8SArto Merilainen syncpts = devm_kzalloc(dev, sizeof(*syncpts), GFP_KERNEL); 4370ae797a8SArto Merilainen if (!syncpts) 4380ae797a8SArto Merilainen return -ENOMEM; 4390ae797a8SArto Merilainen 4400ae797a8SArto Merilainen regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 4410ae797a8SArto Merilainen if (!regs) { 4420ae797a8SArto Merilainen dev_err(&pdev->dev, "failed to get registers\n"); 4430ae797a8SArto Merilainen return -ENXIO; 4440ae797a8SArto Merilainen } 4450ae797a8SArto Merilainen 4460ae797a8SArto Merilainen vic->regs = devm_ioremap_resource(dev, regs); 4470ae797a8SArto Merilainen if (IS_ERR(vic->regs)) 4480ae797a8SArto Merilainen return PTR_ERR(vic->regs); 4490ae797a8SArto Merilainen 4500ae797a8SArto Merilainen vic->clk = devm_clk_get(dev, NULL); 4510ae797a8SArto Merilainen if (IS_ERR(vic->clk)) { 4520ae797a8SArto Merilainen dev_err(&pdev->dev, "failed to get clock\n"); 4530ae797a8SArto Merilainen return PTR_ERR(vic->clk); 4540ae797a8SArto Merilainen } 4550ae797a8SArto Merilainen 4560dc34e19SThierry Reding if (!dev->pm_domain) { 4570dc34e19SThierry Reding vic->rst = devm_reset_control_get(dev, "vic"); 4580dc34e19SThierry Reding if (IS_ERR(vic->rst)) { 4590dc34e19SThierry Reding dev_err(&pdev->dev, "failed to get reset\n"); 4600dc34e19SThierry Reding return PTR_ERR(vic->rst); 4610dc34e19SThierry Reding } 4620dc34e19SThierry Reding } 4630dc34e19SThierry Reding 4640ae797a8SArto Merilainen vic->falcon.dev = dev; 4650ae797a8SArto Merilainen vic->falcon.regs = vic->regs; 4660ae797a8SArto Merilainen 4670ae797a8SArto Merilainen err = falcon_init(&vic->falcon); 4680ae797a8SArto Merilainen if (err < 0) 4690ae797a8SArto Merilainen return err; 4700ae797a8SArto Merilainen 4710ae797a8SArto Merilainen platform_set_drvdata(pdev, vic); 4720ae797a8SArto Merilainen 4730ae797a8SArto Merilainen INIT_LIST_HEAD(&vic->client.base.list); 4740ae797a8SArto Merilainen vic->client.base.ops = &vic_client_ops; 4750ae797a8SArto Merilainen vic->client.base.dev = dev; 4760ae797a8SArto Merilainen vic->client.base.class = HOST1X_CLASS_VIC; 4770ae797a8SArto Merilainen vic->client.base.syncpts = syncpts; 4780ae797a8SArto Merilainen vic->client.base.num_syncpts = 1; 4790ae797a8SArto Merilainen vic->dev = dev; 4800ae797a8SArto Merilainen 4810ae797a8SArto Merilainen INIT_LIST_HEAD(&vic->client.list); 482acae8a9dSThierry Reding vic->client.version = vic->config->version; 4830ae797a8SArto Merilainen vic->client.ops = &vic_ops; 4840ae797a8SArto Merilainen 4850ae797a8SArto Merilainen err = host1x_client_register(&vic->client.base); 4860ae797a8SArto Merilainen if (err < 0) { 4870ae797a8SArto Merilainen dev_err(dev, "failed to register host1x client: %d\n", err); 4880ae797a8SArto Merilainen goto exit_falcon; 4890ae797a8SArto Merilainen } 4900ae797a8SArto Merilainen 4910ae797a8SArto Merilainen pm_runtime_enable(&pdev->dev); 4920ae797a8SArto Merilainen if (!pm_runtime_enabled(&pdev->dev)) { 4930ae797a8SArto Merilainen err = vic_runtime_resume(&pdev->dev); 4940ae797a8SArto Merilainen if (err < 0) 4950ae797a8SArto Merilainen goto unregister_client; 4960ae797a8SArto Merilainen } 4970ae797a8SArto Merilainen 4980ae797a8SArto Merilainen return 0; 4990ae797a8SArto Merilainen 5000ae797a8SArto Merilainen unregister_client: 5010ae797a8SArto Merilainen host1x_client_unregister(&vic->client.base); 5020ae797a8SArto Merilainen exit_falcon: 5030ae797a8SArto Merilainen falcon_exit(&vic->falcon); 5040ae797a8SArto Merilainen 5050ae797a8SArto Merilainen return err; 5060ae797a8SArto Merilainen } 5070ae797a8SArto Merilainen 5080ae797a8SArto Merilainen static int vic_remove(struct platform_device *pdev) 5090ae797a8SArto Merilainen { 5100ae797a8SArto Merilainen struct vic *vic = platform_get_drvdata(pdev); 5110ae797a8SArto Merilainen int err; 5120ae797a8SArto Merilainen 5130ae797a8SArto Merilainen err = host1x_client_unregister(&vic->client.base); 5140ae797a8SArto Merilainen if (err < 0) { 5150ae797a8SArto Merilainen dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", 5160ae797a8SArto Merilainen err); 5170ae797a8SArto Merilainen return err; 5180ae797a8SArto Merilainen } 5190ae797a8SArto Merilainen 5200ae797a8SArto Merilainen if (pm_runtime_enabled(&pdev->dev)) 5210ae797a8SArto Merilainen pm_runtime_disable(&pdev->dev); 5220ae797a8SArto Merilainen else 5230ae797a8SArto Merilainen vic_runtime_suspend(&pdev->dev); 5240ae797a8SArto Merilainen 5250ae797a8SArto Merilainen falcon_exit(&vic->falcon); 5260ae797a8SArto Merilainen 5270ae797a8SArto Merilainen return 0; 5280ae797a8SArto Merilainen } 5290ae797a8SArto Merilainen 5300ae797a8SArto Merilainen static const struct dev_pm_ops vic_pm_ops = { 5310ae797a8SArto Merilainen SET_RUNTIME_PM_OPS(vic_runtime_suspend, vic_runtime_resume, NULL) 5320ae797a8SArto Merilainen }; 5330ae797a8SArto Merilainen 5340ae797a8SArto Merilainen struct platform_driver tegra_vic_driver = { 5350ae797a8SArto Merilainen .driver = { 5360ae797a8SArto Merilainen .name = "tegra-vic", 53782d73874SThierry Reding .of_match_table = tegra_vic_of_match, 5380ae797a8SArto Merilainen .pm = &vic_pm_ops 5390ae797a8SArto Merilainen }, 5400ae797a8SArto Merilainen .probe = vic_probe, 5410ae797a8SArto Merilainen .remove = vic_remove, 5420ae797a8SArto Merilainen }; 543788ff4b6SNicolas Chauvet 544788ff4b6SNicolas Chauvet #if IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC) 545788ff4b6SNicolas Chauvet MODULE_FIRMWARE(NVIDIA_TEGRA_124_VIC_FIRMWARE); 546788ff4b6SNicolas Chauvet #endif 547788ff4b6SNicolas Chauvet #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) 548788ff4b6SNicolas Chauvet MODULE_FIRMWARE(NVIDIA_TEGRA_210_VIC_FIRMWARE); 549788ff4b6SNicolas Chauvet #endif 5506e44b9adSMikko Perttunen #if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC) 5516e44b9adSMikko Perttunen MODULE_FIRMWARE(NVIDIA_TEGRA_186_VIC_FIRMWARE); 5526e44b9adSMikko Perttunen #endif 553d6b9bc02SThierry Reding #if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) 554d6b9bc02SThierry Reding MODULE_FIRMWARE(NVIDIA_TEGRA_194_VIC_FIRMWARE); 555d6b9bc02SThierry Reding #endif 556