1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 NVIDIA Corporation 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/debugfs.h> 9 #include <linux/gpio.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/of_device.h> 13 #include <linux/platform_device.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/reset.h> 17 18 #include <soc/tegra/pmc.h> 19 20 #include <drm/drm_atomic_helper.h> 21 #include <drm/drm_debugfs.h> 22 #include <drm/drm_dp_helper.h> 23 #include <drm/drm_file.h> 24 #include <drm/drm_panel.h> 25 #include <drm/drm_scdc_helper.h> 26 27 #include "dc.h" 28 #include "dp.h" 29 #include "drm.h" 30 #include "hda.h" 31 #include "sor.h" 32 #include "trace.h" 33 34 #define SOR_REKEY 0x38 35 36 struct tegra_sor_hdmi_settings { 37 unsigned long frequency; 38 39 u8 vcocap; 40 u8 filter; 41 u8 ichpmp; 42 u8 loadadj; 43 u8 tmds_termadj; 44 u8 tx_pu_value; 45 u8 bg_temp_coef; 46 u8 bg_vref_level; 47 u8 avdd10_level; 48 u8 avdd14_level; 49 u8 sparepll; 50 51 u8 drive_current[4]; 52 u8 preemphasis[4]; 53 }; 54 55 #if 1 56 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = { 57 { 58 .frequency = 54000000, 59 .vcocap = 0x0, 60 .filter = 0x0, 61 .ichpmp = 0x1, 62 .loadadj = 0x3, 63 .tmds_termadj = 0x9, 64 .tx_pu_value = 0x10, 65 .bg_temp_coef = 0x3, 66 .bg_vref_level = 0x8, 67 .avdd10_level = 0x4, 68 .avdd14_level = 0x4, 69 .sparepll = 0x0, 70 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a }, 71 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 72 }, { 73 .frequency = 75000000, 74 .vcocap = 0x3, 75 .filter = 0x0, 76 .ichpmp = 0x1, 77 .loadadj = 0x3, 78 .tmds_termadj = 0x9, 79 .tx_pu_value = 0x40, 80 .bg_temp_coef = 0x3, 81 .bg_vref_level = 0x8, 82 .avdd10_level = 0x4, 83 .avdd14_level = 0x4, 84 .sparepll = 0x0, 85 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a }, 86 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 87 }, { 88 .frequency = 150000000, 89 .vcocap = 0x3, 90 .filter = 0x0, 91 .ichpmp = 0x1, 92 .loadadj = 0x3, 93 .tmds_termadj = 0x9, 94 .tx_pu_value = 0x66, 95 .bg_temp_coef = 0x3, 96 .bg_vref_level = 0x8, 97 .avdd10_level = 0x4, 98 .avdd14_level = 0x4, 99 .sparepll = 0x0, 100 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a }, 101 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 102 }, { 103 .frequency = 300000000, 104 .vcocap = 0x3, 105 .filter = 0x0, 106 .ichpmp = 0x1, 107 .loadadj = 0x3, 108 .tmds_termadj = 0x9, 109 .tx_pu_value = 0x66, 110 .bg_temp_coef = 0x3, 111 .bg_vref_level = 0xa, 112 .avdd10_level = 0x4, 113 .avdd14_level = 0x4, 114 .sparepll = 0x0, 115 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f }, 116 .preemphasis = { 0x00, 0x17, 0x17, 0x17 }, 117 }, { 118 .frequency = 600000000, 119 .vcocap = 0x3, 120 .filter = 0x0, 121 .ichpmp = 0x1, 122 .loadadj = 0x3, 123 .tmds_termadj = 0x9, 124 .tx_pu_value = 0x66, 125 .bg_temp_coef = 0x3, 126 .bg_vref_level = 0x8, 127 .avdd10_level = 0x4, 128 .avdd14_level = 0x4, 129 .sparepll = 0x0, 130 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f }, 131 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 132 }, 133 }; 134 #else 135 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = { 136 { 137 .frequency = 75000000, 138 .vcocap = 0x3, 139 .filter = 0x0, 140 .ichpmp = 0x1, 141 .loadadj = 0x3, 142 .tmds_termadj = 0x9, 143 .tx_pu_value = 0x40, 144 .bg_temp_coef = 0x3, 145 .bg_vref_level = 0x8, 146 .avdd10_level = 0x4, 147 .avdd14_level = 0x4, 148 .sparepll = 0x0, 149 .drive_current = { 0x29, 0x29, 0x29, 0x29 }, 150 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 151 }, { 152 .frequency = 150000000, 153 .vcocap = 0x3, 154 .filter = 0x0, 155 .ichpmp = 0x1, 156 .loadadj = 0x3, 157 .tmds_termadj = 0x9, 158 .tx_pu_value = 0x66, 159 .bg_temp_coef = 0x3, 160 .bg_vref_level = 0x8, 161 .avdd10_level = 0x4, 162 .avdd14_level = 0x4, 163 .sparepll = 0x0, 164 .drive_current = { 0x30, 0x37, 0x37, 0x37 }, 165 .preemphasis = { 0x01, 0x02, 0x02, 0x02 }, 166 }, { 167 .frequency = 300000000, 168 .vcocap = 0x3, 169 .filter = 0x0, 170 .ichpmp = 0x6, 171 .loadadj = 0x3, 172 .tmds_termadj = 0x9, 173 .tx_pu_value = 0x66, 174 .bg_temp_coef = 0x3, 175 .bg_vref_level = 0xf, 176 .avdd10_level = 0x4, 177 .avdd14_level = 0x4, 178 .sparepll = 0x0, 179 .drive_current = { 0x30, 0x37, 0x37, 0x37 }, 180 .preemphasis = { 0x10, 0x3e, 0x3e, 0x3e }, 181 }, { 182 .frequency = 600000000, 183 .vcocap = 0x3, 184 .filter = 0x0, 185 .ichpmp = 0xa, 186 .loadadj = 0x3, 187 .tmds_termadj = 0xb, 188 .tx_pu_value = 0x66, 189 .bg_temp_coef = 0x3, 190 .bg_vref_level = 0xe, 191 .avdd10_level = 0x4, 192 .avdd14_level = 0x4, 193 .sparepll = 0x0, 194 .drive_current = { 0x35, 0x3e, 0x3e, 0x3e }, 195 .preemphasis = { 0x02, 0x3f, 0x3f, 0x3f }, 196 }, 197 }; 198 #endif 199 200 static const struct tegra_sor_hdmi_settings tegra186_sor_hdmi_defaults[] = { 201 { 202 .frequency = 54000000, 203 .vcocap = 0, 204 .filter = 5, 205 .ichpmp = 5, 206 .loadadj = 3, 207 .tmds_termadj = 0xf, 208 .tx_pu_value = 0, 209 .bg_temp_coef = 3, 210 .bg_vref_level = 8, 211 .avdd10_level = 4, 212 .avdd14_level = 4, 213 .sparepll = 0x54, 214 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 }, 215 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 216 }, { 217 .frequency = 75000000, 218 .vcocap = 1, 219 .filter = 5, 220 .ichpmp = 5, 221 .loadadj = 3, 222 .tmds_termadj = 0xf, 223 .tx_pu_value = 0, 224 .bg_temp_coef = 3, 225 .bg_vref_level = 8, 226 .avdd10_level = 4, 227 .avdd14_level = 4, 228 .sparepll = 0x44, 229 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 }, 230 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 231 }, { 232 .frequency = 150000000, 233 .vcocap = 3, 234 .filter = 5, 235 .ichpmp = 5, 236 .loadadj = 3, 237 .tmds_termadj = 15, 238 .tx_pu_value = 0x66 /* 0 */, 239 .bg_temp_coef = 3, 240 .bg_vref_level = 8, 241 .avdd10_level = 4, 242 .avdd14_level = 4, 243 .sparepll = 0x00, /* 0x34 */ 244 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 }, 245 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 246 }, { 247 .frequency = 300000000, 248 .vcocap = 3, 249 .filter = 5, 250 .ichpmp = 5, 251 .loadadj = 3, 252 .tmds_termadj = 15, 253 .tx_pu_value = 64, 254 .bg_temp_coef = 3, 255 .bg_vref_level = 8, 256 .avdd10_level = 4, 257 .avdd14_level = 4, 258 .sparepll = 0x34, 259 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 }, 260 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 261 }, { 262 .frequency = 600000000, 263 .vcocap = 3, 264 .filter = 5, 265 .ichpmp = 5, 266 .loadadj = 3, 267 .tmds_termadj = 12, 268 .tx_pu_value = 96, 269 .bg_temp_coef = 3, 270 .bg_vref_level = 8, 271 .avdd10_level = 4, 272 .avdd14_level = 4, 273 .sparepll = 0x34, 274 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 }, 275 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 276 } 277 }; 278 279 static const struct tegra_sor_hdmi_settings tegra194_sor_hdmi_defaults[] = { 280 { 281 .frequency = 54000000, 282 .vcocap = 0, 283 .filter = 5, 284 .ichpmp = 5, 285 .loadadj = 3, 286 .tmds_termadj = 0xf, 287 .tx_pu_value = 0, 288 .bg_temp_coef = 3, 289 .bg_vref_level = 8, 290 .avdd10_level = 4, 291 .avdd14_level = 4, 292 .sparepll = 0x54, 293 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 }, 294 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 295 }, { 296 .frequency = 75000000, 297 .vcocap = 1, 298 .filter = 5, 299 .ichpmp = 5, 300 .loadadj = 3, 301 .tmds_termadj = 0xf, 302 .tx_pu_value = 0, 303 .bg_temp_coef = 3, 304 .bg_vref_level = 8, 305 .avdd10_level = 4, 306 .avdd14_level = 4, 307 .sparepll = 0x44, 308 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 }, 309 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 310 }, { 311 .frequency = 150000000, 312 .vcocap = 3, 313 .filter = 5, 314 .ichpmp = 5, 315 .loadadj = 3, 316 .tmds_termadj = 15, 317 .tx_pu_value = 0x66 /* 0 */, 318 .bg_temp_coef = 3, 319 .bg_vref_level = 8, 320 .avdd10_level = 4, 321 .avdd14_level = 4, 322 .sparepll = 0x00, /* 0x34 */ 323 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 }, 324 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 325 }, { 326 .frequency = 300000000, 327 .vcocap = 3, 328 .filter = 5, 329 .ichpmp = 5, 330 .loadadj = 3, 331 .tmds_termadj = 15, 332 .tx_pu_value = 64, 333 .bg_temp_coef = 3, 334 .bg_vref_level = 8, 335 .avdd10_level = 4, 336 .avdd14_level = 4, 337 .sparepll = 0x34, 338 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 }, 339 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 340 }, { 341 .frequency = 600000000, 342 .vcocap = 3, 343 .filter = 5, 344 .ichpmp = 5, 345 .loadadj = 3, 346 .tmds_termadj = 12, 347 .tx_pu_value = 96, 348 .bg_temp_coef = 3, 349 .bg_vref_level = 8, 350 .avdd10_level = 4, 351 .avdd14_level = 4, 352 .sparepll = 0x34, 353 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 }, 354 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 355 } 356 }; 357 358 struct tegra_sor_regs { 359 unsigned int head_state0; 360 unsigned int head_state1; 361 unsigned int head_state2; 362 unsigned int head_state3; 363 unsigned int head_state4; 364 unsigned int head_state5; 365 unsigned int pll0; 366 unsigned int pll1; 367 unsigned int pll2; 368 unsigned int pll3; 369 unsigned int dp_padctl0; 370 unsigned int dp_padctl2; 371 }; 372 373 struct tegra_sor_soc { 374 bool supports_lvds; 375 bool supports_hdmi; 376 bool supports_dp; 377 bool supports_audio; 378 bool supports_hdcp; 379 380 const struct tegra_sor_regs *regs; 381 bool has_nvdisplay; 382 383 const struct tegra_sor_hdmi_settings *settings; 384 unsigned int num_settings; 385 386 const u8 *xbar_cfg; 387 const u8 *lane_map; 388 389 const u8 (*voltage_swing)[4][4]; 390 const u8 (*pre_emphasis)[4][4]; 391 const u8 (*post_cursor)[4][4]; 392 const u8 (*tx_pu)[4][4]; 393 }; 394 395 struct tegra_sor; 396 397 struct tegra_sor_ops { 398 const char *name; 399 int (*probe)(struct tegra_sor *sor); 400 int (*remove)(struct tegra_sor *sor); 401 void (*audio_enable)(struct tegra_sor *sor); 402 void (*audio_disable)(struct tegra_sor *sor); 403 }; 404 405 struct tegra_sor { 406 struct host1x_client client; 407 struct tegra_output output; 408 struct device *dev; 409 410 const struct tegra_sor_soc *soc; 411 void __iomem *regs; 412 unsigned int index; 413 unsigned int irq; 414 415 struct reset_control *rst; 416 struct clk *clk_parent; 417 struct clk *clk_safe; 418 struct clk *clk_out; 419 struct clk *clk_pad; 420 struct clk *clk_dp; 421 struct clk *clk; 422 423 u8 xbar_cfg[5]; 424 425 struct drm_dp_link link; 426 struct drm_dp_aux *aux; 427 428 struct drm_info_list *debugfs_files; 429 430 const struct tegra_sor_ops *ops; 431 enum tegra_io_pad pad; 432 433 /* for HDMI 2.0 */ 434 struct tegra_sor_hdmi_settings *settings; 435 unsigned int num_settings; 436 437 struct regulator *avdd_io_supply; 438 struct regulator *vdd_pll_supply; 439 struct regulator *hdmi_supply; 440 441 struct delayed_work scdc; 442 bool scdc_enabled; 443 444 struct tegra_hda_format format; 445 }; 446 447 struct tegra_sor_state { 448 struct drm_connector_state base; 449 450 unsigned int link_speed; 451 unsigned long pclk; 452 unsigned int bpc; 453 }; 454 455 static inline struct tegra_sor_state * 456 to_sor_state(struct drm_connector_state *state) 457 { 458 return container_of(state, struct tegra_sor_state, base); 459 } 460 461 struct tegra_sor_config { 462 u32 bits_per_pixel; 463 464 u32 active_polarity; 465 u32 active_count; 466 u32 tu_size; 467 u32 active_frac; 468 u32 watermark; 469 470 u32 hblank_symbols; 471 u32 vblank_symbols; 472 }; 473 474 static inline struct tegra_sor * 475 host1x_client_to_sor(struct host1x_client *client) 476 { 477 return container_of(client, struct tegra_sor, client); 478 } 479 480 static inline struct tegra_sor *to_sor(struct tegra_output *output) 481 { 482 return container_of(output, struct tegra_sor, output); 483 } 484 485 static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned int offset) 486 { 487 u32 value = readl(sor->regs + (offset << 2)); 488 489 trace_sor_readl(sor->dev, offset, value); 490 491 return value; 492 } 493 494 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, 495 unsigned int offset) 496 { 497 trace_sor_writel(sor->dev, offset, value); 498 writel(value, sor->regs + (offset << 2)); 499 } 500 501 static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent) 502 { 503 int err; 504 505 clk_disable_unprepare(sor->clk); 506 507 err = clk_set_parent(sor->clk_out, parent); 508 if (err < 0) 509 return err; 510 511 err = clk_prepare_enable(sor->clk); 512 if (err < 0) 513 return err; 514 515 return 0; 516 } 517 518 struct tegra_clk_sor_pad { 519 struct clk_hw hw; 520 struct tegra_sor *sor; 521 }; 522 523 static inline struct tegra_clk_sor_pad *to_pad(struct clk_hw *hw) 524 { 525 return container_of(hw, struct tegra_clk_sor_pad, hw); 526 } 527 528 static const char * const tegra_clk_sor_pad_parents[2][2] = { 529 { "pll_d_out0", "pll_dp" }, 530 { "pll_d2_out0", "pll_dp" }, 531 }; 532 533 /* 534 * Implementing ->set_parent() here isn't really required because the parent 535 * will be explicitly selected in the driver code via the DP_CLK_SEL mux in 536 * the SOR_CLK_CNTRL register. This is primarily for compatibility with the 537 * Tegra186 and later SoC generations where the BPMP implements this clock 538 * and doesn't expose the mux via the common clock framework. 539 */ 540 541 static int tegra_clk_sor_pad_set_parent(struct clk_hw *hw, u8 index) 542 { 543 struct tegra_clk_sor_pad *pad = to_pad(hw); 544 struct tegra_sor *sor = pad->sor; 545 u32 value; 546 547 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 548 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; 549 550 switch (index) { 551 case 0: 552 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; 553 break; 554 555 case 1: 556 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; 557 break; 558 } 559 560 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 561 562 return 0; 563 } 564 565 static u8 tegra_clk_sor_pad_get_parent(struct clk_hw *hw) 566 { 567 struct tegra_clk_sor_pad *pad = to_pad(hw); 568 struct tegra_sor *sor = pad->sor; 569 u8 parent = U8_MAX; 570 u32 value; 571 572 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 573 574 switch (value & SOR_CLK_CNTRL_DP_CLK_SEL_MASK) { 575 case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK: 576 case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK: 577 parent = 0; 578 break; 579 580 case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK: 581 case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK: 582 parent = 1; 583 break; 584 } 585 586 return parent; 587 } 588 589 static const struct clk_ops tegra_clk_sor_pad_ops = { 590 .set_parent = tegra_clk_sor_pad_set_parent, 591 .get_parent = tegra_clk_sor_pad_get_parent, 592 }; 593 594 static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor, 595 const char *name) 596 { 597 struct tegra_clk_sor_pad *pad; 598 struct clk_init_data init; 599 struct clk *clk; 600 601 pad = devm_kzalloc(sor->dev, sizeof(*pad), GFP_KERNEL); 602 if (!pad) 603 return ERR_PTR(-ENOMEM); 604 605 pad->sor = sor; 606 607 init.name = name; 608 init.flags = 0; 609 init.parent_names = tegra_clk_sor_pad_parents[sor->index]; 610 init.num_parents = ARRAY_SIZE(tegra_clk_sor_pad_parents[sor->index]); 611 init.ops = &tegra_clk_sor_pad_ops; 612 613 pad->hw.init = &init; 614 615 clk = devm_clk_register(sor->dev, &pad->hw); 616 617 return clk; 618 } 619 620 static void tegra_sor_filter_rates(struct tegra_sor *sor) 621 { 622 struct drm_dp_link *link = &sor->link; 623 unsigned int i; 624 625 /* Tegra only supports RBR, HBR and HBR2 */ 626 for (i = 0; i < link->num_rates; i++) { 627 switch (link->rates[i]) { 628 case 1620000: 629 case 2700000: 630 case 5400000: 631 break; 632 633 default: 634 DRM_DEBUG_KMS("link rate %lu kHz not supported\n", 635 link->rates[i]); 636 link->rates[i] = 0; 637 break; 638 } 639 } 640 641 drm_dp_link_update_rates(link); 642 } 643 644 static int tegra_sor_power_up_lanes(struct tegra_sor *sor, unsigned int lanes) 645 { 646 unsigned long timeout; 647 u32 value; 648 649 /* 650 * Clear or set the PD_TXD bit corresponding to each lane, depending 651 * on whether it is used or not. 652 */ 653 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 654 655 if (lanes <= 2) 656 value &= ~(SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) | 657 SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2])); 658 else 659 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) | 660 SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]); 661 662 if (lanes <= 1) 663 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]); 664 else 665 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]); 666 667 if (lanes == 0) 668 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]); 669 else 670 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]); 671 672 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 673 674 /* start lane sequencer */ 675 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | 676 SOR_LANE_SEQ_CTL_POWER_STATE_UP; 677 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); 678 679 timeout = jiffies + msecs_to_jiffies(250); 680 681 while (time_before(jiffies, timeout)) { 682 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 683 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) 684 break; 685 686 usleep_range(250, 1000); 687 } 688 689 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) 690 return -ETIMEDOUT; 691 692 return 0; 693 } 694 695 static int tegra_sor_power_down_lanes(struct tegra_sor *sor) 696 { 697 unsigned long timeout; 698 u32 value; 699 700 /* power down all lanes */ 701 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 702 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | 703 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2); 704 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 705 706 /* start lane sequencer */ 707 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP | 708 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN; 709 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); 710 711 timeout = jiffies + msecs_to_jiffies(250); 712 713 while (time_before(jiffies, timeout)) { 714 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 715 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) 716 break; 717 718 usleep_range(25, 100); 719 } 720 721 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) 722 return -ETIMEDOUT; 723 724 return 0; 725 } 726 727 static void tegra_sor_dp_precharge(struct tegra_sor *sor, unsigned int lanes) 728 { 729 u32 value; 730 731 /* pre-charge all used lanes */ 732 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 733 734 if (lanes <= 2) 735 value &= ~(SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) | 736 SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2])); 737 else 738 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) | 739 SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]); 740 741 if (lanes <= 1) 742 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]); 743 else 744 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]); 745 746 if (lanes == 0) 747 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]); 748 else 749 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]); 750 751 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 752 753 usleep_range(15, 100); 754 755 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 756 value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | 757 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0); 758 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 759 } 760 761 static void tegra_sor_dp_term_calibrate(struct tegra_sor *sor) 762 { 763 u32 mask = 0x08, adj = 0, value; 764 765 /* enable pad calibration logic */ 766 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 767 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; 768 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 769 770 value = tegra_sor_readl(sor, sor->soc->regs->pll1); 771 value |= SOR_PLL1_TMDS_TERM; 772 tegra_sor_writel(sor, value, sor->soc->regs->pll1); 773 774 while (mask) { 775 adj |= mask; 776 777 value = tegra_sor_readl(sor, sor->soc->regs->pll1); 778 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; 779 value |= SOR_PLL1_TMDS_TERMADJ(adj); 780 tegra_sor_writel(sor, value, sor->soc->regs->pll1); 781 782 usleep_range(100, 200); 783 784 value = tegra_sor_readl(sor, sor->soc->regs->pll1); 785 if (value & SOR_PLL1_TERM_COMPOUT) 786 adj &= ~mask; 787 788 mask >>= 1; 789 } 790 791 value = tegra_sor_readl(sor, sor->soc->regs->pll1); 792 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; 793 value |= SOR_PLL1_TMDS_TERMADJ(adj); 794 tegra_sor_writel(sor, value, sor->soc->regs->pll1); 795 796 /* disable pad calibration logic */ 797 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 798 value |= SOR_DP_PADCTL_PAD_CAL_PD; 799 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 800 } 801 802 static int tegra_sor_dp_link_apply_training(struct drm_dp_link *link) 803 { 804 struct tegra_sor *sor = container_of(link, struct tegra_sor, link); 805 u32 voltage_swing = 0, pre_emphasis = 0, post_cursor = 0; 806 const struct tegra_sor_soc *soc = sor->soc; 807 u32 pattern = 0, tx_pu = 0, value; 808 unsigned int i; 809 810 for (value = 0, i = 0; i < link->lanes; i++) { 811 u8 vs = link->train.request.voltage_swing[i]; 812 u8 pe = link->train.request.pre_emphasis[i]; 813 u8 pc = link->train.request.post_cursor[i]; 814 u8 shift = sor->soc->lane_map[i] << 3; 815 816 voltage_swing |= soc->voltage_swing[pc][vs][pe] << shift; 817 pre_emphasis |= soc->pre_emphasis[pc][vs][pe] << shift; 818 post_cursor |= soc->post_cursor[pc][vs][pe] << shift; 819 820 if (sor->soc->tx_pu[pc][vs][pe] > tx_pu) 821 tx_pu = sor->soc->tx_pu[pc][vs][pe]; 822 823 switch (link->train.pattern) { 824 case DP_TRAINING_PATTERN_DISABLE: 825 value = SOR_DP_TPG_SCRAMBLER_GALIOS | 826 SOR_DP_TPG_PATTERN_NONE; 827 break; 828 829 case DP_TRAINING_PATTERN_1: 830 value = SOR_DP_TPG_SCRAMBLER_NONE | 831 SOR_DP_TPG_PATTERN_TRAIN1; 832 break; 833 834 case DP_TRAINING_PATTERN_2: 835 value = SOR_DP_TPG_SCRAMBLER_NONE | 836 SOR_DP_TPG_PATTERN_TRAIN2; 837 break; 838 839 case DP_TRAINING_PATTERN_3: 840 value = SOR_DP_TPG_SCRAMBLER_NONE | 841 SOR_DP_TPG_PATTERN_TRAIN3; 842 break; 843 844 default: 845 return -EINVAL; 846 } 847 848 if (link->caps.channel_coding) 849 value |= SOR_DP_TPG_CHANNEL_CODING; 850 851 pattern = pattern << 8 | value; 852 } 853 854 tegra_sor_writel(sor, voltage_swing, SOR_LANE_DRIVE_CURRENT0); 855 tegra_sor_writel(sor, pre_emphasis, SOR_LANE_PREEMPHASIS0); 856 857 if (link->caps.tps3_supported) 858 tegra_sor_writel(sor, post_cursor, SOR_LANE_POSTCURSOR0); 859 860 tegra_sor_writel(sor, pattern, SOR_DP_TPG); 861 862 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 863 value &= ~SOR_DP_PADCTL_TX_PU_MASK; 864 value |= SOR_DP_PADCTL_TX_PU_ENABLE; 865 value |= SOR_DP_PADCTL_TX_PU(tx_pu); 866 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 867 868 usleep_range(20, 100); 869 870 return 0; 871 } 872 873 static int tegra_sor_dp_link_configure(struct drm_dp_link *link) 874 { 875 struct tegra_sor *sor = container_of(link, struct tegra_sor, link); 876 unsigned int rate, lanes; 877 u32 value; 878 int err; 879 880 rate = drm_dp_link_rate_to_bw_code(link->rate); 881 lanes = link->lanes; 882 883 /* configure link speed and lane count */ 884 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 885 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; 886 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate); 887 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 888 889 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); 890 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; 891 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes); 892 893 if (link->caps.enhanced_framing) 894 value |= SOR_DP_LINKCTL_ENHANCED_FRAME; 895 896 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); 897 898 usleep_range(400, 1000); 899 900 /* configure load pulse position adjustment */ 901 value = tegra_sor_readl(sor, sor->soc->regs->pll1); 902 value &= ~SOR_PLL1_LOADADJ_MASK; 903 904 switch (rate) { 905 case DP_LINK_BW_1_62: 906 value |= SOR_PLL1_LOADADJ(0x3); 907 break; 908 909 case DP_LINK_BW_2_7: 910 value |= SOR_PLL1_LOADADJ(0x4); 911 break; 912 913 case DP_LINK_BW_5_4: 914 value |= SOR_PLL1_LOADADJ(0x6); 915 break; 916 } 917 918 tegra_sor_writel(sor, value, sor->soc->regs->pll1); 919 920 /* use alternate scrambler reset for eDP */ 921 value = tegra_sor_readl(sor, SOR_DP_SPARE0); 922 923 if (link->edp == 0) 924 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; 925 else 926 value |= SOR_DP_SPARE_PANEL_INTERNAL; 927 928 tegra_sor_writel(sor, value, SOR_DP_SPARE0); 929 930 err = tegra_sor_power_down_lanes(sor); 931 if (err < 0) { 932 dev_err(sor->dev, "failed to power down lanes: %d\n", err); 933 return err; 934 } 935 936 /* power up and pre-charge lanes */ 937 err = tegra_sor_power_up_lanes(sor, lanes); 938 if (err < 0) { 939 dev_err(sor->dev, "failed to power up %u lane%s: %d\n", 940 lanes, (lanes != 1) ? "s" : "", err); 941 return err; 942 } 943 944 tegra_sor_dp_precharge(sor, lanes); 945 946 return 0; 947 } 948 949 static const struct drm_dp_link_ops tegra_sor_dp_link_ops = { 950 .apply_training = tegra_sor_dp_link_apply_training, 951 .configure = tegra_sor_dp_link_configure, 952 }; 953 954 static void tegra_sor_super_update(struct tegra_sor *sor) 955 { 956 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); 957 tegra_sor_writel(sor, 1, SOR_SUPER_STATE0); 958 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); 959 } 960 961 static void tegra_sor_update(struct tegra_sor *sor) 962 { 963 tegra_sor_writel(sor, 0, SOR_STATE0); 964 tegra_sor_writel(sor, 1, SOR_STATE0); 965 tegra_sor_writel(sor, 0, SOR_STATE0); 966 } 967 968 static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout) 969 { 970 u32 value; 971 972 value = tegra_sor_readl(sor, SOR_PWM_DIV); 973 value &= ~SOR_PWM_DIV_MASK; 974 value |= 0x400; /* period */ 975 tegra_sor_writel(sor, value, SOR_PWM_DIV); 976 977 value = tegra_sor_readl(sor, SOR_PWM_CTL); 978 value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK; 979 value |= 0x400; /* duty cycle */ 980 value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */ 981 value |= SOR_PWM_CTL_TRIGGER; 982 tegra_sor_writel(sor, value, SOR_PWM_CTL); 983 984 timeout = jiffies + msecs_to_jiffies(timeout); 985 986 while (time_before(jiffies, timeout)) { 987 value = tegra_sor_readl(sor, SOR_PWM_CTL); 988 if ((value & SOR_PWM_CTL_TRIGGER) == 0) 989 return 0; 990 991 usleep_range(25, 100); 992 } 993 994 return -ETIMEDOUT; 995 } 996 997 static int tegra_sor_attach(struct tegra_sor *sor) 998 { 999 unsigned long value, timeout; 1000 1001 /* wake up in normal mode */ 1002 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 1003 value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE; 1004 value |= SOR_SUPER_STATE_MODE_NORMAL; 1005 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 1006 tegra_sor_super_update(sor); 1007 1008 /* attach */ 1009 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 1010 value |= SOR_SUPER_STATE_ATTACHED; 1011 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 1012 tegra_sor_super_update(sor); 1013 1014 timeout = jiffies + msecs_to_jiffies(250); 1015 1016 while (time_before(jiffies, timeout)) { 1017 value = tegra_sor_readl(sor, SOR_TEST); 1018 if ((value & SOR_TEST_ATTACHED) != 0) 1019 return 0; 1020 1021 usleep_range(25, 100); 1022 } 1023 1024 return -ETIMEDOUT; 1025 } 1026 1027 static int tegra_sor_wakeup(struct tegra_sor *sor) 1028 { 1029 unsigned long value, timeout; 1030 1031 timeout = jiffies + msecs_to_jiffies(250); 1032 1033 /* wait for head to wake up */ 1034 while (time_before(jiffies, timeout)) { 1035 value = tegra_sor_readl(sor, SOR_TEST); 1036 value &= SOR_TEST_HEAD_MODE_MASK; 1037 1038 if (value == SOR_TEST_HEAD_MODE_AWAKE) 1039 return 0; 1040 1041 usleep_range(25, 100); 1042 } 1043 1044 return -ETIMEDOUT; 1045 } 1046 1047 static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout) 1048 { 1049 u32 value; 1050 1051 value = tegra_sor_readl(sor, SOR_PWR); 1052 value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU; 1053 tegra_sor_writel(sor, value, SOR_PWR); 1054 1055 timeout = jiffies + msecs_to_jiffies(timeout); 1056 1057 while (time_before(jiffies, timeout)) { 1058 value = tegra_sor_readl(sor, SOR_PWR); 1059 if ((value & SOR_PWR_TRIGGER) == 0) 1060 return 0; 1061 1062 usleep_range(25, 100); 1063 } 1064 1065 return -ETIMEDOUT; 1066 } 1067 1068 struct tegra_sor_params { 1069 /* number of link clocks per line */ 1070 unsigned int num_clocks; 1071 /* ratio between input and output */ 1072 u64 ratio; 1073 /* precision factor */ 1074 u64 precision; 1075 1076 unsigned int active_polarity; 1077 unsigned int active_count; 1078 unsigned int active_frac; 1079 unsigned int tu_size; 1080 unsigned int error; 1081 }; 1082 1083 static int tegra_sor_compute_params(struct tegra_sor *sor, 1084 struct tegra_sor_params *params, 1085 unsigned int tu_size) 1086 { 1087 u64 active_sym, active_count, frac, approx; 1088 u32 active_polarity, active_frac = 0; 1089 const u64 f = params->precision; 1090 s64 error; 1091 1092 active_sym = params->ratio * tu_size; 1093 active_count = div_u64(active_sym, f) * f; 1094 frac = active_sym - active_count; 1095 1096 /* fraction < 0.5 */ 1097 if (frac >= (f / 2)) { 1098 active_polarity = 1; 1099 frac = f - frac; 1100 } else { 1101 active_polarity = 0; 1102 } 1103 1104 if (frac != 0) { 1105 frac = div_u64(f * f, frac); /* 1/fraction */ 1106 if (frac <= (15 * f)) { 1107 active_frac = div_u64(frac, f); 1108 1109 /* round up */ 1110 if (active_polarity) 1111 active_frac++; 1112 } else { 1113 active_frac = active_polarity ? 1 : 15; 1114 } 1115 } 1116 1117 if (active_frac == 1) 1118 active_polarity = 0; 1119 1120 if (active_polarity == 1) { 1121 if (active_frac) { 1122 approx = active_count + (active_frac * (f - 1)) * f; 1123 approx = div_u64(approx, active_frac * f); 1124 } else { 1125 approx = active_count + f; 1126 } 1127 } else { 1128 if (active_frac) 1129 approx = active_count + div_u64(f, active_frac); 1130 else 1131 approx = active_count; 1132 } 1133 1134 error = div_s64(active_sym - approx, tu_size); 1135 error *= params->num_clocks; 1136 1137 if (error <= 0 && abs(error) < params->error) { 1138 params->active_count = div_u64(active_count, f); 1139 params->active_polarity = active_polarity; 1140 params->active_frac = active_frac; 1141 params->error = abs(error); 1142 params->tu_size = tu_size; 1143 1144 if (error == 0) 1145 return true; 1146 } 1147 1148 return false; 1149 } 1150 1151 static int tegra_sor_compute_config(struct tegra_sor *sor, 1152 const struct drm_display_mode *mode, 1153 struct tegra_sor_config *config, 1154 struct drm_dp_link *link) 1155 { 1156 const u64 f = 100000, link_rate = link->rate * 1000; 1157 const u64 pclk = mode->clock * 1000; 1158 u64 input, output, watermark, num; 1159 struct tegra_sor_params params; 1160 u32 num_syms_per_line; 1161 unsigned int i; 1162 1163 if (!link_rate || !link->lanes || !pclk || !config->bits_per_pixel) 1164 return -EINVAL; 1165 1166 input = pclk * config->bits_per_pixel; 1167 output = link_rate * 8 * link->lanes; 1168 1169 if (input >= output) 1170 return -ERANGE; 1171 1172 memset(¶ms, 0, sizeof(params)); 1173 params.ratio = div64_u64(input * f, output); 1174 params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk); 1175 params.precision = f; 1176 params.error = 64 * f; 1177 params.tu_size = 64; 1178 1179 for (i = params.tu_size; i >= 32; i--) 1180 if (tegra_sor_compute_params(sor, ¶ms, i)) 1181 break; 1182 1183 if (params.active_frac == 0) { 1184 config->active_polarity = 0; 1185 config->active_count = params.active_count; 1186 1187 if (!params.active_polarity) 1188 config->active_count--; 1189 1190 config->tu_size = params.tu_size; 1191 config->active_frac = 1; 1192 } else { 1193 config->active_polarity = params.active_polarity; 1194 config->active_count = params.active_count; 1195 config->active_frac = params.active_frac; 1196 config->tu_size = params.tu_size; 1197 } 1198 1199 dev_dbg(sor->dev, 1200 "polarity: %d active count: %d tu size: %d active frac: %d\n", 1201 config->active_polarity, config->active_count, 1202 config->tu_size, config->active_frac); 1203 1204 watermark = params.ratio * config->tu_size * (f - params.ratio); 1205 watermark = div_u64(watermark, f); 1206 1207 watermark = div_u64(watermark + params.error, f); 1208 config->watermark = watermark + (config->bits_per_pixel / 8) + 2; 1209 num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) * 1210 (link->lanes * 8); 1211 1212 if (config->watermark > 30) { 1213 config->watermark = 30; 1214 dev_err(sor->dev, 1215 "unable to compute TU size, forcing watermark to %u\n", 1216 config->watermark); 1217 } else if (config->watermark > num_syms_per_line) { 1218 config->watermark = num_syms_per_line; 1219 dev_err(sor->dev, "watermark too high, forcing to %u\n", 1220 config->watermark); 1221 } 1222 1223 /* compute the number of symbols per horizontal blanking interval */ 1224 num = ((mode->htotal - mode->hdisplay) - 7) * link_rate; 1225 config->hblank_symbols = div_u64(num, pclk); 1226 1227 if (link->caps.enhanced_framing) 1228 config->hblank_symbols -= 3; 1229 1230 config->hblank_symbols -= 12 / link->lanes; 1231 1232 /* compute the number of symbols per vertical blanking interval */ 1233 num = (mode->hdisplay - 25) * link_rate; 1234 config->vblank_symbols = div_u64(num, pclk); 1235 config->vblank_symbols -= 36 / link->lanes + 4; 1236 1237 dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols, 1238 config->vblank_symbols); 1239 1240 return 0; 1241 } 1242 1243 static void tegra_sor_apply_config(struct tegra_sor *sor, 1244 const struct tegra_sor_config *config) 1245 { 1246 u32 value; 1247 1248 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); 1249 value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK; 1250 value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size); 1251 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); 1252 1253 value = tegra_sor_readl(sor, SOR_DP_CONFIG0); 1254 value &= ~SOR_DP_CONFIG_WATERMARK_MASK; 1255 value |= SOR_DP_CONFIG_WATERMARK(config->watermark); 1256 1257 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK; 1258 value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count); 1259 1260 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK; 1261 value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac); 1262 1263 if (config->active_polarity) 1264 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; 1265 else 1266 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; 1267 1268 value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE; 1269 value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE; 1270 tegra_sor_writel(sor, value, SOR_DP_CONFIG0); 1271 1272 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS); 1273 value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK; 1274 value |= config->hblank_symbols & 0xffff; 1275 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS); 1276 1277 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS); 1278 value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK; 1279 value |= config->vblank_symbols & 0xffff; 1280 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS); 1281 } 1282 1283 static void tegra_sor_mode_set(struct tegra_sor *sor, 1284 const struct drm_display_mode *mode, 1285 struct tegra_sor_state *state) 1286 { 1287 struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc); 1288 unsigned int vbe, vse, hbe, hse, vbs, hbs; 1289 u32 value; 1290 1291 value = tegra_sor_readl(sor, SOR_STATE1); 1292 value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK; 1293 value &= ~SOR_STATE_ASY_CRC_MODE_MASK; 1294 value &= ~SOR_STATE_ASY_OWNER_MASK; 1295 1296 value |= SOR_STATE_ASY_CRC_MODE_COMPLETE | 1297 SOR_STATE_ASY_OWNER(dc->pipe + 1); 1298 1299 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 1300 value &= ~SOR_STATE_ASY_HSYNCPOL; 1301 1302 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 1303 value |= SOR_STATE_ASY_HSYNCPOL; 1304 1305 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 1306 value &= ~SOR_STATE_ASY_VSYNCPOL; 1307 1308 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 1309 value |= SOR_STATE_ASY_VSYNCPOL; 1310 1311 switch (state->bpc) { 1312 case 16: 1313 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444; 1314 break; 1315 1316 case 12: 1317 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444; 1318 break; 1319 1320 case 10: 1321 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444; 1322 break; 1323 1324 case 8: 1325 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; 1326 break; 1327 1328 case 6: 1329 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444; 1330 break; 1331 1332 default: 1333 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; 1334 break; 1335 } 1336 1337 tegra_sor_writel(sor, value, SOR_STATE1); 1338 1339 /* 1340 * TODO: The video timing programming below doesn't seem to match the 1341 * register definitions. 1342 */ 1343 1344 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff); 1345 tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe); 1346 1347 /* sync end = sync width - 1 */ 1348 vse = mode->vsync_end - mode->vsync_start - 1; 1349 hse = mode->hsync_end - mode->hsync_start - 1; 1350 1351 value = ((vse & 0x7fff) << 16) | (hse & 0x7fff); 1352 tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe); 1353 1354 /* blank end = sync end + back porch */ 1355 vbe = vse + (mode->vtotal - mode->vsync_end); 1356 hbe = hse + (mode->htotal - mode->hsync_end); 1357 1358 value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff); 1359 tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe); 1360 1361 /* blank start = blank end + active */ 1362 vbs = vbe + mode->vdisplay; 1363 hbs = hbe + mode->hdisplay; 1364 1365 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff); 1366 tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe); 1367 1368 /* XXX interlacing support */ 1369 tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe); 1370 } 1371 1372 static int tegra_sor_detach(struct tegra_sor *sor) 1373 { 1374 unsigned long value, timeout; 1375 1376 /* switch to safe mode */ 1377 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 1378 value &= ~SOR_SUPER_STATE_MODE_NORMAL; 1379 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 1380 tegra_sor_super_update(sor); 1381 1382 timeout = jiffies + msecs_to_jiffies(250); 1383 1384 while (time_before(jiffies, timeout)) { 1385 value = tegra_sor_readl(sor, SOR_PWR); 1386 if (value & SOR_PWR_MODE_SAFE) 1387 break; 1388 } 1389 1390 if ((value & SOR_PWR_MODE_SAFE) == 0) 1391 return -ETIMEDOUT; 1392 1393 /* go to sleep */ 1394 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 1395 value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK; 1396 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 1397 tegra_sor_super_update(sor); 1398 1399 /* detach */ 1400 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 1401 value &= ~SOR_SUPER_STATE_ATTACHED; 1402 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 1403 tegra_sor_super_update(sor); 1404 1405 timeout = jiffies + msecs_to_jiffies(250); 1406 1407 while (time_before(jiffies, timeout)) { 1408 value = tegra_sor_readl(sor, SOR_TEST); 1409 if ((value & SOR_TEST_ATTACHED) == 0) 1410 break; 1411 1412 usleep_range(25, 100); 1413 } 1414 1415 if ((value & SOR_TEST_ATTACHED) != 0) 1416 return -ETIMEDOUT; 1417 1418 return 0; 1419 } 1420 1421 static int tegra_sor_power_down(struct tegra_sor *sor) 1422 { 1423 unsigned long value, timeout; 1424 int err; 1425 1426 value = tegra_sor_readl(sor, SOR_PWR); 1427 value &= ~SOR_PWR_NORMAL_STATE_PU; 1428 value |= SOR_PWR_TRIGGER; 1429 tegra_sor_writel(sor, value, SOR_PWR); 1430 1431 timeout = jiffies + msecs_to_jiffies(250); 1432 1433 while (time_before(jiffies, timeout)) { 1434 value = tegra_sor_readl(sor, SOR_PWR); 1435 if ((value & SOR_PWR_TRIGGER) == 0) 1436 return 0; 1437 1438 usleep_range(25, 100); 1439 } 1440 1441 if ((value & SOR_PWR_TRIGGER) != 0) 1442 return -ETIMEDOUT; 1443 1444 /* switch to safe parent clock */ 1445 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); 1446 if (err < 0) { 1447 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); 1448 return err; 1449 } 1450 1451 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 1452 value |= SOR_PLL2_PORT_POWERDOWN; 1453 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 1454 1455 usleep_range(20, 100); 1456 1457 value = tegra_sor_readl(sor, sor->soc->regs->pll0); 1458 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR; 1459 tegra_sor_writel(sor, value, sor->soc->regs->pll0); 1460 1461 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 1462 value |= SOR_PLL2_SEQ_PLLCAPPD; 1463 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; 1464 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 1465 1466 usleep_range(20, 100); 1467 1468 return 0; 1469 } 1470 1471 static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout) 1472 { 1473 u32 value; 1474 1475 timeout = jiffies + msecs_to_jiffies(timeout); 1476 1477 while (time_before(jiffies, timeout)) { 1478 value = tegra_sor_readl(sor, SOR_CRCA); 1479 if (value & SOR_CRCA_VALID) 1480 return 0; 1481 1482 usleep_range(100, 200); 1483 } 1484 1485 return -ETIMEDOUT; 1486 } 1487 1488 static int tegra_sor_show_crc(struct seq_file *s, void *data) 1489 { 1490 struct drm_info_node *node = s->private; 1491 struct tegra_sor *sor = node->info_ent->data; 1492 struct drm_crtc *crtc = sor->output.encoder.crtc; 1493 struct drm_device *drm = node->minor->dev; 1494 int err = 0; 1495 u32 value; 1496 1497 drm_modeset_lock_all(drm); 1498 1499 if (!crtc || !crtc->state->active) { 1500 err = -EBUSY; 1501 goto unlock; 1502 } 1503 1504 value = tegra_sor_readl(sor, SOR_STATE1); 1505 value &= ~SOR_STATE_ASY_CRC_MODE_MASK; 1506 tegra_sor_writel(sor, value, SOR_STATE1); 1507 1508 value = tegra_sor_readl(sor, SOR_CRC_CNTRL); 1509 value |= SOR_CRC_CNTRL_ENABLE; 1510 tegra_sor_writel(sor, value, SOR_CRC_CNTRL); 1511 1512 value = tegra_sor_readl(sor, SOR_TEST); 1513 value &= ~SOR_TEST_CRC_POST_SERIALIZE; 1514 tegra_sor_writel(sor, value, SOR_TEST); 1515 1516 err = tegra_sor_crc_wait(sor, 100); 1517 if (err < 0) 1518 goto unlock; 1519 1520 tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA); 1521 value = tegra_sor_readl(sor, SOR_CRCB); 1522 1523 seq_printf(s, "%08x\n", value); 1524 1525 unlock: 1526 drm_modeset_unlock_all(drm); 1527 return err; 1528 } 1529 1530 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name } 1531 1532 static const struct debugfs_reg32 tegra_sor_regs[] = { 1533 DEBUGFS_REG32(SOR_CTXSW), 1534 DEBUGFS_REG32(SOR_SUPER_STATE0), 1535 DEBUGFS_REG32(SOR_SUPER_STATE1), 1536 DEBUGFS_REG32(SOR_STATE0), 1537 DEBUGFS_REG32(SOR_STATE1), 1538 DEBUGFS_REG32(SOR_HEAD_STATE0(0)), 1539 DEBUGFS_REG32(SOR_HEAD_STATE0(1)), 1540 DEBUGFS_REG32(SOR_HEAD_STATE1(0)), 1541 DEBUGFS_REG32(SOR_HEAD_STATE1(1)), 1542 DEBUGFS_REG32(SOR_HEAD_STATE2(0)), 1543 DEBUGFS_REG32(SOR_HEAD_STATE2(1)), 1544 DEBUGFS_REG32(SOR_HEAD_STATE3(0)), 1545 DEBUGFS_REG32(SOR_HEAD_STATE3(1)), 1546 DEBUGFS_REG32(SOR_HEAD_STATE4(0)), 1547 DEBUGFS_REG32(SOR_HEAD_STATE4(1)), 1548 DEBUGFS_REG32(SOR_HEAD_STATE5(0)), 1549 DEBUGFS_REG32(SOR_HEAD_STATE5(1)), 1550 DEBUGFS_REG32(SOR_CRC_CNTRL), 1551 DEBUGFS_REG32(SOR_DP_DEBUG_MVID), 1552 DEBUGFS_REG32(SOR_CLK_CNTRL), 1553 DEBUGFS_REG32(SOR_CAP), 1554 DEBUGFS_REG32(SOR_PWR), 1555 DEBUGFS_REG32(SOR_TEST), 1556 DEBUGFS_REG32(SOR_PLL0), 1557 DEBUGFS_REG32(SOR_PLL1), 1558 DEBUGFS_REG32(SOR_PLL2), 1559 DEBUGFS_REG32(SOR_PLL3), 1560 DEBUGFS_REG32(SOR_CSTM), 1561 DEBUGFS_REG32(SOR_LVDS), 1562 DEBUGFS_REG32(SOR_CRCA), 1563 DEBUGFS_REG32(SOR_CRCB), 1564 DEBUGFS_REG32(SOR_BLANK), 1565 DEBUGFS_REG32(SOR_SEQ_CTL), 1566 DEBUGFS_REG32(SOR_LANE_SEQ_CTL), 1567 DEBUGFS_REG32(SOR_SEQ_INST(0)), 1568 DEBUGFS_REG32(SOR_SEQ_INST(1)), 1569 DEBUGFS_REG32(SOR_SEQ_INST(2)), 1570 DEBUGFS_REG32(SOR_SEQ_INST(3)), 1571 DEBUGFS_REG32(SOR_SEQ_INST(4)), 1572 DEBUGFS_REG32(SOR_SEQ_INST(5)), 1573 DEBUGFS_REG32(SOR_SEQ_INST(6)), 1574 DEBUGFS_REG32(SOR_SEQ_INST(7)), 1575 DEBUGFS_REG32(SOR_SEQ_INST(8)), 1576 DEBUGFS_REG32(SOR_SEQ_INST(9)), 1577 DEBUGFS_REG32(SOR_SEQ_INST(10)), 1578 DEBUGFS_REG32(SOR_SEQ_INST(11)), 1579 DEBUGFS_REG32(SOR_SEQ_INST(12)), 1580 DEBUGFS_REG32(SOR_SEQ_INST(13)), 1581 DEBUGFS_REG32(SOR_SEQ_INST(14)), 1582 DEBUGFS_REG32(SOR_SEQ_INST(15)), 1583 DEBUGFS_REG32(SOR_PWM_DIV), 1584 DEBUGFS_REG32(SOR_PWM_CTL), 1585 DEBUGFS_REG32(SOR_VCRC_A0), 1586 DEBUGFS_REG32(SOR_VCRC_A1), 1587 DEBUGFS_REG32(SOR_VCRC_B0), 1588 DEBUGFS_REG32(SOR_VCRC_B1), 1589 DEBUGFS_REG32(SOR_CCRC_A0), 1590 DEBUGFS_REG32(SOR_CCRC_A1), 1591 DEBUGFS_REG32(SOR_CCRC_B0), 1592 DEBUGFS_REG32(SOR_CCRC_B1), 1593 DEBUGFS_REG32(SOR_EDATA_A0), 1594 DEBUGFS_REG32(SOR_EDATA_A1), 1595 DEBUGFS_REG32(SOR_EDATA_B0), 1596 DEBUGFS_REG32(SOR_EDATA_B1), 1597 DEBUGFS_REG32(SOR_COUNT_A0), 1598 DEBUGFS_REG32(SOR_COUNT_A1), 1599 DEBUGFS_REG32(SOR_COUNT_B0), 1600 DEBUGFS_REG32(SOR_COUNT_B1), 1601 DEBUGFS_REG32(SOR_DEBUG_A0), 1602 DEBUGFS_REG32(SOR_DEBUG_A1), 1603 DEBUGFS_REG32(SOR_DEBUG_B0), 1604 DEBUGFS_REG32(SOR_DEBUG_B1), 1605 DEBUGFS_REG32(SOR_TRIG), 1606 DEBUGFS_REG32(SOR_MSCHECK), 1607 DEBUGFS_REG32(SOR_XBAR_CTRL), 1608 DEBUGFS_REG32(SOR_XBAR_POL), 1609 DEBUGFS_REG32(SOR_DP_LINKCTL0), 1610 DEBUGFS_REG32(SOR_DP_LINKCTL1), 1611 DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT0), 1612 DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT1), 1613 DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT0), 1614 DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT1), 1615 DEBUGFS_REG32(SOR_LANE_PREEMPHASIS0), 1616 DEBUGFS_REG32(SOR_LANE_PREEMPHASIS1), 1617 DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS0), 1618 DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS1), 1619 DEBUGFS_REG32(SOR_LANE_POSTCURSOR0), 1620 DEBUGFS_REG32(SOR_LANE_POSTCURSOR1), 1621 DEBUGFS_REG32(SOR_DP_CONFIG0), 1622 DEBUGFS_REG32(SOR_DP_CONFIG1), 1623 DEBUGFS_REG32(SOR_DP_MN0), 1624 DEBUGFS_REG32(SOR_DP_MN1), 1625 DEBUGFS_REG32(SOR_DP_PADCTL0), 1626 DEBUGFS_REG32(SOR_DP_PADCTL1), 1627 DEBUGFS_REG32(SOR_DP_PADCTL2), 1628 DEBUGFS_REG32(SOR_DP_DEBUG0), 1629 DEBUGFS_REG32(SOR_DP_DEBUG1), 1630 DEBUGFS_REG32(SOR_DP_SPARE0), 1631 DEBUGFS_REG32(SOR_DP_SPARE1), 1632 DEBUGFS_REG32(SOR_DP_AUDIO_CTRL), 1633 DEBUGFS_REG32(SOR_DP_AUDIO_HBLANK_SYMBOLS), 1634 DEBUGFS_REG32(SOR_DP_AUDIO_VBLANK_SYMBOLS), 1635 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_HEADER), 1636 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK0), 1637 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK1), 1638 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK2), 1639 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK3), 1640 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK4), 1641 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK5), 1642 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK6), 1643 DEBUGFS_REG32(SOR_DP_TPG), 1644 DEBUGFS_REG32(SOR_DP_TPG_CONFIG), 1645 DEBUGFS_REG32(SOR_DP_LQ_CSTM0), 1646 DEBUGFS_REG32(SOR_DP_LQ_CSTM1), 1647 DEBUGFS_REG32(SOR_DP_LQ_CSTM2), 1648 }; 1649 1650 static int tegra_sor_show_regs(struct seq_file *s, void *data) 1651 { 1652 struct drm_info_node *node = s->private; 1653 struct tegra_sor *sor = node->info_ent->data; 1654 struct drm_crtc *crtc = sor->output.encoder.crtc; 1655 struct drm_device *drm = node->minor->dev; 1656 unsigned int i; 1657 int err = 0; 1658 1659 drm_modeset_lock_all(drm); 1660 1661 if (!crtc || !crtc->state->active) { 1662 err = -EBUSY; 1663 goto unlock; 1664 } 1665 1666 for (i = 0; i < ARRAY_SIZE(tegra_sor_regs); i++) { 1667 unsigned int offset = tegra_sor_regs[i].offset; 1668 1669 seq_printf(s, "%-38s %#05x %08x\n", tegra_sor_regs[i].name, 1670 offset, tegra_sor_readl(sor, offset)); 1671 } 1672 1673 unlock: 1674 drm_modeset_unlock_all(drm); 1675 return err; 1676 } 1677 1678 static const struct drm_info_list debugfs_files[] = { 1679 { "crc", tegra_sor_show_crc, 0, NULL }, 1680 { "regs", tegra_sor_show_regs, 0, NULL }, 1681 }; 1682 1683 static int tegra_sor_late_register(struct drm_connector *connector) 1684 { 1685 struct tegra_output *output = connector_to_output(connector); 1686 unsigned int i, count = ARRAY_SIZE(debugfs_files); 1687 struct drm_minor *minor = connector->dev->primary; 1688 struct dentry *root = connector->debugfs_entry; 1689 struct tegra_sor *sor = to_sor(output); 1690 int err; 1691 1692 sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), 1693 GFP_KERNEL); 1694 if (!sor->debugfs_files) 1695 return -ENOMEM; 1696 1697 for (i = 0; i < count; i++) 1698 sor->debugfs_files[i].data = sor; 1699 1700 err = drm_debugfs_create_files(sor->debugfs_files, count, root, minor); 1701 if (err < 0) 1702 goto free; 1703 1704 return 0; 1705 1706 free: 1707 kfree(sor->debugfs_files); 1708 sor->debugfs_files = NULL; 1709 1710 return err; 1711 } 1712 1713 static void tegra_sor_early_unregister(struct drm_connector *connector) 1714 { 1715 struct tegra_output *output = connector_to_output(connector); 1716 unsigned int count = ARRAY_SIZE(debugfs_files); 1717 struct tegra_sor *sor = to_sor(output); 1718 1719 drm_debugfs_remove_files(sor->debugfs_files, count, 1720 connector->dev->primary); 1721 kfree(sor->debugfs_files); 1722 sor->debugfs_files = NULL; 1723 } 1724 1725 static void tegra_sor_connector_reset(struct drm_connector *connector) 1726 { 1727 struct tegra_sor_state *state; 1728 1729 state = kzalloc(sizeof(*state), GFP_KERNEL); 1730 if (!state) 1731 return; 1732 1733 if (connector->state) { 1734 __drm_atomic_helper_connector_destroy_state(connector->state); 1735 kfree(connector->state); 1736 } 1737 1738 __drm_atomic_helper_connector_reset(connector, &state->base); 1739 } 1740 1741 static enum drm_connector_status 1742 tegra_sor_connector_detect(struct drm_connector *connector, bool force) 1743 { 1744 struct tegra_output *output = connector_to_output(connector); 1745 struct tegra_sor *sor = to_sor(output); 1746 1747 if (sor->aux) 1748 return drm_dp_aux_detect(sor->aux); 1749 1750 return tegra_output_connector_detect(connector, force); 1751 } 1752 1753 static struct drm_connector_state * 1754 tegra_sor_connector_duplicate_state(struct drm_connector *connector) 1755 { 1756 struct tegra_sor_state *state = to_sor_state(connector->state); 1757 struct tegra_sor_state *copy; 1758 1759 copy = kmemdup(state, sizeof(*state), GFP_KERNEL); 1760 if (!copy) 1761 return NULL; 1762 1763 __drm_atomic_helper_connector_duplicate_state(connector, ©->base); 1764 1765 return ©->base; 1766 } 1767 1768 static const struct drm_connector_funcs tegra_sor_connector_funcs = { 1769 .reset = tegra_sor_connector_reset, 1770 .detect = tegra_sor_connector_detect, 1771 .fill_modes = drm_helper_probe_single_connector_modes, 1772 .destroy = tegra_output_connector_destroy, 1773 .atomic_duplicate_state = tegra_sor_connector_duplicate_state, 1774 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1775 .late_register = tegra_sor_late_register, 1776 .early_unregister = tegra_sor_early_unregister, 1777 }; 1778 1779 static int tegra_sor_connector_get_modes(struct drm_connector *connector) 1780 { 1781 struct tegra_output *output = connector_to_output(connector); 1782 struct tegra_sor *sor = to_sor(output); 1783 int err; 1784 1785 if (sor->aux) 1786 drm_dp_aux_enable(sor->aux); 1787 1788 err = tegra_output_connector_get_modes(connector); 1789 1790 if (sor->aux) 1791 drm_dp_aux_disable(sor->aux); 1792 1793 return err; 1794 } 1795 1796 static enum drm_mode_status 1797 tegra_sor_connector_mode_valid(struct drm_connector *connector, 1798 struct drm_display_mode *mode) 1799 { 1800 return MODE_OK; 1801 } 1802 1803 static const struct drm_connector_helper_funcs tegra_sor_connector_helper_funcs = { 1804 .get_modes = tegra_sor_connector_get_modes, 1805 .mode_valid = tegra_sor_connector_mode_valid, 1806 }; 1807 1808 static const struct drm_encoder_funcs tegra_sor_encoder_funcs = { 1809 .destroy = tegra_output_encoder_destroy, 1810 }; 1811 1812 static int 1813 tegra_sor_encoder_atomic_check(struct drm_encoder *encoder, 1814 struct drm_crtc_state *crtc_state, 1815 struct drm_connector_state *conn_state) 1816 { 1817 struct tegra_output *output = encoder_to_output(encoder); 1818 struct tegra_sor_state *state = to_sor_state(conn_state); 1819 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc); 1820 unsigned long pclk = crtc_state->mode.clock * 1000; 1821 struct tegra_sor *sor = to_sor(output); 1822 struct drm_display_info *info; 1823 int err; 1824 1825 info = &output->connector.display_info; 1826 1827 /* 1828 * For HBR2 modes, the SOR brick needs to use the x20 multiplier, so 1829 * the pixel clock must be corrected accordingly. 1830 */ 1831 if (pclk >= 340000000) { 1832 state->link_speed = 20; 1833 state->pclk = pclk / 2; 1834 } else { 1835 state->link_speed = 10; 1836 state->pclk = pclk; 1837 } 1838 1839 err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent, 1840 pclk, 0); 1841 if (err < 0) { 1842 dev_err(output->dev, "failed to setup CRTC state: %d\n", err); 1843 return err; 1844 } 1845 1846 switch (info->bpc) { 1847 case 8: 1848 case 6: 1849 state->bpc = info->bpc; 1850 break; 1851 1852 default: 1853 DRM_DEBUG_KMS("%u bits-per-color not supported\n", info->bpc); 1854 state->bpc = 8; 1855 break; 1856 } 1857 1858 return 0; 1859 } 1860 1861 static inline u32 tegra_sor_hdmi_subpack(const u8 *ptr, size_t size) 1862 { 1863 u32 value = 0; 1864 size_t i; 1865 1866 for (i = size; i > 0; i--) 1867 value = (value << 8) | ptr[i - 1]; 1868 1869 return value; 1870 } 1871 1872 static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor, 1873 const void *data, size_t size) 1874 { 1875 const u8 *ptr = data; 1876 unsigned long offset; 1877 size_t i, j; 1878 u32 value; 1879 1880 switch (ptr[0]) { 1881 case HDMI_INFOFRAME_TYPE_AVI: 1882 offset = SOR_HDMI_AVI_INFOFRAME_HEADER; 1883 break; 1884 1885 case HDMI_INFOFRAME_TYPE_AUDIO: 1886 offset = SOR_HDMI_AUDIO_INFOFRAME_HEADER; 1887 break; 1888 1889 case HDMI_INFOFRAME_TYPE_VENDOR: 1890 offset = SOR_HDMI_VSI_INFOFRAME_HEADER; 1891 break; 1892 1893 default: 1894 dev_err(sor->dev, "unsupported infoframe type: %02x\n", 1895 ptr[0]); 1896 return; 1897 } 1898 1899 value = INFOFRAME_HEADER_TYPE(ptr[0]) | 1900 INFOFRAME_HEADER_VERSION(ptr[1]) | 1901 INFOFRAME_HEADER_LEN(ptr[2]); 1902 tegra_sor_writel(sor, value, offset); 1903 offset++; 1904 1905 /* 1906 * Each subpack contains 7 bytes, divided into: 1907 * - subpack_low: bytes 0 - 3 1908 * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00) 1909 */ 1910 for (i = 3, j = 0; i < size; i += 7, j += 8) { 1911 size_t rem = size - i, num = min_t(size_t, rem, 4); 1912 1913 value = tegra_sor_hdmi_subpack(&ptr[i], num); 1914 tegra_sor_writel(sor, value, offset++); 1915 1916 num = min_t(size_t, rem - num, 3); 1917 1918 value = tegra_sor_hdmi_subpack(&ptr[i + 4], num); 1919 tegra_sor_writel(sor, value, offset++); 1920 } 1921 } 1922 1923 static int 1924 tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor, 1925 const struct drm_display_mode *mode) 1926 { 1927 u8 buffer[HDMI_INFOFRAME_SIZE(AVI)]; 1928 struct hdmi_avi_infoframe frame; 1929 u32 value; 1930 int err; 1931 1932 /* disable AVI infoframe */ 1933 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); 1934 value &= ~INFOFRAME_CTRL_SINGLE; 1935 value &= ~INFOFRAME_CTRL_OTHER; 1936 value &= ~INFOFRAME_CTRL_ENABLE; 1937 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); 1938 1939 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, 1940 &sor->output.connector, mode); 1941 if (err < 0) { 1942 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); 1943 return err; 1944 } 1945 1946 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 1947 if (err < 0) { 1948 dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err); 1949 return err; 1950 } 1951 1952 tegra_sor_hdmi_write_infopack(sor, buffer, err); 1953 1954 /* enable AVI infoframe */ 1955 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); 1956 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE; 1957 value |= INFOFRAME_CTRL_ENABLE; 1958 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); 1959 1960 return 0; 1961 } 1962 1963 static void tegra_sor_write_eld(struct tegra_sor *sor) 1964 { 1965 size_t length = drm_eld_size(sor->output.connector.eld), i; 1966 1967 for (i = 0; i < length; i++) 1968 tegra_sor_writel(sor, i << 8 | sor->output.connector.eld[i], 1969 SOR_AUDIO_HDA_ELD_BUFWR); 1970 1971 /* 1972 * The HDA codec will always report an ELD buffer size of 96 bytes and 1973 * the HDA codec driver will check that each byte read from the buffer 1974 * is valid. Therefore every byte must be written, even if no 96 bytes 1975 * were parsed from EDID. 1976 */ 1977 for (i = length; i < 96; i++) 1978 tegra_sor_writel(sor, i << 8 | 0, SOR_AUDIO_HDA_ELD_BUFWR); 1979 } 1980 1981 static void tegra_sor_audio_prepare(struct tegra_sor *sor) 1982 { 1983 u32 value; 1984 1985 /* 1986 * Enable and unmask the HDA codec SCRATCH0 register interrupt. This 1987 * is used for interoperability between the HDA codec driver and the 1988 * HDMI/DP driver. 1989 */ 1990 value = SOR_INT_CODEC_SCRATCH1 | SOR_INT_CODEC_SCRATCH0; 1991 tegra_sor_writel(sor, value, SOR_INT_ENABLE); 1992 tegra_sor_writel(sor, value, SOR_INT_MASK); 1993 1994 tegra_sor_write_eld(sor); 1995 1996 value = SOR_AUDIO_HDA_PRESENSE_ELDV | SOR_AUDIO_HDA_PRESENSE_PD; 1997 tegra_sor_writel(sor, value, SOR_AUDIO_HDA_PRESENSE); 1998 } 1999 2000 static void tegra_sor_audio_unprepare(struct tegra_sor *sor) 2001 { 2002 tegra_sor_writel(sor, 0, SOR_AUDIO_HDA_PRESENSE); 2003 tegra_sor_writel(sor, 0, SOR_INT_MASK); 2004 tegra_sor_writel(sor, 0, SOR_INT_ENABLE); 2005 } 2006 2007 static void tegra_sor_audio_enable(struct tegra_sor *sor) 2008 { 2009 u32 value; 2010 2011 value = tegra_sor_readl(sor, SOR_AUDIO_CNTRL); 2012 2013 /* select HDA audio input */ 2014 value &= ~SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_MASK); 2015 value |= SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_HDA); 2016 2017 /* inject null samples */ 2018 if (sor->format.channels != 2) 2019 value &= ~SOR_AUDIO_CNTRL_INJECT_NULLSMPL; 2020 else 2021 value |= SOR_AUDIO_CNTRL_INJECT_NULLSMPL; 2022 2023 value |= SOR_AUDIO_CNTRL_AFIFO_FLUSH; 2024 2025 tegra_sor_writel(sor, value, SOR_AUDIO_CNTRL); 2026 2027 /* enable advertising HBR capability */ 2028 tegra_sor_writel(sor, SOR_AUDIO_SPARE_HBR_ENABLE, SOR_AUDIO_SPARE); 2029 } 2030 2031 static int tegra_sor_hdmi_enable_audio_infoframe(struct tegra_sor *sor) 2032 { 2033 u8 buffer[HDMI_INFOFRAME_SIZE(AUDIO)]; 2034 struct hdmi_audio_infoframe frame; 2035 u32 value; 2036 int err; 2037 2038 err = hdmi_audio_infoframe_init(&frame); 2039 if (err < 0) { 2040 dev_err(sor->dev, "failed to setup audio infoframe: %d\n", err); 2041 return err; 2042 } 2043 2044 frame.channels = sor->format.channels; 2045 2046 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer)); 2047 if (err < 0) { 2048 dev_err(sor->dev, "failed to pack audio infoframe: %d\n", err); 2049 return err; 2050 } 2051 2052 tegra_sor_hdmi_write_infopack(sor, buffer, err); 2053 2054 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); 2055 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE; 2056 value |= INFOFRAME_CTRL_ENABLE; 2057 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); 2058 2059 return 0; 2060 } 2061 2062 static void tegra_sor_hdmi_audio_enable(struct tegra_sor *sor) 2063 { 2064 u32 value; 2065 2066 tegra_sor_audio_enable(sor); 2067 2068 tegra_sor_writel(sor, 0, SOR_HDMI_ACR_CTRL); 2069 2070 value = SOR_HDMI_SPARE_ACR_PRIORITY_HIGH | 2071 SOR_HDMI_SPARE_CTS_RESET(1) | 2072 SOR_HDMI_SPARE_HW_CTS_ENABLE; 2073 tegra_sor_writel(sor, value, SOR_HDMI_SPARE); 2074 2075 /* enable HW CTS */ 2076 value = SOR_HDMI_ACR_SUBPACK_LOW_SB1(0); 2077 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_LOW); 2078 2079 /* allow packet to be sent */ 2080 value = SOR_HDMI_ACR_SUBPACK_HIGH_ENABLE; 2081 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_HIGH); 2082 2083 /* reset N counter and enable lookup */ 2084 value = SOR_HDMI_AUDIO_N_RESET | SOR_HDMI_AUDIO_N_LOOKUP; 2085 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N); 2086 2087 value = (24000 * 4096) / (128 * sor->format.sample_rate / 1000); 2088 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0320); 2089 tegra_sor_writel(sor, 4096, SOR_AUDIO_NVAL_0320); 2090 2091 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0441); 2092 tegra_sor_writel(sor, 4704, SOR_AUDIO_NVAL_0441); 2093 2094 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0882); 2095 tegra_sor_writel(sor, 9408, SOR_AUDIO_NVAL_0882); 2096 2097 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_1764); 2098 tegra_sor_writel(sor, 18816, SOR_AUDIO_NVAL_1764); 2099 2100 value = (24000 * 6144) / (128 * sor->format.sample_rate / 1000); 2101 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0480); 2102 tegra_sor_writel(sor, 6144, SOR_AUDIO_NVAL_0480); 2103 2104 value = (24000 * 12288) / (128 * sor->format.sample_rate / 1000); 2105 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0960); 2106 tegra_sor_writel(sor, 12288, SOR_AUDIO_NVAL_0960); 2107 2108 value = (24000 * 24576) / (128 * sor->format.sample_rate / 1000); 2109 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_1920); 2110 tegra_sor_writel(sor, 24576, SOR_AUDIO_NVAL_1920); 2111 2112 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_N); 2113 value &= ~SOR_HDMI_AUDIO_N_RESET; 2114 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N); 2115 2116 tegra_sor_hdmi_enable_audio_infoframe(sor); 2117 } 2118 2119 static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor) 2120 { 2121 u32 value; 2122 2123 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); 2124 value &= ~INFOFRAME_CTRL_ENABLE; 2125 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); 2126 } 2127 2128 static void tegra_sor_hdmi_audio_disable(struct tegra_sor *sor) 2129 { 2130 tegra_sor_hdmi_disable_audio_infoframe(sor); 2131 } 2132 2133 static struct tegra_sor_hdmi_settings * 2134 tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency) 2135 { 2136 unsigned int i; 2137 2138 for (i = 0; i < sor->num_settings; i++) 2139 if (frequency <= sor->settings[i].frequency) 2140 return &sor->settings[i]; 2141 2142 return NULL; 2143 } 2144 2145 static void tegra_sor_hdmi_disable_scrambling(struct tegra_sor *sor) 2146 { 2147 u32 value; 2148 2149 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); 2150 value &= ~SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4; 2151 value &= ~SOR_HDMI2_CTRL_SCRAMBLE; 2152 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); 2153 } 2154 2155 static void tegra_sor_hdmi_scdc_disable(struct tegra_sor *sor) 2156 { 2157 struct i2c_adapter *ddc = sor->output.ddc; 2158 2159 drm_scdc_set_high_tmds_clock_ratio(ddc, false); 2160 drm_scdc_set_scrambling(ddc, false); 2161 2162 tegra_sor_hdmi_disable_scrambling(sor); 2163 } 2164 2165 static void tegra_sor_hdmi_scdc_stop(struct tegra_sor *sor) 2166 { 2167 if (sor->scdc_enabled) { 2168 cancel_delayed_work_sync(&sor->scdc); 2169 tegra_sor_hdmi_scdc_disable(sor); 2170 } 2171 } 2172 2173 static void tegra_sor_hdmi_enable_scrambling(struct tegra_sor *sor) 2174 { 2175 u32 value; 2176 2177 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); 2178 value |= SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4; 2179 value |= SOR_HDMI2_CTRL_SCRAMBLE; 2180 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); 2181 } 2182 2183 static void tegra_sor_hdmi_scdc_enable(struct tegra_sor *sor) 2184 { 2185 struct i2c_adapter *ddc = sor->output.ddc; 2186 2187 drm_scdc_set_high_tmds_clock_ratio(ddc, true); 2188 drm_scdc_set_scrambling(ddc, true); 2189 2190 tegra_sor_hdmi_enable_scrambling(sor); 2191 } 2192 2193 static void tegra_sor_hdmi_scdc_work(struct work_struct *work) 2194 { 2195 struct tegra_sor *sor = container_of(work, struct tegra_sor, scdc.work); 2196 struct i2c_adapter *ddc = sor->output.ddc; 2197 2198 if (!drm_scdc_get_scrambling_status(ddc)) { 2199 DRM_DEBUG_KMS("SCDC not scrambled\n"); 2200 tegra_sor_hdmi_scdc_enable(sor); 2201 } 2202 2203 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000)); 2204 } 2205 2206 static void tegra_sor_hdmi_scdc_start(struct tegra_sor *sor) 2207 { 2208 struct drm_scdc *scdc = &sor->output.connector.display_info.hdmi.scdc; 2209 struct drm_display_mode *mode; 2210 2211 mode = &sor->output.encoder.crtc->state->adjusted_mode; 2212 2213 if (mode->clock >= 340000 && scdc->supported) { 2214 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000)); 2215 tegra_sor_hdmi_scdc_enable(sor); 2216 sor->scdc_enabled = true; 2217 } 2218 } 2219 2220 static void tegra_sor_hdmi_disable(struct drm_encoder *encoder) 2221 { 2222 struct tegra_output *output = encoder_to_output(encoder); 2223 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 2224 struct tegra_sor *sor = to_sor(output); 2225 u32 value; 2226 int err; 2227 2228 tegra_sor_audio_unprepare(sor); 2229 tegra_sor_hdmi_scdc_stop(sor); 2230 2231 err = tegra_sor_detach(sor); 2232 if (err < 0) 2233 dev_err(sor->dev, "failed to detach SOR: %d\n", err); 2234 2235 tegra_sor_writel(sor, 0, SOR_STATE1); 2236 tegra_sor_update(sor); 2237 2238 /* disable display to SOR clock */ 2239 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 2240 2241 if (!sor->soc->has_nvdisplay) 2242 value &= ~SOR1_TIMING_CYA; 2243 2244 value &= ~SOR_ENABLE(sor->index); 2245 2246 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 2247 2248 tegra_dc_commit(dc); 2249 2250 err = tegra_sor_power_down(sor); 2251 if (err < 0) 2252 dev_err(sor->dev, "failed to power down SOR: %d\n", err); 2253 2254 err = tegra_io_pad_power_disable(sor->pad); 2255 if (err < 0) 2256 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err); 2257 2258 pm_runtime_put(sor->dev); 2259 } 2260 2261 static void tegra_sor_hdmi_enable(struct drm_encoder *encoder) 2262 { 2263 struct tegra_output *output = encoder_to_output(encoder); 2264 unsigned int h_ref_to_sync = 1, pulse_start, max_ac; 2265 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 2266 struct tegra_sor_hdmi_settings *settings; 2267 struct tegra_sor *sor = to_sor(output); 2268 struct tegra_sor_state *state; 2269 struct drm_display_mode *mode; 2270 unsigned long rate, pclk; 2271 unsigned int div, i; 2272 u32 value; 2273 int err; 2274 2275 state = to_sor_state(output->connector.state); 2276 mode = &encoder->crtc->state->adjusted_mode; 2277 pclk = mode->clock * 1000; 2278 2279 pm_runtime_get_sync(sor->dev); 2280 2281 /* switch to safe parent clock */ 2282 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); 2283 if (err < 0) { 2284 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); 2285 return; 2286 } 2287 2288 div = clk_get_rate(sor->clk) / 1000000 * 4; 2289 2290 err = tegra_io_pad_power_enable(sor->pad); 2291 if (err < 0) 2292 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err); 2293 2294 usleep_range(20, 100); 2295 2296 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 2297 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; 2298 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 2299 2300 usleep_range(20, 100); 2301 2302 value = tegra_sor_readl(sor, sor->soc->regs->pll3); 2303 value &= ~SOR_PLL3_PLL_VDD_MODE_3V3; 2304 tegra_sor_writel(sor, value, sor->soc->regs->pll3); 2305 2306 value = tegra_sor_readl(sor, sor->soc->regs->pll0); 2307 value &= ~SOR_PLL0_VCOPD; 2308 value &= ~SOR_PLL0_PWR; 2309 tegra_sor_writel(sor, value, sor->soc->regs->pll0); 2310 2311 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 2312 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; 2313 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 2314 2315 usleep_range(200, 400); 2316 2317 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 2318 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; 2319 value &= ~SOR_PLL2_PORT_POWERDOWN; 2320 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 2321 2322 usleep_range(20, 100); 2323 2324 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 2325 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | 2326 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2; 2327 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 2328 2329 while (true) { 2330 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 2331 if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0) 2332 break; 2333 2334 usleep_range(250, 1000); 2335 } 2336 2337 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | 2338 SOR_LANE_SEQ_CTL_POWER_STATE_UP | SOR_LANE_SEQ_CTL_DELAY(5); 2339 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); 2340 2341 while (true) { 2342 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 2343 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) 2344 break; 2345 2346 usleep_range(250, 1000); 2347 } 2348 2349 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 2350 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; 2351 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; 2352 2353 if (mode->clock < 340000) { 2354 DRM_DEBUG_KMS("setting 2.7 GHz link speed\n"); 2355 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70; 2356 } else { 2357 DRM_DEBUG_KMS("setting 5.4 GHz link speed\n"); 2358 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40; 2359 } 2360 2361 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; 2362 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 2363 2364 /* SOR pad PLL stabilization time */ 2365 usleep_range(250, 1000); 2366 2367 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); 2368 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; 2369 value |= SOR_DP_LINKCTL_LANE_COUNT(4); 2370 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); 2371 2372 value = tegra_sor_readl(sor, SOR_DP_SPARE0); 2373 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE; 2374 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; 2375 value &= ~SOR_DP_SPARE_SEQ_ENABLE; 2376 value &= ~SOR_DP_SPARE_MACRO_SOR_CLK; 2377 tegra_sor_writel(sor, value, SOR_DP_SPARE0); 2378 2379 value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) | 2380 SOR_SEQ_CTL_PD_PC(8) | SOR_SEQ_CTL_PD_PC_ALT(8); 2381 tegra_sor_writel(sor, value, SOR_SEQ_CTL); 2382 2383 value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT | 2384 SOR_SEQ_INST_WAIT_VSYNC | SOR_SEQ_INST_WAIT(1); 2385 tegra_sor_writel(sor, value, SOR_SEQ_INST(0)); 2386 tegra_sor_writel(sor, value, SOR_SEQ_INST(8)); 2387 2388 if (!sor->soc->has_nvdisplay) { 2389 /* program the reference clock */ 2390 value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div); 2391 tegra_sor_writel(sor, value, SOR_REFCLK); 2392 } 2393 2394 /* XXX not in TRM */ 2395 for (value = 0, i = 0; i < 5; i++) 2396 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) | 2397 SOR_XBAR_CTRL_LINK1_XSEL(i, i); 2398 2399 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); 2400 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); 2401 2402 /* 2403 * Switch the pad clock to the DP clock. Note that we cannot actually 2404 * do this because Tegra186 and later don't support clk_set_parent() 2405 * on the sorX_pad_clkout clocks. We already do the equivalent above 2406 * using the DP_CLK_SEL mux of the SOR_CLK_CNTRL register. 2407 */ 2408 #if 0 2409 err = clk_set_parent(sor->clk_pad, sor->clk_dp); 2410 if (err < 0) { 2411 dev_err(sor->dev, "failed to select pad parent clock: %d\n", 2412 err); 2413 return; 2414 } 2415 #endif 2416 2417 /* switch the SOR clock to the pad clock */ 2418 err = tegra_sor_set_parent_clock(sor, sor->clk_pad); 2419 if (err < 0) { 2420 dev_err(sor->dev, "failed to select SOR parent clock: %d\n", 2421 err); 2422 return; 2423 } 2424 2425 /* switch the output clock to the parent pixel clock */ 2426 err = clk_set_parent(sor->clk, sor->clk_parent); 2427 if (err < 0) { 2428 dev_err(sor->dev, "failed to select output parent clock: %d\n", 2429 err); 2430 return; 2431 } 2432 2433 /* adjust clock rate for HDMI 2.0 modes */ 2434 rate = clk_get_rate(sor->clk_parent); 2435 2436 if (mode->clock >= 340000) 2437 rate /= 2; 2438 2439 DRM_DEBUG_KMS("setting clock to %lu Hz, mode: %lu Hz\n", rate, pclk); 2440 2441 clk_set_rate(sor->clk, rate); 2442 2443 if (!sor->soc->has_nvdisplay) { 2444 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe); 2445 2446 /* XXX is this the proper check? */ 2447 if (mode->clock < 75000) 2448 value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED; 2449 2450 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL); 2451 } 2452 2453 max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32; 2454 2455 value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) | 2456 SOR_HDMI_CTRL_AUDIO_LAYOUT | SOR_HDMI_CTRL_REKEY(SOR_REKEY); 2457 tegra_sor_writel(sor, value, SOR_HDMI_CTRL); 2458 2459 if (!dc->soc->has_nvdisplay) { 2460 /* H_PULSE2 setup */ 2461 pulse_start = h_ref_to_sync + 2462 (mode->hsync_end - mode->hsync_start) + 2463 (mode->htotal - mode->hsync_end) - 10; 2464 2465 value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE | 2466 PULSE_POLARITY_HIGH | PULSE_MODE_NORMAL; 2467 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL); 2468 2469 value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start); 2470 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A); 2471 2472 value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0); 2473 value |= H_PULSE2_ENABLE; 2474 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0); 2475 } 2476 2477 /* infoframe setup */ 2478 err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode); 2479 if (err < 0) 2480 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); 2481 2482 /* XXX HDMI audio support not implemented yet */ 2483 tegra_sor_hdmi_disable_audio_infoframe(sor); 2484 2485 /* use single TMDS protocol */ 2486 value = tegra_sor_readl(sor, SOR_STATE1); 2487 value &= ~SOR_STATE_ASY_PROTOCOL_MASK; 2488 value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A; 2489 tegra_sor_writel(sor, value, SOR_STATE1); 2490 2491 /* power up pad calibration */ 2492 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 2493 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; 2494 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 2495 2496 /* production settings */ 2497 settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000); 2498 if (!settings) { 2499 dev_err(sor->dev, "no settings for pixel clock %d Hz\n", 2500 mode->clock * 1000); 2501 return; 2502 } 2503 2504 value = tegra_sor_readl(sor, sor->soc->regs->pll0); 2505 value &= ~SOR_PLL0_ICHPMP_MASK; 2506 value &= ~SOR_PLL0_FILTER_MASK; 2507 value &= ~SOR_PLL0_VCOCAP_MASK; 2508 value |= SOR_PLL0_ICHPMP(settings->ichpmp); 2509 value |= SOR_PLL0_FILTER(settings->filter); 2510 value |= SOR_PLL0_VCOCAP(settings->vcocap); 2511 tegra_sor_writel(sor, value, sor->soc->regs->pll0); 2512 2513 /* XXX not in TRM */ 2514 value = tegra_sor_readl(sor, sor->soc->regs->pll1); 2515 value &= ~SOR_PLL1_LOADADJ_MASK; 2516 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; 2517 value |= SOR_PLL1_LOADADJ(settings->loadadj); 2518 value |= SOR_PLL1_TMDS_TERMADJ(settings->tmds_termadj); 2519 value |= SOR_PLL1_TMDS_TERM; 2520 tegra_sor_writel(sor, value, sor->soc->regs->pll1); 2521 2522 value = tegra_sor_readl(sor, sor->soc->regs->pll3); 2523 value &= ~SOR_PLL3_BG_TEMP_COEF_MASK; 2524 value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK; 2525 value &= ~SOR_PLL3_AVDD10_LEVEL_MASK; 2526 value &= ~SOR_PLL3_AVDD14_LEVEL_MASK; 2527 value |= SOR_PLL3_BG_TEMP_COEF(settings->bg_temp_coef); 2528 value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref_level); 2529 value |= SOR_PLL3_AVDD10_LEVEL(settings->avdd10_level); 2530 value |= SOR_PLL3_AVDD14_LEVEL(settings->avdd14_level); 2531 tegra_sor_writel(sor, value, sor->soc->regs->pll3); 2532 2533 value = settings->drive_current[3] << 24 | 2534 settings->drive_current[2] << 16 | 2535 settings->drive_current[1] << 8 | 2536 settings->drive_current[0] << 0; 2537 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); 2538 2539 value = settings->preemphasis[3] << 24 | 2540 settings->preemphasis[2] << 16 | 2541 settings->preemphasis[1] << 8 | 2542 settings->preemphasis[0] << 0; 2543 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); 2544 2545 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 2546 value &= ~SOR_DP_PADCTL_TX_PU_MASK; 2547 value |= SOR_DP_PADCTL_TX_PU_ENABLE; 2548 value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value); 2549 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 2550 2551 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2); 2552 value &= ~SOR_DP_PADCTL_SPAREPLL_MASK; 2553 value |= SOR_DP_PADCTL_SPAREPLL(settings->sparepll); 2554 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2); 2555 2556 /* power down pad calibration */ 2557 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 2558 value |= SOR_DP_PADCTL_PAD_CAL_PD; 2559 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 2560 2561 if (!dc->soc->has_nvdisplay) { 2562 /* miscellaneous display controller settings */ 2563 value = VSYNC_H_POSITION(1); 2564 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS); 2565 } 2566 2567 value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL); 2568 value &= ~DITHER_CONTROL_MASK; 2569 value &= ~BASE_COLOR_SIZE_MASK; 2570 2571 switch (state->bpc) { 2572 case 6: 2573 value |= BASE_COLOR_SIZE_666; 2574 break; 2575 2576 case 8: 2577 value |= BASE_COLOR_SIZE_888; 2578 break; 2579 2580 case 10: 2581 value |= BASE_COLOR_SIZE_101010; 2582 break; 2583 2584 case 12: 2585 value |= BASE_COLOR_SIZE_121212; 2586 break; 2587 2588 default: 2589 WARN(1, "%u bits-per-color not supported\n", state->bpc); 2590 value |= BASE_COLOR_SIZE_888; 2591 break; 2592 } 2593 2594 tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL); 2595 2596 /* XXX set display head owner */ 2597 value = tegra_sor_readl(sor, SOR_STATE1); 2598 value &= ~SOR_STATE_ASY_OWNER_MASK; 2599 value |= SOR_STATE_ASY_OWNER(1 + dc->pipe); 2600 tegra_sor_writel(sor, value, SOR_STATE1); 2601 2602 err = tegra_sor_power_up(sor, 250); 2603 if (err < 0) 2604 dev_err(sor->dev, "failed to power up SOR: %d\n", err); 2605 2606 /* configure dynamic range of output */ 2607 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); 2608 value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK; 2609 value &= ~SOR_HEAD_STATE_DYNRANGE_MASK; 2610 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); 2611 2612 /* configure colorspace */ 2613 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); 2614 value &= ~SOR_HEAD_STATE_COLORSPACE_MASK; 2615 value |= SOR_HEAD_STATE_COLORSPACE_RGB; 2616 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); 2617 2618 tegra_sor_mode_set(sor, mode, state); 2619 2620 tegra_sor_update(sor); 2621 2622 /* program preamble timing in SOR (XXX) */ 2623 value = tegra_sor_readl(sor, SOR_DP_SPARE0); 2624 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE; 2625 tegra_sor_writel(sor, value, SOR_DP_SPARE0); 2626 2627 err = tegra_sor_attach(sor); 2628 if (err < 0) 2629 dev_err(sor->dev, "failed to attach SOR: %d\n", err); 2630 2631 /* enable display to SOR clock and generate HDMI preamble */ 2632 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 2633 2634 if (!sor->soc->has_nvdisplay) 2635 value |= SOR1_TIMING_CYA; 2636 2637 value |= SOR_ENABLE(sor->index); 2638 2639 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 2640 2641 if (dc->soc->has_nvdisplay) { 2642 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); 2643 value &= ~PROTOCOL_MASK; 2644 value |= PROTOCOL_SINGLE_TMDS_A; 2645 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); 2646 } 2647 2648 tegra_dc_commit(dc); 2649 2650 err = tegra_sor_wakeup(sor); 2651 if (err < 0) 2652 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err); 2653 2654 tegra_sor_hdmi_scdc_start(sor); 2655 tegra_sor_audio_prepare(sor); 2656 } 2657 2658 static const struct drm_encoder_helper_funcs tegra_sor_hdmi_helpers = { 2659 .disable = tegra_sor_hdmi_disable, 2660 .enable = tegra_sor_hdmi_enable, 2661 .atomic_check = tegra_sor_encoder_atomic_check, 2662 }; 2663 2664 static void tegra_sor_dp_disable(struct drm_encoder *encoder) 2665 { 2666 struct tegra_output *output = encoder_to_output(encoder); 2667 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 2668 struct tegra_sor *sor = to_sor(output); 2669 u32 value; 2670 int err; 2671 2672 if (output->panel) 2673 drm_panel_disable(output->panel); 2674 2675 /* 2676 * Do not attempt to power down a DP link if we're not connected since 2677 * the AUX transactions would just be timing out. 2678 */ 2679 if (output->connector.status != connector_status_disconnected) { 2680 err = drm_dp_link_power_down(sor->aux, &sor->link); 2681 if (err < 0) 2682 dev_err(sor->dev, "failed to power down link: %d\n", 2683 err); 2684 } 2685 2686 err = tegra_sor_detach(sor); 2687 if (err < 0) 2688 dev_err(sor->dev, "failed to detach SOR: %d\n", err); 2689 2690 tegra_sor_writel(sor, 0, SOR_STATE1); 2691 tegra_sor_update(sor); 2692 2693 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 2694 value &= ~SOR_ENABLE(sor->index); 2695 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 2696 tegra_dc_commit(dc); 2697 2698 value = tegra_sor_readl(sor, SOR_STATE1); 2699 value &= ~SOR_STATE_ASY_PROTOCOL_MASK; 2700 value &= ~SOR_STATE_ASY_SUBOWNER_MASK; 2701 value &= ~SOR_STATE_ASY_OWNER_MASK; 2702 tegra_sor_writel(sor, value, SOR_STATE1); 2703 tegra_sor_update(sor); 2704 2705 /* switch to safe parent clock */ 2706 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); 2707 if (err < 0) 2708 dev_err(sor->dev, "failed to set safe clock: %d\n", err); 2709 2710 err = tegra_sor_power_down(sor); 2711 if (err < 0) 2712 dev_err(sor->dev, "failed to power down SOR: %d\n", err); 2713 2714 err = tegra_io_pad_power_disable(sor->pad); 2715 if (err < 0) 2716 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err); 2717 2718 err = drm_dp_aux_disable(sor->aux); 2719 if (err < 0) 2720 dev_err(sor->dev, "failed disable DPAUX: %d\n", err); 2721 2722 if (output->panel) 2723 drm_panel_unprepare(output->panel); 2724 2725 pm_runtime_put(sor->dev); 2726 } 2727 2728 static void tegra_sor_dp_enable(struct drm_encoder *encoder) 2729 { 2730 struct tegra_output *output = encoder_to_output(encoder); 2731 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 2732 struct tegra_sor *sor = to_sor(output); 2733 struct tegra_sor_config config; 2734 struct tegra_sor_state *state; 2735 struct drm_display_mode *mode; 2736 struct drm_display_info *info; 2737 unsigned int i; 2738 u32 value; 2739 int err; 2740 2741 state = to_sor_state(output->connector.state); 2742 mode = &encoder->crtc->state->adjusted_mode; 2743 info = &output->connector.display_info; 2744 2745 pm_runtime_get_sync(sor->dev); 2746 2747 /* switch to safe parent clock */ 2748 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); 2749 if (err < 0) 2750 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); 2751 2752 err = tegra_io_pad_power_enable(sor->pad); 2753 if (err < 0) 2754 dev_err(sor->dev, "failed to power on LVDS rail: %d\n", err); 2755 2756 usleep_range(20, 100); 2757 2758 err = drm_dp_aux_enable(sor->aux); 2759 if (err < 0) 2760 dev_err(sor->dev, "failed to enable DPAUX: %d\n", err); 2761 2762 err = drm_dp_link_probe(sor->aux, &sor->link); 2763 if (err < 0) 2764 dev_err(sor->dev, "failed to probe DP link: %d\n", err); 2765 2766 tegra_sor_filter_rates(sor); 2767 2768 err = drm_dp_link_choose(&sor->link, mode, info); 2769 if (err < 0) 2770 dev_err(sor->dev, "failed to choose link: %d\n", err); 2771 2772 if (output->panel) 2773 drm_panel_prepare(output->panel); 2774 2775 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 2776 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; 2777 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 2778 2779 usleep_range(20, 40); 2780 2781 value = tegra_sor_readl(sor, sor->soc->regs->pll3); 2782 value |= SOR_PLL3_PLL_VDD_MODE_3V3; 2783 tegra_sor_writel(sor, value, sor->soc->regs->pll3); 2784 2785 value = tegra_sor_readl(sor, sor->soc->regs->pll0); 2786 value &= ~(SOR_PLL0_VCOPD | SOR_PLL0_PWR); 2787 tegra_sor_writel(sor, value, sor->soc->regs->pll0); 2788 2789 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 2790 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; 2791 value |= SOR_PLL2_SEQ_PLLCAPPD; 2792 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 2793 2794 usleep_range(200, 400); 2795 2796 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 2797 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; 2798 value &= ~SOR_PLL2_PORT_POWERDOWN; 2799 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 2800 2801 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 2802 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; 2803 2804 if (output->panel) 2805 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; 2806 else 2807 value |= SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK; 2808 2809 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 2810 2811 usleep_range(200, 400); 2812 2813 value = tegra_sor_readl(sor, SOR_DP_SPARE0); 2814 /* XXX not in TRM */ 2815 if (output->panel) 2816 value |= SOR_DP_SPARE_PANEL_INTERNAL; 2817 else 2818 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; 2819 2820 value |= SOR_DP_SPARE_SEQ_ENABLE; 2821 tegra_sor_writel(sor, value, SOR_DP_SPARE0); 2822 2823 /* XXX not in TRM */ 2824 tegra_sor_writel(sor, 0, SOR_LVDS); 2825 2826 value = tegra_sor_readl(sor, sor->soc->regs->pll0); 2827 value &= ~SOR_PLL0_ICHPMP_MASK; 2828 value &= ~SOR_PLL0_VCOCAP_MASK; 2829 value |= SOR_PLL0_ICHPMP(0x1); 2830 value |= SOR_PLL0_VCOCAP(0x3); 2831 value |= SOR_PLL0_RESISTOR_EXT; 2832 tegra_sor_writel(sor, value, sor->soc->regs->pll0); 2833 2834 /* XXX not in TRM */ 2835 for (value = 0, i = 0; i < 5; i++) 2836 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) | 2837 SOR_XBAR_CTRL_LINK1_XSEL(i, i); 2838 2839 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); 2840 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); 2841 2842 /* 2843 * Switch the pad clock to the DP clock. Note that we cannot actually 2844 * do this because Tegra186 and later don't support clk_set_parent() 2845 * on the sorX_pad_clkout clocks. We already do the equivalent above 2846 * using the DP_CLK_SEL mux of the SOR_CLK_CNTRL register. 2847 */ 2848 #if 0 2849 err = clk_set_parent(sor->clk_pad, sor->clk_parent); 2850 if (err < 0) { 2851 dev_err(sor->dev, "failed to select pad parent clock: %d\n", 2852 err); 2853 return; 2854 } 2855 #endif 2856 2857 /* switch the SOR clock to the pad clock */ 2858 err = tegra_sor_set_parent_clock(sor, sor->clk_pad); 2859 if (err < 0) { 2860 dev_err(sor->dev, "failed to select SOR parent clock: %d\n", 2861 err); 2862 return; 2863 } 2864 2865 /* switch the output clock to the parent pixel clock */ 2866 err = clk_set_parent(sor->clk, sor->clk_parent); 2867 if (err < 0) { 2868 dev_err(sor->dev, "failed to select output parent clock: %d\n", 2869 err); 2870 return; 2871 } 2872 2873 /* use DP-A protocol */ 2874 value = tegra_sor_readl(sor, SOR_STATE1); 2875 value &= ~SOR_STATE_ASY_PROTOCOL_MASK; 2876 value |= SOR_STATE_ASY_PROTOCOL_DP_A; 2877 tegra_sor_writel(sor, value, SOR_STATE1); 2878 2879 /* enable port */ 2880 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); 2881 value |= SOR_DP_LINKCTL_ENABLE; 2882 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); 2883 2884 tegra_sor_dp_term_calibrate(sor); 2885 2886 err = drm_dp_link_train(&sor->link); 2887 if (err < 0) 2888 dev_err(sor->dev, "link training failed: %d\n", err); 2889 else 2890 dev_dbg(sor->dev, "link training succeeded\n"); 2891 2892 err = drm_dp_link_power_up(sor->aux, &sor->link); 2893 if (err < 0) 2894 dev_err(sor->dev, "failed to power up DP link: %d\n", err); 2895 2896 /* compute configuration */ 2897 memset(&config, 0, sizeof(config)); 2898 config.bits_per_pixel = state->bpc * 3; 2899 2900 err = tegra_sor_compute_config(sor, mode, &config, &sor->link); 2901 if (err < 0) 2902 dev_err(sor->dev, "failed to compute configuration: %d\n", err); 2903 2904 tegra_sor_apply_config(sor, &config); 2905 tegra_sor_mode_set(sor, mode, state); 2906 2907 if (output->panel) { 2908 /* CSTM (LVDS, link A/B, upper) */ 2909 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B | 2910 SOR_CSTM_UPPER; 2911 tegra_sor_writel(sor, value, SOR_CSTM); 2912 2913 /* PWM setup */ 2914 err = tegra_sor_setup_pwm(sor, 250); 2915 if (err < 0) 2916 dev_err(sor->dev, "failed to setup PWM: %d\n", err); 2917 } 2918 2919 tegra_sor_update(sor); 2920 2921 err = tegra_sor_power_up(sor, 250); 2922 if (err < 0) 2923 dev_err(sor->dev, "failed to power up SOR: %d\n", err); 2924 2925 /* attach and wake up */ 2926 err = tegra_sor_attach(sor); 2927 if (err < 0) 2928 dev_err(sor->dev, "failed to attach SOR: %d\n", err); 2929 2930 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 2931 value |= SOR_ENABLE(sor->index); 2932 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 2933 2934 tegra_dc_commit(dc); 2935 2936 err = tegra_sor_wakeup(sor); 2937 if (err < 0) 2938 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err); 2939 2940 if (output->panel) 2941 drm_panel_enable(output->panel); 2942 } 2943 2944 static const struct drm_encoder_helper_funcs tegra_sor_dp_helpers = { 2945 .disable = tegra_sor_dp_disable, 2946 .enable = tegra_sor_dp_enable, 2947 .atomic_check = tegra_sor_encoder_atomic_check, 2948 }; 2949 2950 static int tegra_sor_hdmi_probe(struct tegra_sor *sor) 2951 { 2952 int err; 2953 2954 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io"); 2955 if (IS_ERR(sor->avdd_io_supply)) { 2956 dev_err(sor->dev, "cannot get AVDD I/O supply: %ld\n", 2957 PTR_ERR(sor->avdd_io_supply)); 2958 return PTR_ERR(sor->avdd_io_supply); 2959 } 2960 2961 err = regulator_enable(sor->avdd_io_supply); 2962 if (err < 0) { 2963 dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n", 2964 err); 2965 return err; 2966 } 2967 2968 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-pll"); 2969 if (IS_ERR(sor->vdd_pll_supply)) { 2970 dev_err(sor->dev, "cannot get VDD PLL supply: %ld\n", 2971 PTR_ERR(sor->vdd_pll_supply)); 2972 return PTR_ERR(sor->vdd_pll_supply); 2973 } 2974 2975 err = regulator_enable(sor->vdd_pll_supply); 2976 if (err < 0) { 2977 dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n", 2978 err); 2979 return err; 2980 } 2981 2982 sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi"); 2983 if (IS_ERR(sor->hdmi_supply)) { 2984 dev_err(sor->dev, "cannot get HDMI supply: %ld\n", 2985 PTR_ERR(sor->hdmi_supply)); 2986 return PTR_ERR(sor->hdmi_supply); 2987 } 2988 2989 err = regulator_enable(sor->hdmi_supply); 2990 if (err < 0) { 2991 dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err); 2992 return err; 2993 } 2994 2995 INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work); 2996 2997 return 0; 2998 } 2999 3000 static int tegra_sor_hdmi_remove(struct tegra_sor *sor) 3001 { 3002 regulator_disable(sor->hdmi_supply); 3003 regulator_disable(sor->vdd_pll_supply); 3004 regulator_disable(sor->avdd_io_supply); 3005 3006 return 0; 3007 } 3008 3009 static const struct tegra_sor_ops tegra_sor_hdmi_ops = { 3010 .name = "HDMI", 3011 .probe = tegra_sor_hdmi_probe, 3012 .remove = tegra_sor_hdmi_remove, 3013 .audio_enable = tegra_sor_hdmi_audio_enable, 3014 .audio_disable = tegra_sor_hdmi_audio_disable, 3015 }; 3016 3017 static int tegra_sor_dp_probe(struct tegra_sor *sor) 3018 { 3019 int err; 3020 3021 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp"); 3022 if (IS_ERR(sor->avdd_io_supply)) 3023 return PTR_ERR(sor->avdd_io_supply); 3024 3025 err = regulator_enable(sor->avdd_io_supply); 3026 if (err < 0) 3027 return err; 3028 3029 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll"); 3030 if (IS_ERR(sor->vdd_pll_supply)) 3031 return PTR_ERR(sor->vdd_pll_supply); 3032 3033 err = regulator_enable(sor->vdd_pll_supply); 3034 if (err < 0) 3035 return err; 3036 3037 return 0; 3038 } 3039 3040 static int tegra_sor_dp_remove(struct tegra_sor *sor) 3041 { 3042 regulator_disable(sor->vdd_pll_supply); 3043 regulator_disable(sor->avdd_io_supply); 3044 3045 return 0; 3046 } 3047 3048 static const struct tegra_sor_ops tegra_sor_dp_ops = { 3049 .name = "DP", 3050 .probe = tegra_sor_dp_probe, 3051 .remove = tegra_sor_dp_remove, 3052 }; 3053 3054 static int tegra_sor_init(struct host1x_client *client) 3055 { 3056 struct drm_device *drm = dev_get_drvdata(client->parent); 3057 const struct drm_encoder_helper_funcs *helpers = NULL; 3058 struct tegra_sor *sor = host1x_client_to_sor(client); 3059 int connector = DRM_MODE_CONNECTOR_Unknown; 3060 int encoder = DRM_MODE_ENCODER_NONE; 3061 int err; 3062 3063 if (!sor->aux) { 3064 if (sor->ops == &tegra_sor_hdmi_ops) { 3065 connector = DRM_MODE_CONNECTOR_HDMIA; 3066 encoder = DRM_MODE_ENCODER_TMDS; 3067 helpers = &tegra_sor_hdmi_helpers; 3068 } else if (sor->soc->supports_lvds) { 3069 connector = DRM_MODE_CONNECTOR_LVDS; 3070 encoder = DRM_MODE_ENCODER_LVDS; 3071 } 3072 } else { 3073 if (sor->output.panel) { 3074 connector = DRM_MODE_CONNECTOR_eDP; 3075 encoder = DRM_MODE_ENCODER_TMDS; 3076 helpers = &tegra_sor_dp_helpers; 3077 } else { 3078 connector = DRM_MODE_CONNECTOR_DisplayPort; 3079 encoder = DRM_MODE_ENCODER_TMDS; 3080 helpers = &tegra_sor_dp_helpers; 3081 } 3082 3083 sor->link.ops = &tegra_sor_dp_link_ops; 3084 sor->link.aux = sor->aux; 3085 } 3086 3087 sor->output.dev = sor->dev; 3088 3089 drm_connector_init(drm, &sor->output.connector, 3090 &tegra_sor_connector_funcs, 3091 connector); 3092 drm_connector_helper_add(&sor->output.connector, 3093 &tegra_sor_connector_helper_funcs); 3094 sor->output.connector.dpms = DRM_MODE_DPMS_OFF; 3095 3096 drm_encoder_init(drm, &sor->output.encoder, &tegra_sor_encoder_funcs, 3097 encoder, NULL); 3098 drm_encoder_helper_add(&sor->output.encoder, helpers); 3099 3100 drm_connector_attach_encoder(&sor->output.connector, 3101 &sor->output.encoder); 3102 drm_connector_register(&sor->output.connector); 3103 3104 err = tegra_output_init(drm, &sor->output); 3105 if (err < 0) { 3106 dev_err(client->dev, "failed to initialize output: %d\n", err); 3107 return err; 3108 } 3109 3110 tegra_output_find_possible_crtcs(&sor->output, drm); 3111 3112 if (sor->aux) { 3113 err = drm_dp_aux_attach(sor->aux, &sor->output); 3114 if (err < 0) { 3115 dev_err(sor->dev, "failed to attach DP: %d\n", err); 3116 return err; 3117 } 3118 } 3119 3120 /* 3121 * XXX: Remove this reset once proper hand-over from firmware to 3122 * kernel is possible. 3123 */ 3124 if (sor->rst) { 3125 err = reset_control_acquire(sor->rst); 3126 if (err < 0) { 3127 dev_err(sor->dev, "failed to acquire SOR reset: %d\n", 3128 err); 3129 return err; 3130 } 3131 3132 err = reset_control_assert(sor->rst); 3133 if (err < 0) { 3134 dev_err(sor->dev, "failed to assert SOR reset: %d\n", 3135 err); 3136 return err; 3137 } 3138 } 3139 3140 err = clk_prepare_enable(sor->clk); 3141 if (err < 0) { 3142 dev_err(sor->dev, "failed to enable clock: %d\n", err); 3143 return err; 3144 } 3145 3146 usleep_range(1000, 3000); 3147 3148 if (sor->rst) { 3149 err = reset_control_deassert(sor->rst); 3150 if (err < 0) { 3151 dev_err(sor->dev, "failed to deassert SOR reset: %d\n", 3152 err); 3153 return err; 3154 } 3155 3156 reset_control_release(sor->rst); 3157 } 3158 3159 err = clk_prepare_enable(sor->clk_safe); 3160 if (err < 0) 3161 return err; 3162 3163 err = clk_prepare_enable(sor->clk_dp); 3164 if (err < 0) 3165 return err; 3166 3167 return 0; 3168 } 3169 3170 static int tegra_sor_exit(struct host1x_client *client) 3171 { 3172 struct tegra_sor *sor = host1x_client_to_sor(client); 3173 int err; 3174 3175 tegra_output_exit(&sor->output); 3176 3177 if (sor->aux) { 3178 err = drm_dp_aux_detach(sor->aux); 3179 if (err < 0) { 3180 dev_err(sor->dev, "failed to detach DP: %d\n", err); 3181 return err; 3182 } 3183 } 3184 3185 clk_disable_unprepare(sor->clk_safe); 3186 clk_disable_unprepare(sor->clk_dp); 3187 clk_disable_unprepare(sor->clk); 3188 3189 return 0; 3190 } 3191 3192 static const struct host1x_client_ops sor_client_ops = { 3193 .init = tegra_sor_init, 3194 .exit = tegra_sor_exit, 3195 }; 3196 3197 static const u8 tegra124_sor_xbar_cfg[5] = { 3198 0, 1, 2, 3, 4 3199 }; 3200 3201 static const struct tegra_sor_regs tegra124_sor_regs = { 3202 .head_state0 = 0x05, 3203 .head_state1 = 0x07, 3204 .head_state2 = 0x09, 3205 .head_state3 = 0x0b, 3206 .head_state4 = 0x0d, 3207 .head_state5 = 0x0f, 3208 .pll0 = 0x17, 3209 .pll1 = 0x18, 3210 .pll2 = 0x19, 3211 .pll3 = 0x1a, 3212 .dp_padctl0 = 0x5c, 3213 .dp_padctl2 = 0x73, 3214 }; 3215 3216 /* Tegra124 and Tegra132 have lanes 0 and 2 swapped. */ 3217 static const u8 tegra124_sor_lane_map[4] = { 3218 2, 1, 0, 3, 3219 }; 3220 3221 static const u8 tegra124_sor_voltage_swing[4][4][4] = { 3222 { 3223 { 0x13, 0x19, 0x1e, 0x28 }, 3224 { 0x1e, 0x25, 0x2d, }, 3225 { 0x28, 0x32, }, 3226 { 0x3c, }, 3227 }, { 3228 { 0x12, 0x17, 0x1b, 0x25 }, 3229 { 0x1c, 0x23, 0x2a, }, 3230 { 0x25, 0x2f, }, 3231 { 0x39, } 3232 }, { 3233 { 0x12, 0x16, 0x1a, 0x22 }, 3234 { 0x1b, 0x20, 0x27, }, 3235 { 0x24, 0x2d, }, 3236 { 0x36, }, 3237 }, { 3238 { 0x11, 0x14, 0x17, 0x1f }, 3239 { 0x19, 0x1e, 0x24, }, 3240 { 0x22, 0x2a, }, 3241 { 0x32, }, 3242 }, 3243 }; 3244 3245 static const u8 tegra124_sor_pre_emphasis[4][4][4] = { 3246 { 3247 { 0x00, 0x09, 0x13, 0x25 }, 3248 { 0x00, 0x0f, 0x1e, }, 3249 { 0x00, 0x14, }, 3250 { 0x00, }, 3251 }, { 3252 { 0x00, 0x0a, 0x14, 0x28 }, 3253 { 0x00, 0x0f, 0x1e, }, 3254 { 0x00, 0x14, }, 3255 { 0x00 }, 3256 }, { 3257 { 0x00, 0x0a, 0x14, 0x28 }, 3258 { 0x00, 0x0f, 0x1e, }, 3259 { 0x00, 0x14, }, 3260 { 0x00, }, 3261 }, { 3262 { 0x00, 0x0a, 0x14, 0x28 }, 3263 { 0x00, 0x0f, 0x1e, }, 3264 { 0x00, 0x14, }, 3265 { 0x00, }, 3266 }, 3267 }; 3268 3269 static const u8 tegra124_sor_post_cursor[4][4][4] = { 3270 { 3271 { 0x00, 0x00, 0x00, 0x00 }, 3272 { 0x00, 0x00, 0x00, }, 3273 { 0x00, 0x00, }, 3274 { 0x00, }, 3275 }, { 3276 { 0x02, 0x02, 0x04, 0x05 }, 3277 { 0x02, 0x04, 0x05, }, 3278 { 0x04, 0x05, }, 3279 { 0x05, }, 3280 }, { 3281 { 0x04, 0x05, 0x08, 0x0b }, 3282 { 0x05, 0x09, 0x0b, }, 3283 { 0x08, 0x0a, }, 3284 { 0x0b, }, 3285 }, { 3286 { 0x05, 0x09, 0x0b, 0x12 }, 3287 { 0x09, 0x0d, 0x12, }, 3288 { 0x0b, 0x0f, }, 3289 { 0x12, }, 3290 }, 3291 }; 3292 3293 static const u8 tegra124_sor_tx_pu[4][4][4] = { 3294 { 3295 { 0x20, 0x30, 0x40, 0x60 }, 3296 { 0x30, 0x40, 0x60, }, 3297 { 0x40, 0x60, }, 3298 { 0x60, }, 3299 }, { 3300 { 0x20, 0x20, 0x30, 0x50 }, 3301 { 0x30, 0x40, 0x50, }, 3302 { 0x40, 0x50, }, 3303 { 0x60, }, 3304 }, { 3305 { 0x20, 0x20, 0x30, 0x40, }, 3306 { 0x30, 0x30, 0x40, }, 3307 { 0x40, 0x50, }, 3308 { 0x60, }, 3309 }, { 3310 { 0x20, 0x20, 0x20, 0x40, }, 3311 { 0x30, 0x30, 0x40, }, 3312 { 0x40, 0x40, }, 3313 { 0x60, }, 3314 }, 3315 }; 3316 3317 static const struct tegra_sor_soc tegra124_sor = { 3318 .supports_lvds = true, 3319 .supports_hdmi = false, 3320 .supports_dp = true, 3321 .supports_audio = false, 3322 .supports_hdcp = false, 3323 .regs = &tegra124_sor_regs, 3324 .has_nvdisplay = false, 3325 .xbar_cfg = tegra124_sor_xbar_cfg, 3326 .lane_map = tegra124_sor_lane_map, 3327 .voltage_swing = tegra124_sor_voltage_swing, 3328 .pre_emphasis = tegra124_sor_pre_emphasis, 3329 .post_cursor = tegra124_sor_post_cursor, 3330 .tx_pu = tegra124_sor_tx_pu, 3331 }; 3332 3333 static const u8 tegra132_sor_pre_emphasis[4][4][4] = { 3334 { 3335 { 0x00, 0x08, 0x12, 0x24 }, 3336 { 0x01, 0x0e, 0x1d, }, 3337 { 0x01, 0x13, }, 3338 { 0x00, }, 3339 }, { 3340 { 0x00, 0x08, 0x12, 0x24 }, 3341 { 0x00, 0x0e, 0x1d, }, 3342 { 0x00, 0x13, }, 3343 { 0x00 }, 3344 }, { 3345 { 0x00, 0x08, 0x12, 0x24 }, 3346 { 0x00, 0x0e, 0x1d, }, 3347 { 0x00, 0x13, }, 3348 { 0x00, }, 3349 }, { 3350 { 0x00, 0x08, 0x12, 0x24 }, 3351 { 0x00, 0x0e, 0x1d, }, 3352 { 0x00, 0x13, }, 3353 { 0x00, }, 3354 }, 3355 }; 3356 3357 static const struct tegra_sor_soc tegra132_sor = { 3358 .supports_lvds = true, 3359 .supports_hdmi = false, 3360 .supports_dp = true, 3361 .supports_audio = false, 3362 .supports_hdcp = false, 3363 .regs = &tegra124_sor_regs, 3364 .has_nvdisplay = false, 3365 .xbar_cfg = tegra124_sor_xbar_cfg, 3366 .lane_map = tegra124_sor_lane_map, 3367 .voltage_swing = tegra124_sor_voltage_swing, 3368 .pre_emphasis = tegra132_sor_pre_emphasis, 3369 .post_cursor = tegra124_sor_post_cursor, 3370 .tx_pu = tegra124_sor_tx_pu, 3371 }; 3372 3373 static const struct tegra_sor_regs tegra210_sor_regs = { 3374 .head_state0 = 0x05, 3375 .head_state1 = 0x07, 3376 .head_state2 = 0x09, 3377 .head_state3 = 0x0b, 3378 .head_state4 = 0x0d, 3379 .head_state5 = 0x0f, 3380 .pll0 = 0x17, 3381 .pll1 = 0x18, 3382 .pll2 = 0x19, 3383 .pll3 = 0x1a, 3384 .dp_padctl0 = 0x5c, 3385 .dp_padctl2 = 0x73, 3386 }; 3387 3388 static const u8 tegra210_sor_xbar_cfg[5] = { 3389 2, 1, 0, 3, 4 3390 }; 3391 3392 static const u8 tegra210_sor_lane_map[4] = { 3393 0, 1, 2, 3, 3394 }; 3395 3396 static const struct tegra_sor_soc tegra210_sor = { 3397 .supports_lvds = false, 3398 .supports_hdmi = false, 3399 .supports_dp = true, 3400 .supports_audio = false, 3401 .supports_hdcp = false, 3402 3403 .regs = &tegra210_sor_regs, 3404 .has_nvdisplay = false, 3405 3406 .xbar_cfg = tegra210_sor_xbar_cfg, 3407 .lane_map = tegra210_sor_lane_map, 3408 .voltage_swing = tegra124_sor_voltage_swing, 3409 .pre_emphasis = tegra124_sor_pre_emphasis, 3410 .post_cursor = tegra124_sor_post_cursor, 3411 .tx_pu = tegra124_sor_tx_pu, 3412 }; 3413 3414 static const struct tegra_sor_soc tegra210_sor1 = { 3415 .supports_lvds = false, 3416 .supports_hdmi = true, 3417 .supports_dp = true, 3418 .supports_audio = true, 3419 .supports_hdcp = true, 3420 3421 .regs = &tegra210_sor_regs, 3422 .has_nvdisplay = false, 3423 3424 .num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults), 3425 .settings = tegra210_sor_hdmi_defaults, 3426 .xbar_cfg = tegra210_sor_xbar_cfg, 3427 .lane_map = tegra210_sor_lane_map, 3428 .voltage_swing = tegra124_sor_voltage_swing, 3429 .pre_emphasis = tegra124_sor_pre_emphasis, 3430 .post_cursor = tegra124_sor_post_cursor, 3431 .tx_pu = tegra124_sor_tx_pu, 3432 }; 3433 3434 static const struct tegra_sor_regs tegra186_sor_regs = { 3435 .head_state0 = 0x151, 3436 .head_state1 = 0x154, 3437 .head_state2 = 0x157, 3438 .head_state3 = 0x15a, 3439 .head_state4 = 0x15d, 3440 .head_state5 = 0x160, 3441 .pll0 = 0x163, 3442 .pll1 = 0x164, 3443 .pll2 = 0x165, 3444 .pll3 = 0x166, 3445 .dp_padctl0 = 0x168, 3446 .dp_padctl2 = 0x16a, 3447 }; 3448 3449 static const u8 tegra186_sor_voltage_swing[4][4][4] = { 3450 { 3451 { 0x13, 0x19, 0x1e, 0x28 }, 3452 { 0x1e, 0x25, 0x2d, }, 3453 { 0x28, 0x32, }, 3454 { 0x39, }, 3455 }, { 3456 { 0x12, 0x16, 0x1b, 0x25 }, 3457 { 0x1c, 0x23, 0x2a, }, 3458 { 0x25, 0x2f, }, 3459 { 0x37, } 3460 }, { 3461 { 0x12, 0x16, 0x1a, 0x22 }, 3462 { 0x1b, 0x20, 0x27, }, 3463 { 0x24, 0x2d, }, 3464 { 0x35, }, 3465 }, { 3466 { 0x11, 0x14, 0x17, 0x1f }, 3467 { 0x19, 0x1e, 0x24, }, 3468 { 0x22, 0x2a, }, 3469 { 0x32, }, 3470 }, 3471 }; 3472 3473 static const u8 tegra186_sor_pre_emphasis[4][4][4] = { 3474 { 3475 { 0x00, 0x08, 0x12, 0x24 }, 3476 { 0x01, 0x0e, 0x1d, }, 3477 { 0x01, 0x13, }, 3478 { 0x00, }, 3479 }, { 3480 { 0x00, 0x08, 0x12, 0x24 }, 3481 { 0x00, 0x0e, 0x1d, }, 3482 { 0x00, 0x13, }, 3483 { 0x00 }, 3484 }, { 3485 { 0x00, 0x08, 0x14, 0x24 }, 3486 { 0x00, 0x0e, 0x1d, }, 3487 { 0x00, 0x13, }, 3488 { 0x00, }, 3489 }, { 3490 { 0x00, 0x08, 0x12, 0x24 }, 3491 { 0x00, 0x0e, 0x1d, }, 3492 { 0x00, 0x13, }, 3493 { 0x00, }, 3494 }, 3495 }; 3496 3497 static const struct tegra_sor_soc tegra186_sor = { 3498 .supports_lvds = false, 3499 .supports_hdmi = true, 3500 .supports_dp = true, 3501 .supports_audio = true, 3502 .supports_hdcp = true, 3503 3504 .regs = &tegra186_sor_regs, 3505 .has_nvdisplay = true, 3506 3507 .num_settings = ARRAY_SIZE(tegra186_sor_hdmi_defaults), 3508 .settings = tegra186_sor_hdmi_defaults, 3509 .xbar_cfg = tegra124_sor_xbar_cfg, 3510 .lane_map = tegra124_sor_lane_map, 3511 .voltage_swing = tegra186_sor_voltage_swing, 3512 .pre_emphasis = tegra186_sor_pre_emphasis, 3513 .post_cursor = tegra124_sor_post_cursor, 3514 .tx_pu = tegra124_sor_tx_pu, 3515 }; 3516 3517 static const struct tegra_sor_regs tegra194_sor_regs = { 3518 .head_state0 = 0x151, 3519 .head_state1 = 0x155, 3520 .head_state2 = 0x159, 3521 .head_state3 = 0x15d, 3522 .head_state4 = 0x161, 3523 .head_state5 = 0x165, 3524 .pll0 = 0x169, 3525 .pll1 = 0x16a, 3526 .pll2 = 0x16b, 3527 .pll3 = 0x16c, 3528 .dp_padctl0 = 0x16e, 3529 .dp_padctl2 = 0x16f, 3530 }; 3531 3532 static const struct tegra_sor_soc tegra194_sor = { 3533 .supports_lvds = false, 3534 .supports_hdmi = true, 3535 .supports_dp = true, 3536 .supports_audio = true, 3537 .supports_hdcp = true, 3538 3539 .regs = &tegra194_sor_regs, 3540 .has_nvdisplay = true, 3541 3542 .num_settings = ARRAY_SIZE(tegra194_sor_hdmi_defaults), 3543 .settings = tegra194_sor_hdmi_defaults, 3544 3545 .xbar_cfg = tegra210_sor_xbar_cfg, 3546 .lane_map = tegra124_sor_lane_map, 3547 .voltage_swing = tegra186_sor_voltage_swing, 3548 .pre_emphasis = tegra186_sor_pre_emphasis, 3549 .post_cursor = tegra124_sor_post_cursor, 3550 .tx_pu = tegra124_sor_tx_pu, 3551 }; 3552 3553 static const struct of_device_id tegra_sor_of_match[] = { 3554 { .compatible = "nvidia,tegra194-sor", .data = &tegra194_sor }, 3555 { .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor }, 3556 { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 }, 3557 { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor }, 3558 { .compatible = "nvidia,tegra132-sor", .data = &tegra132_sor }, 3559 { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor }, 3560 { }, 3561 }; 3562 MODULE_DEVICE_TABLE(of, tegra_sor_of_match); 3563 3564 static int tegra_sor_parse_dt(struct tegra_sor *sor) 3565 { 3566 struct device_node *np = sor->dev->of_node; 3567 u32 xbar_cfg[5]; 3568 unsigned int i; 3569 u32 value; 3570 int err; 3571 3572 if (sor->soc->has_nvdisplay) { 3573 err = of_property_read_u32(np, "nvidia,interface", &value); 3574 if (err < 0) 3575 return err; 3576 3577 sor->index = value; 3578 3579 /* 3580 * override the default that we already set for Tegra210 and 3581 * earlier 3582 */ 3583 sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index; 3584 } else { 3585 if (!sor->soc->supports_audio) 3586 sor->index = 0; 3587 else 3588 sor->index = 1; 3589 } 3590 3591 err = of_property_read_u32_array(np, "nvidia,xbar-cfg", xbar_cfg, 5); 3592 if (err < 0) { 3593 /* fall back to default per-SoC XBAR configuration */ 3594 for (i = 0; i < 5; i++) 3595 sor->xbar_cfg[i] = sor->soc->xbar_cfg[i]; 3596 } else { 3597 /* copy cells to SOR XBAR configuration */ 3598 for (i = 0; i < 5; i++) 3599 sor->xbar_cfg[i] = xbar_cfg[i]; 3600 } 3601 3602 return 0; 3603 } 3604 3605 static irqreturn_t tegra_sor_irq(int irq, void *data) 3606 { 3607 struct tegra_sor *sor = data; 3608 u32 value; 3609 3610 value = tegra_sor_readl(sor, SOR_INT_STATUS); 3611 tegra_sor_writel(sor, value, SOR_INT_STATUS); 3612 3613 if (value & SOR_INT_CODEC_SCRATCH0) { 3614 value = tegra_sor_readl(sor, SOR_AUDIO_HDA_CODEC_SCRATCH0); 3615 3616 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) { 3617 unsigned int format; 3618 3619 format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK; 3620 3621 tegra_hda_parse_format(format, &sor->format); 3622 3623 if (sor->ops->audio_enable) 3624 sor->ops->audio_enable(sor); 3625 } else { 3626 if (sor->ops->audio_disable) 3627 sor->ops->audio_disable(sor); 3628 } 3629 } 3630 3631 return IRQ_HANDLED; 3632 } 3633 3634 static int tegra_sor_probe(struct platform_device *pdev) 3635 { 3636 struct device_node *np; 3637 struct tegra_sor *sor; 3638 struct resource *regs; 3639 int err; 3640 3641 sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL); 3642 if (!sor) 3643 return -ENOMEM; 3644 3645 sor->soc = of_device_get_match_data(&pdev->dev); 3646 sor->output.dev = sor->dev = &pdev->dev; 3647 3648 sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings, 3649 sor->soc->num_settings * 3650 sizeof(*sor->settings), 3651 GFP_KERNEL); 3652 if (!sor->settings) 3653 return -ENOMEM; 3654 3655 sor->num_settings = sor->soc->num_settings; 3656 3657 np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0); 3658 if (np) { 3659 sor->aux = drm_dp_aux_find_by_of_node(np); 3660 of_node_put(np); 3661 3662 if (!sor->aux) 3663 return -EPROBE_DEFER; 3664 3665 sor->output.ddc = &sor->aux->ddc; 3666 } 3667 3668 if (!sor->aux) { 3669 if (sor->soc->supports_hdmi) { 3670 sor->ops = &tegra_sor_hdmi_ops; 3671 sor->pad = TEGRA_IO_PAD_HDMI; 3672 } else if (sor->soc->supports_lvds) { 3673 dev_err(&pdev->dev, "LVDS not supported yet\n"); 3674 return -ENODEV; 3675 } else { 3676 dev_err(&pdev->dev, "unknown (non-DP) support\n"); 3677 return -ENODEV; 3678 } 3679 } else { 3680 np = of_parse_phandle(pdev->dev.of_node, "nvidia,panel", 0); 3681 /* 3682 * No need to keep this around since we only use it as a check 3683 * to see if a panel is connected (eDP) or not (DP). 3684 */ 3685 of_node_put(np); 3686 3687 sor->ops = &tegra_sor_dp_ops; 3688 sor->pad = TEGRA_IO_PAD_LVDS; 3689 } 3690 3691 err = tegra_sor_parse_dt(sor); 3692 if (err < 0) 3693 return err; 3694 3695 err = tegra_output_probe(&sor->output); 3696 if (err < 0) { 3697 dev_err(&pdev->dev, "failed to probe output: %d\n", err); 3698 return err; 3699 } 3700 3701 if (sor->ops && sor->ops->probe) { 3702 err = sor->ops->probe(sor); 3703 if (err < 0) { 3704 dev_err(&pdev->dev, "failed to probe %s: %d\n", 3705 sor->ops->name, err); 3706 goto output; 3707 } 3708 } 3709 3710 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3711 sor->regs = devm_ioremap_resource(&pdev->dev, regs); 3712 if (IS_ERR(sor->regs)) { 3713 err = PTR_ERR(sor->regs); 3714 goto remove; 3715 } 3716 3717 err = platform_get_irq(pdev, 0); 3718 if (err < 0) { 3719 dev_err(&pdev->dev, "failed to get IRQ: %d\n", err); 3720 goto remove; 3721 } 3722 3723 sor->irq = err; 3724 3725 err = devm_request_irq(sor->dev, sor->irq, tegra_sor_irq, 0, 3726 dev_name(sor->dev), sor); 3727 if (err < 0) { 3728 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err); 3729 goto remove; 3730 } 3731 3732 sor->rst = devm_reset_control_get_exclusive_released(&pdev->dev, "sor"); 3733 if (IS_ERR(sor->rst)) { 3734 err = PTR_ERR(sor->rst); 3735 3736 if (err != -EBUSY || WARN_ON(!pdev->dev.pm_domain)) { 3737 dev_err(&pdev->dev, "failed to get reset control: %d\n", 3738 err); 3739 goto remove; 3740 } 3741 3742 /* 3743 * At this point, the reset control is most likely being used 3744 * by the generic power domain implementation. With any luck 3745 * the power domain will have taken care of resetting the SOR 3746 * and we don't have to do anything. 3747 */ 3748 sor->rst = NULL; 3749 } 3750 3751 sor->clk = devm_clk_get(&pdev->dev, NULL); 3752 if (IS_ERR(sor->clk)) { 3753 err = PTR_ERR(sor->clk); 3754 dev_err(&pdev->dev, "failed to get module clock: %d\n", err); 3755 goto remove; 3756 } 3757 3758 if (sor->soc->supports_hdmi || sor->soc->supports_dp) { 3759 struct device_node *np = pdev->dev.of_node; 3760 const char *name; 3761 3762 /* 3763 * For backwards compatibility with Tegra210 device trees, 3764 * fall back to the old clock name "source" if the new "out" 3765 * clock is not available. 3766 */ 3767 if (of_property_match_string(np, "clock-names", "out") < 0) 3768 name = "source"; 3769 else 3770 name = "out"; 3771 3772 sor->clk_out = devm_clk_get(&pdev->dev, name); 3773 if (IS_ERR(sor->clk_out)) { 3774 err = PTR_ERR(sor->clk_out); 3775 dev_err(sor->dev, "failed to get %s clock: %d\n", 3776 name, err); 3777 goto remove; 3778 } 3779 } else { 3780 /* fall back to the module clock on SOR0 (eDP/LVDS only) */ 3781 sor->clk_out = sor->clk; 3782 } 3783 3784 sor->clk_parent = devm_clk_get(&pdev->dev, "parent"); 3785 if (IS_ERR(sor->clk_parent)) { 3786 err = PTR_ERR(sor->clk_parent); 3787 dev_err(&pdev->dev, "failed to get parent clock: %d\n", err); 3788 goto remove; 3789 } 3790 3791 sor->clk_safe = devm_clk_get(&pdev->dev, "safe"); 3792 if (IS_ERR(sor->clk_safe)) { 3793 err = PTR_ERR(sor->clk_safe); 3794 dev_err(&pdev->dev, "failed to get safe clock: %d\n", err); 3795 goto remove; 3796 } 3797 3798 sor->clk_dp = devm_clk_get(&pdev->dev, "dp"); 3799 if (IS_ERR(sor->clk_dp)) { 3800 err = PTR_ERR(sor->clk_dp); 3801 dev_err(&pdev->dev, "failed to get DP clock: %d\n", err); 3802 goto remove; 3803 } 3804 3805 /* 3806 * Starting with Tegra186, the BPMP provides an implementation for 3807 * the pad output clock, so we have to look it up from device tree. 3808 */ 3809 sor->clk_pad = devm_clk_get(&pdev->dev, "pad"); 3810 if (IS_ERR(sor->clk_pad)) { 3811 if (sor->clk_pad != ERR_PTR(-ENOENT)) { 3812 err = PTR_ERR(sor->clk_pad); 3813 goto remove; 3814 } 3815 3816 /* 3817 * If the pad output clock is not available, then we assume 3818 * we're on Tegra210 or earlier and have to provide our own 3819 * implementation. 3820 */ 3821 sor->clk_pad = NULL; 3822 } 3823 3824 /* 3825 * The bootloader may have set up the SOR such that it's module clock 3826 * is sourced by one of the display PLLs. However, that doesn't work 3827 * without properly having set up other bits of the SOR. 3828 */ 3829 err = clk_set_parent(sor->clk_out, sor->clk_safe); 3830 if (err < 0) { 3831 dev_err(&pdev->dev, "failed to use safe clock: %d\n", err); 3832 goto remove; 3833 } 3834 3835 platform_set_drvdata(pdev, sor); 3836 pm_runtime_enable(&pdev->dev); 3837 3838 /* 3839 * On Tegra210 and earlier, provide our own implementation for the 3840 * pad output clock. 3841 */ 3842 if (!sor->clk_pad) { 3843 char *name; 3844 3845 err = pm_runtime_get_sync(&pdev->dev); 3846 if (err < 0) { 3847 dev_err(&pdev->dev, "failed to get runtime PM: %d\n", 3848 err); 3849 goto remove; 3850 } 3851 3852 name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "sor%u_pad_clkout", sor->index); 3853 if (!name) { 3854 err = -ENOMEM; 3855 goto remove; 3856 } 3857 3858 sor->clk_pad = tegra_clk_sor_pad_register(sor, name); 3859 pm_runtime_put(&pdev->dev); 3860 } 3861 3862 if (IS_ERR(sor->clk_pad)) { 3863 err = PTR_ERR(sor->clk_pad); 3864 dev_err(&pdev->dev, "failed to register SOR pad clock: %d\n", 3865 err); 3866 goto remove; 3867 } 3868 3869 INIT_LIST_HEAD(&sor->client.list); 3870 sor->client.ops = &sor_client_ops; 3871 sor->client.dev = &pdev->dev; 3872 3873 err = host1x_client_register(&sor->client); 3874 if (err < 0) { 3875 dev_err(&pdev->dev, "failed to register host1x client: %d\n", 3876 err); 3877 goto remove; 3878 } 3879 3880 return 0; 3881 3882 remove: 3883 if (sor->ops && sor->ops->remove) 3884 sor->ops->remove(sor); 3885 output: 3886 tegra_output_remove(&sor->output); 3887 return err; 3888 } 3889 3890 static int tegra_sor_remove(struct platform_device *pdev) 3891 { 3892 struct tegra_sor *sor = platform_get_drvdata(pdev); 3893 int err; 3894 3895 pm_runtime_disable(&pdev->dev); 3896 3897 err = host1x_client_unregister(&sor->client); 3898 if (err < 0) { 3899 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", 3900 err); 3901 return err; 3902 } 3903 3904 if (sor->ops && sor->ops->remove) { 3905 err = sor->ops->remove(sor); 3906 if (err < 0) 3907 dev_err(&pdev->dev, "failed to remove SOR: %d\n", err); 3908 } 3909 3910 tegra_output_remove(&sor->output); 3911 3912 return 0; 3913 } 3914 3915 static int tegra_sor_runtime_suspend(struct device *dev) 3916 { 3917 struct tegra_sor *sor = dev_get_drvdata(dev); 3918 int err; 3919 3920 if (sor->rst) { 3921 err = reset_control_assert(sor->rst); 3922 if (err < 0) { 3923 dev_err(dev, "failed to assert reset: %d\n", err); 3924 return err; 3925 } 3926 3927 reset_control_release(sor->rst); 3928 } 3929 3930 usleep_range(1000, 2000); 3931 3932 clk_disable_unprepare(sor->clk); 3933 3934 return 0; 3935 } 3936 3937 static int tegra_sor_runtime_resume(struct device *dev) 3938 { 3939 struct tegra_sor *sor = dev_get_drvdata(dev); 3940 int err; 3941 3942 err = clk_prepare_enable(sor->clk); 3943 if (err < 0) { 3944 dev_err(dev, "failed to enable clock: %d\n", err); 3945 return err; 3946 } 3947 3948 usleep_range(1000, 2000); 3949 3950 if (sor->rst) { 3951 err = reset_control_acquire(sor->rst); 3952 if (err < 0) { 3953 dev_err(dev, "failed to acquire reset: %d\n", err); 3954 clk_disable_unprepare(sor->clk); 3955 return err; 3956 } 3957 3958 err = reset_control_deassert(sor->rst); 3959 if (err < 0) { 3960 dev_err(dev, "failed to deassert reset: %d\n", err); 3961 reset_control_release(sor->rst); 3962 clk_disable_unprepare(sor->clk); 3963 return err; 3964 } 3965 } 3966 3967 return 0; 3968 } 3969 3970 static int tegra_sor_suspend(struct device *dev) 3971 { 3972 struct tegra_sor *sor = dev_get_drvdata(dev); 3973 int err; 3974 3975 if (sor->hdmi_supply) { 3976 err = regulator_disable(sor->hdmi_supply); 3977 if (err < 0) 3978 return err; 3979 } 3980 3981 return 0; 3982 } 3983 3984 static int tegra_sor_resume(struct device *dev) 3985 { 3986 struct tegra_sor *sor = dev_get_drvdata(dev); 3987 int err; 3988 3989 if (sor->hdmi_supply) { 3990 err = regulator_enable(sor->hdmi_supply); 3991 if (err < 0) 3992 return err; 3993 } 3994 3995 return 0; 3996 } 3997 3998 static const struct dev_pm_ops tegra_sor_pm_ops = { 3999 SET_RUNTIME_PM_OPS(tegra_sor_runtime_suspend, tegra_sor_runtime_resume, 4000 NULL) 4001 SET_SYSTEM_SLEEP_PM_OPS(tegra_sor_suspend, tegra_sor_resume) 4002 }; 4003 4004 struct platform_driver tegra_sor_driver = { 4005 .driver = { 4006 .name = "tegra-sor", 4007 .of_match_table = tegra_sor_of_match, 4008 .pm = &tegra_sor_pm_ops, 4009 }, 4010 .probe = tegra_sor_probe, 4011 .remove = tegra_sor_remove, 4012 }; 4013