1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 NVIDIA Corporation 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/debugfs.h> 9 #include <linux/io.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/platform_device.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/regulator/consumer.h> 15 #include <linux/reset.h> 16 #include <linux/string_choices.h> 17 18 #include <soc/tegra/pmc.h> 19 20 #include <drm/display/drm_dp_helper.h> 21 #include <drm/display/drm_scdc_helper.h> 22 #include <drm/drm_atomic_helper.h> 23 #include <drm/drm_debugfs.h> 24 #include <drm/drm_edid.h> 25 #include <drm/drm_eld.h> 26 #include <drm/drm_encoder.h> 27 #include <drm/drm_file.h> 28 #include <drm/drm_panel.h> 29 #include <drm/drm_print.h> 30 31 #include "dc.h" 32 #include "dp.h" 33 #include "drm.h" 34 #include "hda.h" 35 #include "sor.h" 36 #include "trace.h" 37 38 #define SOR_REKEY 0x38 39 40 struct tegra_sor_hdmi_settings { 41 unsigned long frequency; 42 43 u8 vcocap; 44 u8 filter; 45 u8 ichpmp; 46 u8 loadadj; 47 u8 tmds_termadj; 48 u8 tx_pu_value; 49 u8 bg_temp_coef; 50 u8 bg_vref_level; 51 u8 avdd10_level; 52 u8 avdd14_level; 53 u8 sparepll; 54 55 u8 drive_current[4]; 56 u8 preemphasis[4]; 57 }; 58 59 #if 1 60 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = { 61 { 62 .frequency = 54000000, 63 .vcocap = 0x0, 64 .filter = 0x0, 65 .ichpmp = 0x1, 66 .loadadj = 0x3, 67 .tmds_termadj = 0x9, 68 .tx_pu_value = 0x10, 69 .bg_temp_coef = 0x3, 70 .bg_vref_level = 0x8, 71 .avdd10_level = 0x4, 72 .avdd14_level = 0x4, 73 .sparepll = 0x0, 74 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a }, 75 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 76 }, { 77 .frequency = 75000000, 78 .vcocap = 0x3, 79 .filter = 0x0, 80 .ichpmp = 0x1, 81 .loadadj = 0x3, 82 .tmds_termadj = 0x9, 83 .tx_pu_value = 0x40, 84 .bg_temp_coef = 0x3, 85 .bg_vref_level = 0x8, 86 .avdd10_level = 0x4, 87 .avdd14_level = 0x4, 88 .sparepll = 0x0, 89 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a }, 90 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 91 }, { 92 .frequency = 150000000, 93 .vcocap = 0x3, 94 .filter = 0x0, 95 .ichpmp = 0x1, 96 .loadadj = 0x3, 97 .tmds_termadj = 0x9, 98 .tx_pu_value = 0x66, 99 .bg_temp_coef = 0x3, 100 .bg_vref_level = 0x8, 101 .avdd10_level = 0x4, 102 .avdd14_level = 0x4, 103 .sparepll = 0x0, 104 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a }, 105 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 106 }, { 107 .frequency = 300000000, 108 .vcocap = 0x3, 109 .filter = 0x0, 110 .ichpmp = 0x1, 111 .loadadj = 0x3, 112 .tmds_termadj = 0x9, 113 .tx_pu_value = 0x66, 114 .bg_temp_coef = 0x3, 115 .bg_vref_level = 0xa, 116 .avdd10_level = 0x4, 117 .avdd14_level = 0x4, 118 .sparepll = 0x0, 119 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f }, 120 .preemphasis = { 0x00, 0x17, 0x17, 0x17 }, 121 }, { 122 .frequency = 600000000, 123 .vcocap = 0x3, 124 .filter = 0x0, 125 .ichpmp = 0x1, 126 .loadadj = 0x3, 127 .tmds_termadj = 0x9, 128 .tx_pu_value = 0x66, 129 .bg_temp_coef = 0x3, 130 .bg_vref_level = 0x8, 131 .avdd10_level = 0x4, 132 .avdd14_level = 0x4, 133 .sparepll = 0x0, 134 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f }, 135 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 136 }, 137 }; 138 #else 139 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = { 140 { 141 .frequency = 75000000, 142 .vcocap = 0x3, 143 .filter = 0x0, 144 .ichpmp = 0x1, 145 .loadadj = 0x3, 146 .tmds_termadj = 0x9, 147 .tx_pu_value = 0x40, 148 .bg_temp_coef = 0x3, 149 .bg_vref_level = 0x8, 150 .avdd10_level = 0x4, 151 .avdd14_level = 0x4, 152 .sparepll = 0x0, 153 .drive_current = { 0x29, 0x29, 0x29, 0x29 }, 154 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 155 }, { 156 .frequency = 150000000, 157 .vcocap = 0x3, 158 .filter = 0x0, 159 .ichpmp = 0x1, 160 .loadadj = 0x3, 161 .tmds_termadj = 0x9, 162 .tx_pu_value = 0x66, 163 .bg_temp_coef = 0x3, 164 .bg_vref_level = 0x8, 165 .avdd10_level = 0x4, 166 .avdd14_level = 0x4, 167 .sparepll = 0x0, 168 .drive_current = { 0x30, 0x37, 0x37, 0x37 }, 169 .preemphasis = { 0x01, 0x02, 0x02, 0x02 }, 170 }, { 171 .frequency = 300000000, 172 .vcocap = 0x3, 173 .filter = 0x0, 174 .ichpmp = 0x6, 175 .loadadj = 0x3, 176 .tmds_termadj = 0x9, 177 .tx_pu_value = 0x66, 178 .bg_temp_coef = 0x3, 179 .bg_vref_level = 0xf, 180 .avdd10_level = 0x4, 181 .avdd14_level = 0x4, 182 .sparepll = 0x0, 183 .drive_current = { 0x30, 0x37, 0x37, 0x37 }, 184 .preemphasis = { 0x10, 0x3e, 0x3e, 0x3e }, 185 }, { 186 .frequency = 600000000, 187 .vcocap = 0x3, 188 .filter = 0x0, 189 .ichpmp = 0xa, 190 .loadadj = 0x3, 191 .tmds_termadj = 0xb, 192 .tx_pu_value = 0x66, 193 .bg_temp_coef = 0x3, 194 .bg_vref_level = 0xe, 195 .avdd10_level = 0x4, 196 .avdd14_level = 0x4, 197 .sparepll = 0x0, 198 .drive_current = { 0x35, 0x3e, 0x3e, 0x3e }, 199 .preemphasis = { 0x02, 0x3f, 0x3f, 0x3f }, 200 }, 201 }; 202 #endif 203 204 static const struct tegra_sor_hdmi_settings tegra186_sor_hdmi_defaults[] = { 205 { 206 .frequency = 54000000, 207 .vcocap = 0, 208 .filter = 5, 209 .ichpmp = 5, 210 .loadadj = 3, 211 .tmds_termadj = 0xf, 212 .tx_pu_value = 0, 213 .bg_temp_coef = 3, 214 .bg_vref_level = 8, 215 .avdd10_level = 4, 216 .avdd14_level = 4, 217 .sparepll = 0x54, 218 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 }, 219 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 220 }, { 221 .frequency = 75000000, 222 .vcocap = 1, 223 .filter = 5, 224 .ichpmp = 5, 225 .loadadj = 3, 226 .tmds_termadj = 0xf, 227 .tx_pu_value = 0, 228 .bg_temp_coef = 3, 229 .bg_vref_level = 8, 230 .avdd10_level = 4, 231 .avdd14_level = 4, 232 .sparepll = 0x44, 233 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 }, 234 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 235 }, { 236 .frequency = 150000000, 237 .vcocap = 3, 238 .filter = 5, 239 .ichpmp = 5, 240 .loadadj = 3, 241 .tmds_termadj = 15, 242 .tx_pu_value = 0x66 /* 0 */, 243 .bg_temp_coef = 3, 244 .bg_vref_level = 8, 245 .avdd10_level = 4, 246 .avdd14_level = 4, 247 .sparepll = 0x00, /* 0x34 */ 248 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 }, 249 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 250 }, { 251 .frequency = 300000000, 252 .vcocap = 3, 253 .filter = 5, 254 .ichpmp = 5, 255 .loadadj = 3, 256 .tmds_termadj = 15, 257 .tx_pu_value = 64, 258 .bg_temp_coef = 3, 259 .bg_vref_level = 8, 260 .avdd10_level = 4, 261 .avdd14_level = 4, 262 .sparepll = 0x34, 263 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 }, 264 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 265 }, { 266 .frequency = 600000000, 267 .vcocap = 3, 268 .filter = 5, 269 .ichpmp = 5, 270 .loadadj = 3, 271 .tmds_termadj = 12, 272 .tx_pu_value = 96, 273 .bg_temp_coef = 3, 274 .bg_vref_level = 8, 275 .avdd10_level = 4, 276 .avdd14_level = 4, 277 .sparepll = 0x34, 278 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 }, 279 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 280 } 281 }; 282 283 static const struct tegra_sor_hdmi_settings tegra194_sor_hdmi_defaults[] = { 284 { 285 .frequency = 54000000, 286 .vcocap = 0, 287 .filter = 5, 288 .ichpmp = 5, 289 .loadadj = 3, 290 .tmds_termadj = 0xf, 291 .tx_pu_value = 0, 292 .bg_temp_coef = 3, 293 .bg_vref_level = 8, 294 .avdd10_level = 4, 295 .avdd14_level = 4, 296 .sparepll = 0x54, 297 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 }, 298 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 299 }, { 300 .frequency = 75000000, 301 .vcocap = 1, 302 .filter = 5, 303 .ichpmp = 5, 304 .loadadj = 3, 305 .tmds_termadj = 0xf, 306 .tx_pu_value = 0, 307 .bg_temp_coef = 3, 308 .bg_vref_level = 8, 309 .avdd10_level = 4, 310 .avdd14_level = 4, 311 .sparepll = 0x44, 312 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 }, 313 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 314 }, { 315 .frequency = 150000000, 316 .vcocap = 3, 317 .filter = 5, 318 .ichpmp = 5, 319 .loadadj = 3, 320 .tmds_termadj = 15, 321 .tx_pu_value = 0x66 /* 0 */, 322 .bg_temp_coef = 3, 323 .bg_vref_level = 8, 324 .avdd10_level = 4, 325 .avdd14_level = 4, 326 .sparepll = 0x00, /* 0x34 */ 327 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 }, 328 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 329 }, { 330 .frequency = 300000000, 331 .vcocap = 3, 332 .filter = 5, 333 .ichpmp = 5, 334 .loadadj = 3, 335 .tmds_termadj = 15, 336 .tx_pu_value = 64, 337 .bg_temp_coef = 3, 338 .bg_vref_level = 8, 339 .avdd10_level = 4, 340 .avdd14_level = 4, 341 .sparepll = 0x34, 342 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 }, 343 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 344 }, { 345 .frequency = 600000000, 346 .vcocap = 3, 347 .filter = 5, 348 .ichpmp = 5, 349 .loadadj = 3, 350 .tmds_termadj = 12, 351 .tx_pu_value = 96, 352 .bg_temp_coef = 3, 353 .bg_vref_level = 8, 354 .avdd10_level = 4, 355 .avdd14_level = 4, 356 .sparepll = 0x34, 357 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 }, 358 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 359 } 360 }; 361 362 struct tegra_sor_regs { 363 unsigned int head_state0; 364 unsigned int head_state1; 365 unsigned int head_state2; 366 unsigned int head_state3; 367 unsigned int head_state4; 368 unsigned int head_state5; 369 unsigned int pll0; 370 unsigned int pll1; 371 unsigned int pll2; 372 unsigned int pll3; 373 unsigned int dp_padctl0; 374 unsigned int dp_padctl2; 375 }; 376 377 struct tegra_sor_soc { 378 bool supports_lvds; 379 bool supports_hdmi; 380 bool supports_dp; 381 bool supports_audio; 382 bool supports_hdcp; 383 384 const struct tegra_sor_regs *regs; 385 bool has_nvdisplay; 386 387 const struct tegra_sor_hdmi_settings *settings; 388 unsigned int num_settings; 389 390 const u8 *xbar_cfg; 391 const u8 *lane_map; 392 393 const u8 (*voltage_swing)[4][4]; 394 const u8 (*pre_emphasis)[4][4]; 395 const u8 (*post_cursor)[4][4]; 396 const u8 (*tx_pu)[4][4]; 397 }; 398 399 struct tegra_sor; 400 401 struct tegra_sor_ops { 402 const char *name; 403 int (*probe)(struct tegra_sor *sor); 404 void (*audio_enable)(struct tegra_sor *sor); 405 void (*audio_disable)(struct tegra_sor *sor); 406 }; 407 408 struct tegra_sor { 409 struct host1x_client client; 410 struct tegra_output output; 411 struct device *dev; 412 413 const struct tegra_sor_soc *soc; 414 void __iomem *regs; 415 unsigned int index; 416 unsigned int irq; 417 418 struct reset_control *rst; 419 struct clk *clk_parent; 420 struct clk *clk_safe; 421 struct clk *clk_out; 422 struct clk *clk_pad; 423 struct clk *clk_dp; 424 struct clk *clk; 425 426 u8 xbar_cfg[5]; 427 428 struct drm_dp_link link; 429 struct drm_dp_aux *aux; 430 431 struct drm_info_list *debugfs_files; 432 433 const struct tegra_sor_ops *ops; 434 enum tegra_io_pad pad; 435 436 /* for HDMI 2.0 */ 437 struct tegra_sor_hdmi_settings *settings; 438 unsigned int num_settings; 439 440 struct regulator *avdd_io_supply; 441 struct regulator *vdd_pll_supply; 442 struct regulator *hdmi_supply; 443 444 struct delayed_work scdc; 445 bool scdc_enabled; 446 447 struct tegra_hda_format format; 448 }; 449 450 struct tegra_sor_state { 451 struct drm_connector_state base; 452 453 unsigned int link_speed; 454 unsigned long pclk; 455 unsigned int bpc; 456 }; 457 458 static inline struct tegra_sor_state * 459 to_sor_state(struct drm_connector_state *state) 460 { 461 return container_of(state, struct tegra_sor_state, base); 462 } 463 464 struct tegra_sor_config { 465 u32 bits_per_pixel; 466 467 u32 active_polarity; 468 u32 active_count; 469 u32 tu_size; 470 u32 active_frac; 471 u32 watermark; 472 473 u32 hblank_symbols; 474 u32 vblank_symbols; 475 }; 476 477 static inline struct tegra_sor * 478 host1x_client_to_sor(struct host1x_client *client) 479 { 480 return container_of(client, struct tegra_sor, client); 481 } 482 483 static inline struct tegra_sor *to_sor(struct tegra_output *output) 484 { 485 return container_of(output, struct tegra_sor, output); 486 } 487 488 static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned int offset) 489 { 490 u32 value = readl(sor->regs + (offset << 2)); 491 492 trace_sor_readl(sor->dev, offset, value); 493 494 return value; 495 } 496 497 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, 498 unsigned int offset) 499 { 500 trace_sor_writel(sor->dev, offset, value); 501 writel(value, sor->regs + (offset << 2)); 502 } 503 504 static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent) 505 { 506 int err; 507 508 clk_disable_unprepare(sor->clk); 509 510 err = clk_set_parent(sor->clk_out, parent); 511 if (err < 0) 512 return err; 513 514 err = clk_prepare_enable(sor->clk); 515 if (err < 0) 516 return err; 517 518 return 0; 519 } 520 521 struct tegra_clk_sor_pad { 522 struct clk_hw hw; 523 struct tegra_sor *sor; 524 }; 525 526 static inline struct tegra_clk_sor_pad *to_pad(struct clk_hw *hw) 527 { 528 return container_of(hw, struct tegra_clk_sor_pad, hw); 529 } 530 531 static const char * const tegra_clk_sor_pad_parents[2][2] = { 532 { "pll_d_out0", "pll_dp" }, 533 { "pll_d2_out0", "pll_dp" }, 534 }; 535 536 /* 537 * Implementing ->set_parent() here isn't really required because the parent 538 * will be explicitly selected in the driver code via the DP_CLK_SEL mux in 539 * the SOR_CLK_CNTRL register. This is primarily for compatibility with the 540 * Tegra186 and later SoC generations where the BPMP implements this clock 541 * and doesn't expose the mux via the common clock framework. 542 */ 543 544 static int tegra_clk_sor_pad_set_parent(struct clk_hw *hw, u8 index) 545 { 546 struct tegra_clk_sor_pad *pad = to_pad(hw); 547 struct tegra_sor *sor = pad->sor; 548 u32 value; 549 550 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 551 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; 552 553 switch (index) { 554 case 0: 555 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; 556 break; 557 558 case 1: 559 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; 560 break; 561 } 562 563 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 564 565 return 0; 566 } 567 568 static u8 tegra_clk_sor_pad_get_parent(struct clk_hw *hw) 569 { 570 struct tegra_clk_sor_pad *pad = to_pad(hw); 571 struct tegra_sor *sor = pad->sor; 572 u8 parent = U8_MAX; 573 u32 value; 574 575 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 576 577 switch (value & SOR_CLK_CNTRL_DP_CLK_SEL_MASK) { 578 case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK: 579 case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK: 580 parent = 0; 581 break; 582 583 case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK: 584 case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK: 585 parent = 1; 586 break; 587 } 588 589 return parent; 590 } 591 592 static const struct clk_ops tegra_clk_sor_pad_ops = { 593 .determine_rate = clk_hw_determine_rate_no_reparent, 594 .set_parent = tegra_clk_sor_pad_set_parent, 595 .get_parent = tegra_clk_sor_pad_get_parent, 596 }; 597 598 static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor, 599 const char *name) 600 { 601 struct tegra_clk_sor_pad *pad; 602 struct clk_init_data init; 603 struct clk *clk; 604 605 pad = devm_kzalloc(sor->dev, sizeof(*pad), GFP_KERNEL); 606 if (!pad) 607 return ERR_PTR(-ENOMEM); 608 609 pad->sor = sor; 610 611 init.name = name; 612 init.flags = 0; 613 init.parent_names = tegra_clk_sor_pad_parents[sor->index]; 614 init.num_parents = ARRAY_SIZE(tegra_clk_sor_pad_parents[sor->index]); 615 init.ops = &tegra_clk_sor_pad_ops; 616 617 pad->hw.init = &init; 618 619 clk = devm_clk_register(sor->dev, &pad->hw); 620 621 return clk; 622 } 623 624 static void tegra_sor_filter_rates(struct tegra_sor *sor) 625 { 626 struct drm_dp_link *link = &sor->link; 627 unsigned int i; 628 629 /* Tegra only supports RBR, HBR and HBR2 */ 630 for (i = 0; i < link->num_rates; i++) { 631 switch (link->rates[i]) { 632 case 1620000: 633 case 2700000: 634 case 5400000: 635 break; 636 637 default: 638 DRM_DEBUG_KMS("link rate %lu kHz not supported\n", 639 link->rates[i]); 640 link->rates[i] = 0; 641 break; 642 } 643 } 644 645 drm_dp_link_update_rates(link); 646 } 647 648 static int tegra_sor_power_up_lanes(struct tegra_sor *sor, unsigned int lanes) 649 { 650 unsigned long timeout; 651 u32 value; 652 653 /* 654 * Clear or set the PD_TXD bit corresponding to each lane, depending 655 * on whether it is used or not. 656 */ 657 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 658 659 if (lanes <= 2) 660 value &= ~(SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) | 661 SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2])); 662 else 663 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) | 664 SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]); 665 666 if (lanes <= 1) 667 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]); 668 else 669 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]); 670 671 if (lanes == 0) 672 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]); 673 else 674 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]); 675 676 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 677 678 /* start lane sequencer */ 679 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | 680 SOR_LANE_SEQ_CTL_POWER_STATE_UP; 681 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); 682 683 timeout = jiffies + msecs_to_jiffies(250); 684 685 while (time_before(jiffies, timeout)) { 686 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 687 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) 688 break; 689 690 usleep_range(250, 1000); 691 } 692 693 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) 694 return -ETIMEDOUT; 695 696 return 0; 697 } 698 699 static int tegra_sor_power_down_lanes(struct tegra_sor *sor) 700 { 701 unsigned long timeout; 702 u32 value; 703 704 /* power down all lanes */ 705 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 706 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | 707 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2); 708 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 709 710 /* start lane sequencer */ 711 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP | 712 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN; 713 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); 714 715 timeout = jiffies + msecs_to_jiffies(250); 716 717 while (time_before(jiffies, timeout)) { 718 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 719 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) 720 break; 721 722 usleep_range(25, 100); 723 } 724 725 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) 726 return -ETIMEDOUT; 727 728 return 0; 729 } 730 731 static void tegra_sor_dp_precharge(struct tegra_sor *sor, unsigned int lanes) 732 { 733 u32 value; 734 735 /* pre-charge all used lanes */ 736 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 737 738 if (lanes <= 2) 739 value &= ~(SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) | 740 SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2])); 741 else 742 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) | 743 SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]); 744 745 if (lanes <= 1) 746 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]); 747 else 748 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]); 749 750 if (lanes == 0) 751 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]); 752 else 753 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]); 754 755 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 756 757 usleep_range(15, 100); 758 759 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 760 value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | 761 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0); 762 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 763 } 764 765 static void tegra_sor_dp_term_calibrate(struct tegra_sor *sor) 766 { 767 u32 mask = 0x08, adj = 0, value; 768 769 /* enable pad calibration logic */ 770 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 771 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; 772 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 773 774 value = tegra_sor_readl(sor, sor->soc->regs->pll1); 775 value |= SOR_PLL1_TMDS_TERM; 776 tegra_sor_writel(sor, value, sor->soc->regs->pll1); 777 778 while (mask) { 779 adj |= mask; 780 781 value = tegra_sor_readl(sor, sor->soc->regs->pll1); 782 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; 783 value |= SOR_PLL1_TMDS_TERMADJ(adj); 784 tegra_sor_writel(sor, value, sor->soc->regs->pll1); 785 786 usleep_range(100, 200); 787 788 value = tegra_sor_readl(sor, sor->soc->regs->pll1); 789 if (value & SOR_PLL1_TERM_COMPOUT) 790 adj &= ~mask; 791 792 mask >>= 1; 793 } 794 795 value = tegra_sor_readl(sor, sor->soc->regs->pll1); 796 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; 797 value |= SOR_PLL1_TMDS_TERMADJ(adj); 798 tegra_sor_writel(sor, value, sor->soc->regs->pll1); 799 800 /* disable pad calibration logic */ 801 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 802 value |= SOR_DP_PADCTL_PAD_CAL_PD; 803 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 804 } 805 806 static int tegra_sor_dp_link_apply_training(struct drm_dp_link *link) 807 { 808 struct tegra_sor *sor = container_of(link, struct tegra_sor, link); 809 u32 voltage_swing = 0, pre_emphasis = 0, post_cursor = 0; 810 const struct tegra_sor_soc *soc = sor->soc; 811 u32 pattern = 0, tx_pu = 0, value; 812 unsigned int i; 813 814 for (value = 0, i = 0; i < link->lanes; i++) { 815 u8 vs = link->train.request.voltage_swing[i]; 816 u8 pe = link->train.request.pre_emphasis[i]; 817 u8 pc = link->train.request.post_cursor[i]; 818 u8 shift = sor->soc->lane_map[i] << 3; 819 820 voltage_swing |= soc->voltage_swing[pc][vs][pe] << shift; 821 pre_emphasis |= soc->pre_emphasis[pc][vs][pe] << shift; 822 post_cursor |= soc->post_cursor[pc][vs][pe] << shift; 823 824 if (sor->soc->tx_pu[pc][vs][pe] > tx_pu) 825 tx_pu = sor->soc->tx_pu[pc][vs][pe]; 826 827 switch (link->train.pattern) { 828 case DP_TRAINING_PATTERN_DISABLE: 829 value = SOR_DP_TPG_SCRAMBLER_GALIOS | 830 SOR_DP_TPG_PATTERN_NONE; 831 break; 832 833 case DP_TRAINING_PATTERN_1: 834 value = SOR_DP_TPG_SCRAMBLER_NONE | 835 SOR_DP_TPG_PATTERN_TRAIN1; 836 break; 837 838 case DP_TRAINING_PATTERN_2: 839 value = SOR_DP_TPG_SCRAMBLER_NONE | 840 SOR_DP_TPG_PATTERN_TRAIN2; 841 break; 842 843 case DP_TRAINING_PATTERN_3: 844 value = SOR_DP_TPG_SCRAMBLER_NONE | 845 SOR_DP_TPG_PATTERN_TRAIN3; 846 break; 847 848 default: 849 return -EINVAL; 850 } 851 852 if (link->caps.channel_coding) 853 value |= SOR_DP_TPG_CHANNEL_CODING; 854 855 pattern = pattern << 8 | value; 856 } 857 858 tegra_sor_writel(sor, voltage_swing, SOR_LANE_DRIVE_CURRENT0); 859 tegra_sor_writel(sor, pre_emphasis, SOR_LANE_PREEMPHASIS0); 860 861 if (link->caps.tps3_supported) 862 tegra_sor_writel(sor, post_cursor, SOR_LANE_POSTCURSOR0); 863 864 tegra_sor_writel(sor, pattern, SOR_DP_TPG); 865 866 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 867 value &= ~SOR_DP_PADCTL_TX_PU_MASK; 868 value |= SOR_DP_PADCTL_TX_PU_ENABLE; 869 value |= SOR_DP_PADCTL_TX_PU(tx_pu); 870 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 871 872 usleep_range(20, 100); 873 874 return 0; 875 } 876 877 static int tegra_sor_dp_link_configure(struct drm_dp_link *link) 878 { 879 struct tegra_sor *sor = container_of(link, struct tegra_sor, link); 880 unsigned int rate, lanes; 881 u32 value; 882 int err; 883 884 rate = drm_dp_link_rate_to_bw_code(link->rate); 885 lanes = link->lanes; 886 887 /* configure link speed and lane count */ 888 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 889 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; 890 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate); 891 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 892 893 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); 894 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; 895 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes); 896 897 if (link->caps.enhanced_framing) 898 value |= SOR_DP_LINKCTL_ENHANCED_FRAME; 899 900 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); 901 902 usleep_range(400, 1000); 903 904 /* configure load pulse position adjustment */ 905 value = tegra_sor_readl(sor, sor->soc->regs->pll1); 906 value &= ~SOR_PLL1_LOADADJ_MASK; 907 908 switch (rate) { 909 case DP_LINK_BW_1_62: 910 value |= SOR_PLL1_LOADADJ(0x3); 911 break; 912 913 case DP_LINK_BW_2_7: 914 value |= SOR_PLL1_LOADADJ(0x4); 915 break; 916 917 case DP_LINK_BW_5_4: 918 value |= SOR_PLL1_LOADADJ(0x6); 919 break; 920 } 921 922 tegra_sor_writel(sor, value, sor->soc->regs->pll1); 923 924 /* use alternate scrambler reset for eDP */ 925 value = tegra_sor_readl(sor, SOR_DP_SPARE0); 926 927 if (link->edp == 0) 928 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; 929 else 930 value |= SOR_DP_SPARE_PANEL_INTERNAL; 931 932 tegra_sor_writel(sor, value, SOR_DP_SPARE0); 933 934 err = tegra_sor_power_down_lanes(sor); 935 if (err < 0) { 936 dev_err(sor->dev, "failed to power down lanes: %d\n", err); 937 return err; 938 } 939 940 /* power up and pre-charge lanes */ 941 err = tegra_sor_power_up_lanes(sor, lanes); 942 if (err < 0) { 943 dev_err(sor->dev, "failed to power up %u lane%s: %d\n", 944 lanes, str_plural(lanes), err); 945 return err; 946 } 947 948 tegra_sor_dp_precharge(sor, lanes); 949 950 return 0; 951 } 952 953 static const struct drm_dp_link_ops tegra_sor_dp_link_ops = { 954 .apply_training = tegra_sor_dp_link_apply_training, 955 .configure = tegra_sor_dp_link_configure, 956 }; 957 958 static void tegra_sor_super_update(struct tegra_sor *sor) 959 { 960 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); 961 tegra_sor_writel(sor, 1, SOR_SUPER_STATE0); 962 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); 963 } 964 965 static void tegra_sor_update(struct tegra_sor *sor) 966 { 967 tegra_sor_writel(sor, 0, SOR_STATE0); 968 tegra_sor_writel(sor, 1, SOR_STATE0); 969 tegra_sor_writel(sor, 0, SOR_STATE0); 970 } 971 972 static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout) 973 { 974 u32 value; 975 976 value = tegra_sor_readl(sor, SOR_PWM_DIV); 977 value &= ~SOR_PWM_DIV_MASK; 978 value |= 0x400; /* period */ 979 tegra_sor_writel(sor, value, SOR_PWM_DIV); 980 981 value = tegra_sor_readl(sor, SOR_PWM_CTL); 982 value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK; 983 value |= 0x400; /* duty cycle */ 984 value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */ 985 value |= SOR_PWM_CTL_TRIGGER; 986 tegra_sor_writel(sor, value, SOR_PWM_CTL); 987 988 timeout = jiffies + msecs_to_jiffies(timeout); 989 990 while (time_before(jiffies, timeout)) { 991 value = tegra_sor_readl(sor, SOR_PWM_CTL); 992 if ((value & SOR_PWM_CTL_TRIGGER) == 0) 993 return 0; 994 995 usleep_range(25, 100); 996 } 997 998 return -ETIMEDOUT; 999 } 1000 1001 static int tegra_sor_attach(struct tegra_sor *sor) 1002 { 1003 unsigned long value, timeout; 1004 1005 /* wake up in normal mode */ 1006 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 1007 value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE; 1008 value |= SOR_SUPER_STATE_MODE_NORMAL; 1009 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 1010 tegra_sor_super_update(sor); 1011 1012 /* attach */ 1013 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 1014 value |= SOR_SUPER_STATE_ATTACHED; 1015 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 1016 tegra_sor_super_update(sor); 1017 1018 timeout = jiffies + msecs_to_jiffies(250); 1019 1020 while (time_before(jiffies, timeout)) { 1021 value = tegra_sor_readl(sor, SOR_TEST); 1022 if ((value & SOR_TEST_ATTACHED) != 0) 1023 return 0; 1024 1025 usleep_range(25, 100); 1026 } 1027 1028 return -ETIMEDOUT; 1029 } 1030 1031 static int tegra_sor_wakeup(struct tegra_sor *sor) 1032 { 1033 unsigned long value, timeout; 1034 1035 timeout = jiffies + msecs_to_jiffies(250); 1036 1037 /* wait for head to wake up */ 1038 while (time_before(jiffies, timeout)) { 1039 value = tegra_sor_readl(sor, SOR_TEST); 1040 value &= SOR_TEST_HEAD_MODE_MASK; 1041 1042 if (value == SOR_TEST_HEAD_MODE_AWAKE) 1043 return 0; 1044 1045 usleep_range(25, 100); 1046 } 1047 1048 return -ETIMEDOUT; 1049 } 1050 1051 static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout) 1052 { 1053 u32 value; 1054 1055 value = tegra_sor_readl(sor, SOR_PWR); 1056 value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU; 1057 tegra_sor_writel(sor, value, SOR_PWR); 1058 1059 timeout = jiffies + msecs_to_jiffies(timeout); 1060 1061 while (time_before(jiffies, timeout)) { 1062 value = tegra_sor_readl(sor, SOR_PWR); 1063 if ((value & SOR_PWR_TRIGGER) == 0) 1064 return 0; 1065 1066 usleep_range(25, 100); 1067 } 1068 1069 return -ETIMEDOUT; 1070 } 1071 1072 struct tegra_sor_params { 1073 /* number of link clocks per line */ 1074 unsigned int num_clocks; 1075 /* ratio between input and output */ 1076 u64 ratio; 1077 /* precision factor */ 1078 u64 precision; 1079 1080 unsigned int active_polarity; 1081 unsigned int active_count; 1082 unsigned int active_frac; 1083 unsigned int tu_size; 1084 unsigned int error; 1085 }; 1086 1087 static int tegra_sor_compute_params(struct tegra_sor *sor, 1088 struct tegra_sor_params *params, 1089 unsigned int tu_size) 1090 { 1091 u64 active_sym, active_count, frac, approx; 1092 u32 active_polarity, active_frac = 0; 1093 const u64 f = params->precision; 1094 s64 error; 1095 1096 active_sym = params->ratio * tu_size; 1097 active_count = div_u64(active_sym, f) * f; 1098 frac = active_sym - active_count; 1099 1100 /* fraction < 0.5 */ 1101 if (frac >= (f / 2)) { 1102 active_polarity = 1; 1103 frac = f - frac; 1104 } else { 1105 active_polarity = 0; 1106 } 1107 1108 if (frac != 0) { 1109 frac = div_u64(f * f, frac); /* 1/fraction */ 1110 if (frac <= (15 * f)) { 1111 active_frac = div_u64(frac, f); 1112 1113 /* round up */ 1114 if (active_polarity) 1115 active_frac++; 1116 } else { 1117 active_frac = active_polarity ? 1 : 15; 1118 } 1119 } 1120 1121 if (active_frac == 1) 1122 active_polarity = 0; 1123 1124 if (active_polarity == 1) { 1125 if (active_frac) { 1126 approx = active_count + (active_frac * (f - 1)) * f; 1127 approx = div_u64(approx, active_frac * f); 1128 } else { 1129 approx = active_count + f; 1130 } 1131 } else { 1132 if (active_frac) 1133 approx = active_count + div_u64(f, active_frac); 1134 else 1135 approx = active_count; 1136 } 1137 1138 error = div_s64(active_sym - approx, tu_size); 1139 error *= params->num_clocks; 1140 1141 if (error <= 0 && abs(error) < params->error) { 1142 params->active_count = div_u64(active_count, f); 1143 params->active_polarity = active_polarity; 1144 params->active_frac = active_frac; 1145 params->error = abs(error); 1146 params->tu_size = tu_size; 1147 1148 if (error == 0) 1149 return true; 1150 } 1151 1152 return false; 1153 } 1154 1155 static int tegra_sor_compute_config(struct tegra_sor *sor, 1156 const struct drm_display_mode *mode, 1157 struct tegra_sor_config *config, 1158 struct drm_dp_link *link) 1159 { 1160 const u64 f = 100000, link_rate = link->rate * 1000; 1161 const u64 pclk = (u64)mode->clock * 1000; 1162 u64 input, output, watermark, num; 1163 struct tegra_sor_params params; 1164 u32 num_syms_per_line; 1165 unsigned int i; 1166 1167 if (!link_rate || !link->lanes || !pclk || !config->bits_per_pixel) 1168 return -EINVAL; 1169 1170 input = pclk * config->bits_per_pixel; 1171 output = link_rate * 8 * link->lanes; 1172 1173 if (input >= output) 1174 return -ERANGE; 1175 1176 memset(¶ms, 0, sizeof(params)); 1177 params.ratio = div64_u64(input * f, output); 1178 params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk); 1179 params.precision = f; 1180 params.error = 64 * f; 1181 params.tu_size = 64; 1182 1183 for (i = params.tu_size; i >= 32; i--) 1184 if (tegra_sor_compute_params(sor, ¶ms, i)) 1185 break; 1186 1187 if (params.active_frac == 0) { 1188 config->active_polarity = 0; 1189 config->active_count = params.active_count; 1190 1191 if (!params.active_polarity) 1192 config->active_count--; 1193 1194 config->tu_size = params.tu_size; 1195 config->active_frac = 1; 1196 } else { 1197 config->active_polarity = params.active_polarity; 1198 config->active_count = params.active_count; 1199 config->active_frac = params.active_frac; 1200 config->tu_size = params.tu_size; 1201 } 1202 1203 dev_dbg(sor->dev, 1204 "polarity: %d active count: %d tu size: %d active frac: %d\n", 1205 config->active_polarity, config->active_count, 1206 config->tu_size, config->active_frac); 1207 1208 watermark = params.ratio * config->tu_size * (f - params.ratio); 1209 watermark = div_u64(watermark, f); 1210 1211 watermark = div_u64(watermark + params.error, f); 1212 config->watermark = watermark + (config->bits_per_pixel / 8) + 2; 1213 num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) * 1214 (link->lanes * 8); 1215 1216 if (config->watermark > 30) { 1217 config->watermark = 30; 1218 dev_err(sor->dev, 1219 "unable to compute TU size, forcing watermark to %u\n", 1220 config->watermark); 1221 } else if (config->watermark > num_syms_per_line) { 1222 config->watermark = num_syms_per_line; 1223 dev_err(sor->dev, "watermark too high, forcing to %u\n", 1224 config->watermark); 1225 } 1226 1227 /* compute the number of symbols per horizontal blanking interval */ 1228 num = ((mode->htotal - mode->hdisplay) - 7) * link_rate; 1229 config->hblank_symbols = div_u64(num, pclk); 1230 1231 if (link->caps.enhanced_framing) 1232 config->hblank_symbols -= 3; 1233 1234 config->hblank_symbols -= 12 / link->lanes; 1235 1236 /* compute the number of symbols per vertical blanking interval */ 1237 num = (mode->hdisplay - 25) * link_rate; 1238 config->vblank_symbols = div_u64(num, pclk); 1239 config->vblank_symbols -= 36 / link->lanes + 4; 1240 1241 dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols, 1242 config->vblank_symbols); 1243 1244 return 0; 1245 } 1246 1247 static void tegra_sor_apply_config(struct tegra_sor *sor, 1248 const struct tegra_sor_config *config) 1249 { 1250 u32 value; 1251 1252 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); 1253 value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK; 1254 value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size); 1255 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); 1256 1257 value = tegra_sor_readl(sor, SOR_DP_CONFIG0); 1258 value &= ~SOR_DP_CONFIG_WATERMARK_MASK; 1259 value |= SOR_DP_CONFIG_WATERMARK(config->watermark); 1260 1261 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK; 1262 value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count); 1263 1264 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK; 1265 value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac); 1266 1267 if (config->active_polarity) 1268 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; 1269 else 1270 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; 1271 1272 value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE; 1273 value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE; 1274 tegra_sor_writel(sor, value, SOR_DP_CONFIG0); 1275 1276 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS); 1277 value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK; 1278 value |= config->hblank_symbols & 0xffff; 1279 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS); 1280 1281 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS); 1282 value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK; 1283 value |= config->vblank_symbols & 0xffff; 1284 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS); 1285 } 1286 1287 static void tegra_sor_mode_set(struct tegra_sor *sor, 1288 const struct drm_display_mode *mode, 1289 struct tegra_sor_state *state) 1290 { 1291 struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc); 1292 unsigned int vbe, vse, hbe, hse, vbs, hbs; 1293 u32 value; 1294 1295 value = tegra_sor_readl(sor, SOR_STATE1); 1296 value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK; 1297 value &= ~SOR_STATE_ASY_CRC_MODE_MASK; 1298 value &= ~SOR_STATE_ASY_OWNER_MASK; 1299 1300 value |= SOR_STATE_ASY_CRC_MODE_COMPLETE | 1301 SOR_STATE_ASY_OWNER(dc->pipe + 1); 1302 1303 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 1304 value &= ~SOR_STATE_ASY_HSYNCPOL; 1305 1306 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 1307 value |= SOR_STATE_ASY_HSYNCPOL; 1308 1309 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 1310 value &= ~SOR_STATE_ASY_VSYNCPOL; 1311 1312 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 1313 value |= SOR_STATE_ASY_VSYNCPOL; 1314 1315 switch (state->bpc) { 1316 case 16: 1317 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444; 1318 break; 1319 1320 case 12: 1321 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444; 1322 break; 1323 1324 case 10: 1325 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444; 1326 break; 1327 1328 case 8: 1329 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; 1330 break; 1331 1332 case 6: 1333 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444; 1334 break; 1335 1336 default: 1337 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; 1338 break; 1339 } 1340 1341 tegra_sor_writel(sor, value, SOR_STATE1); 1342 1343 /* 1344 * TODO: The video timing programming below doesn't seem to match the 1345 * register definitions. 1346 */ 1347 1348 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff); 1349 tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe); 1350 1351 /* sync end = sync width - 1 */ 1352 vse = mode->vsync_end - mode->vsync_start - 1; 1353 hse = mode->hsync_end - mode->hsync_start - 1; 1354 1355 value = ((vse & 0x7fff) << 16) | (hse & 0x7fff); 1356 tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe); 1357 1358 /* blank end = sync end + back porch */ 1359 vbe = vse + (mode->vtotal - mode->vsync_end); 1360 hbe = hse + (mode->htotal - mode->hsync_end); 1361 1362 value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff); 1363 tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe); 1364 1365 /* blank start = blank end + active */ 1366 vbs = vbe + mode->vdisplay; 1367 hbs = hbe + mode->hdisplay; 1368 1369 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff); 1370 tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe); 1371 1372 /* XXX interlacing support */ 1373 tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe); 1374 } 1375 1376 static int tegra_sor_detach(struct tegra_sor *sor) 1377 { 1378 unsigned long value, timeout; 1379 1380 /* switch to safe mode */ 1381 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 1382 value &= ~SOR_SUPER_STATE_MODE_NORMAL; 1383 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 1384 tegra_sor_super_update(sor); 1385 1386 timeout = jiffies + msecs_to_jiffies(250); 1387 1388 while (time_before(jiffies, timeout)) { 1389 value = tegra_sor_readl(sor, SOR_PWR); 1390 if (value & SOR_PWR_MODE_SAFE) 1391 break; 1392 } 1393 1394 if ((value & SOR_PWR_MODE_SAFE) == 0) 1395 return -ETIMEDOUT; 1396 1397 /* go to sleep */ 1398 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 1399 value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK; 1400 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 1401 tegra_sor_super_update(sor); 1402 1403 /* detach */ 1404 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 1405 value &= ~SOR_SUPER_STATE_ATTACHED; 1406 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 1407 tegra_sor_super_update(sor); 1408 1409 timeout = jiffies + msecs_to_jiffies(250); 1410 1411 while (time_before(jiffies, timeout)) { 1412 value = tegra_sor_readl(sor, SOR_TEST); 1413 if ((value & SOR_TEST_ATTACHED) == 0) 1414 break; 1415 1416 usleep_range(25, 100); 1417 } 1418 1419 if ((value & SOR_TEST_ATTACHED) != 0) 1420 return -ETIMEDOUT; 1421 1422 return 0; 1423 } 1424 1425 static int tegra_sor_power_down(struct tegra_sor *sor) 1426 { 1427 unsigned long value, timeout; 1428 int err; 1429 1430 value = tegra_sor_readl(sor, SOR_PWR); 1431 value &= ~SOR_PWR_NORMAL_STATE_PU; 1432 value |= SOR_PWR_TRIGGER; 1433 tegra_sor_writel(sor, value, SOR_PWR); 1434 1435 timeout = jiffies + msecs_to_jiffies(250); 1436 1437 while (time_before(jiffies, timeout)) { 1438 value = tegra_sor_readl(sor, SOR_PWR); 1439 if ((value & SOR_PWR_TRIGGER) == 0) 1440 return 0; 1441 1442 usleep_range(25, 100); 1443 } 1444 1445 if ((value & SOR_PWR_TRIGGER) != 0) 1446 return -ETIMEDOUT; 1447 1448 /* switch to safe parent clock */ 1449 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); 1450 if (err < 0) { 1451 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); 1452 return err; 1453 } 1454 1455 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 1456 value |= SOR_PLL2_PORT_POWERDOWN; 1457 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 1458 1459 usleep_range(20, 100); 1460 1461 value = tegra_sor_readl(sor, sor->soc->regs->pll0); 1462 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR; 1463 tegra_sor_writel(sor, value, sor->soc->regs->pll0); 1464 1465 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 1466 value |= SOR_PLL2_SEQ_PLLCAPPD; 1467 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; 1468 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 1469 1470 usleep_range(20, 100); 1471 1472 return 0; 1473 } 1474 1475 static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout) 1476 { 1477 u32 value; 1478 1479 timeout = jiffies + msecs_to_jiffies(timeout); 1480 1481 while (time_before(jiffies, timeout)) { 1482 value = tegra_sor_readl(sor, SOR_CRCA); 1483 if (value & SOR_CRCA_VALID) 1484 return 0; 1485 1486 usleep_range(100, 200); 1487 } 1488 1489 return -ETIMEDOUT; 1490 } 1491 1492 static int tegra_sor_show_crc(struct seq_file *s, void *data) 1493 { 1494 struct drm_info_node *node = s->private; 1495 struct tegra_sor *sor = node->info_ent->data; 1496 struct drm_crtc *crtc = sor->output.encoder.crtc; 1497 struct drm_device *drm = node->minor->dev; 1498 int err = 0; 1499 u32 value; 1500 1501 drm_modeset_lock_all(drm); 1502 1503 if (!crtc || !crtc->state->active) { 1504 err = -EBUSY; 1505 goto unlock; 1506 } 1507 1508 value = tegra_sor_readl(sor, SOR_STATE1); 1509 value &= ~SOR_STATE_ASY_CRC_MODE_MASK; 1510 tegra_sor_writel(sor, value, SOR_STATE1); 1511 1512 value = tegra_sor_readl(sor, SOR_CRC_CNTRL); 1513 value |= SOR_CRC_CNTRL_ENABLE; 1514 tegra_sor_writel(sor, value, SOR_CRC_CNTRL); 1515 1516 value = tegra_sor_readl(sor, SOR_TEST); 1517 value &= ~SOR_TEST_CRC_POST_SERIALIZE; 1518 tegra_sor_writel(sor, value, SOR_TEST); 1519 1520 err = tegra_sor_crc_wait(sor, 100); 1521 if (err < 0) 1522 goto unlock; 1523 1524 tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA); 1525 value = tegra_sor_readl(sor, SOR_CRCB); 1526 1527 seq_printf(s, "%08x\n", value); 1528 1529 unlock: 1530 drm_modeset_unlock_all(drm); 1531 return err; 1532 } 1533 1534 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name } 1535 1536 static const struct debugfs_reg32 tegra_sor_regs[] = { 1537 DEBUGFS_REG32(SOR_CTXSW), 1538 DEBUGFS_REG32(SOR_SUPER_STATE0), 1539 DEBUGFS_REG32(SOR_SUPER_STATE1), 1540 DEBUGFS_REG32(SOR_STATE0), 1541 DEBUGFS_REG32(SOR_STATE1), 1542 DEBUGFS_REG32(SOR_HEAD_STATE0(0)), 1543 DEBUGFS_REG32(SOR_HEAD_STATE0(1)), 1544 DEBUGFS_REG32(SOR_HEAD_STATE1(0)), 1545 DEBUGFS_REG32(SOR_HEAD_STATE1(1)), 1546 DEBUGFS_REG32(SOR_HEAD_STATE2(0)), 1547 DEBUGFS_REG32(SOR_HEAD_STATE2(1)), 1548 DEBUGFS_REG32(SOR_HEAD_STATE3(0)), 1549 DEBUGFS_REG32(SOR_HEAD_STATE3(1)), 1550 DEBUGFS_REG32(SOR_HEAD_STATE4(0)), 1551 DEBUGFS_REG32(SOR_HEAD_STATE4(1)), 1552 DEBUGFS_REG32(SOR_HEAD_STATE5(0)), 1553 DEBUGFS_REG32(SOR_HEAD_STATE5(1)), 1554 DEBUGFS_REG32(SOR_CRC_CNTRL), 1555 DEBUGFS_REG32(SOR_DP_DEBUG_MVID), 1556 DEBUGFS_REG32(SOR_CLK_CNTRL), 1557 DEBUGFS_REG32(SOR_CAP), 1558 DEBUGFS_REG32(SOR_PWR), 1559 DEBUGFS_REG32(SOR_TEST), 1560 DEBUGFS_REG32(SOR_PLL0), 1561 DEBUGFS_REG32(SOR_PLL1), 1562 DEBUGFS_REG32(SOR_PLL2), 1563 DEBUGFS_REG32(SOR_PLL3), 1564 DEBUGFS_REG32(SOR_CSTM), 1565 DEBUGFS_REG32(SOR_LVDS), 1566 DEBUGFS_REG32(SOR_CRCA), 1567 DEBUGFS_REG32(SOR_CRCB), 1568 DEBUGFS_REG32(SOR_BLANK), 1569 DEBUGFS_REG32(SOR_SEQ_CTL), 1570 DEBUGFS_REG32(SOR_LANE_SEQ_CTL), 1571 DEBUGFS_REG32(SOR_SEQ_INST(0)), 1572 DEBUGFS_REG32(SOR_SEQ_INST(1)), 1573 DEBUGFS_REG32(SOR_SEQ_INST(2)), 1574 DEBUGFS_REG32(SOR_SEQ_INST(3)), 1575 DEBUGFS_REG32(SOR_SEQ_INST(4)), 1576 DEBUGFS_REG32(SOR_SEQ_INST(5)), 1577 DEBUGFS_REG32(SOR_SEQ_INST(6)), 1578 DEBUGFS_REG32(SOR_SEQ_INST(7)), 1579 DEBUGFS_REG32(SOR_SEQ_INST(8)), 1580 DEBUGFS_REG32(SOR_SEQ_INST(9)), 1581 DEBUGFS_REG32(SOR_SEQ_INST(10)), 1582 DEBUGFS_REG32(SOR_SEQ_INST(11)), 1583 DEBUGFS_REG32(SOR_SEQ_INST(12)), 1584 DEBUGFS_REG32(SOR_SEQ_INST(13)), 1585 DEBUGFS_REG32(SOR_SEQ_INST(14)), 1586 DEBUGFS_REG32(SOR_SEQ_INST(15)), 1587 DEBUGFS_REG32(SOR_PWM_DIV), 1588 DEBUGFS_REG32(SOR_PWM_CTL), 1589 DEBUGFS_REG32(SOR_VCRC_A0), 1590 DEBUGFS_REG32(SOR_VCRC_A1), 1591 DEBUGFS_REG32(SOR_VCRC_B0), 1592 DEBUGFS_REG32(SOR_VCRC_B1), 1593 DEBUGFS_REG32(SOR_CCRC_A0), 1594 DEBUGFS_REG32(SOR_CCRC_A1), 1595 DEBUGFS_REG32(SOR_CCRC_B0), 1596 DEBUGFS_REG32(SOR_CCRC_B1), 1597 DEBUGFS_REG32(SOR_EDATA_A0), 1598 DEBUGFS_REG32(SOR_EDATA_A1), 1599 DEBUGFS_REG32(SOR_EDATA_B0), 1600 DEBUGFS_REG32(SOR_EDATA_B1), 1601 DEBUGFS_REG32(SOR_COUNT_A0), 1602 DEBUGFS_REG32(SOR_COUNT_A1), 1603 DEBUGFS_REG32(SOR_COUNT_B0), 1604 DEBUGFS_REG32(SOR_COUNT_B1), 1605 DEBUGFS_REG32(SOR_DEBUG_A0), 1606 DEBUGFS_REG32(SOR_DEBUG_A1), 1607 DEBUGFS_REG32(SOR_DEBUG_B0), 1608 DEBUGFS_REG32(SOR_DEBUG_B1), 1609 DEBUGFS_REG32(SOR_TRIG), 1610 DEBUGFS_REG32(SOR_MSCHECK), 1611 DEBUGFS_REG32(SOR_XBAR_CTRL), 1612 DEBUGFS_REG32(SOR_XBAR_POL), 1613 DEBUGFS_REG32(SOR_DP_LINKCTL0), 1614 DEBUGFS_REG32(SOR_DP_LINKCTL1), 1615 DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT0), 1616 DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT1), 1617 DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT0), 1618 DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT1), 1619 DEBUGFS_REG32(SOR_LANE_PREEMPHASIS0), 1620 DEBUGFS_REG32(SOR_LANE_PREEMPHASIS1), 1621 DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS0), 1622 DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS1), 1623 DEBUGFS_REG32(SOR_LANE_POSTCURSOR0), 1624 DEBUGFS_REG32(SOR_LANE_POSTCURSOR1), 1625 DEBUGFS_REG32(SOR_DP_CONFIG0), 1626 DEBUGFS_REG32(SOR_DP_CONFIG1), 1627 DEBUGFS_REG32(SOR_DP_MN0), 1628 DEBUGFS_REG32(SOR_DP_MN1), 1629 DEBUGFS_REG32(SOR_DP_PADCTL0), 1630 DEBUGFS_REG32(SOR_DP_PADCTL1), 1631 DEBUGFS_REG32(SOR_DP_PADCTL2), 1632 DEBUGFS_REG32(SOR_DP_DEBUG0), 1633 DEBUGFS_REG32(SOR_DP_DEBUG1), 1634 DEBUGFS_REG32(SOR_DP_SPARE0), 1635 DEBUGFS_REG32(SOR_DP_SPARE1), 1636 DEBUGFS_REG32(SOR_DP_AUDIO_CTRL), 1637 DEBUGFS_REG32(SOR_DP_AUDIO_HBLANK_SYMBOLS), 1638 DEBUGFS_REG32(SOR_DP_AUDIO_VBLANK_SYMBOLS), 1639 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_HEADER), 1640 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK0), 1641 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK1), 1642 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK2), 1643 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK3), 1644 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK4), 1645 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK5), 1646 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK6), 1647 DEBUGFS_REG32(SOR_DP_TPG), 1648 DEBUGFS_REG32(SOR_DP_TPG_CONFIG), 1649 DEBUGFS_REG32(SOR_DP_LQ_CSTM0), 1650 DEBUGFS_REG32(SOR_DP_LQ_CSTM1), 1651 DEBUGFS_REG32(SOR_DP_LQ_CSTM2), 1652 }; 1653 1654 static int tegra_sor_show_regs(struct seq_file *s, void *data) 1655 { 1656 struct drm_info_node *node = s->private; 1657 struct tegra_sor *sor = node->info_ent->data; 1658 struct drm_crtc *crtc = sor->output.encoder.crtc; 1659 struct drm_device *drm = node->minor->dev; 1660 unsigned int i; 1661 int err = 0; 1662 1663 drm_modeset_lock_all(drm); 1664 1665 if (!crtc || !crtc->state->active) { 1666 err = -EBUSY; 1667 goto unlock; 1668 } 1669 1670 for (i = 0; i < ARRAY_SIZE(tegra_sor_regs); i++) { 1671 unsigned int offset = tegra_sor_regs[i].offset; 1672 1673 seq_printf(s, "%-38s %#05x %08x\n", tegra_sor_regs[i].name, 1674 offset, tegra_sor_readl(sor, offset)); 1675 } 1676 1677 unlock: 1678 drm_modeset_unlock_all(drm); 1679 return err; 1680 } 1681 1682 static const struct drm_info_list debugfs_files[] = { 1683 { "crc", tegra_sor_show_crc, 0, NULL }, 1684 { "regs", tegra_sor_show_regs, 0, NULL }, 1685 }; 1686 1687 static int tegra_sor_late_register(struct drm_connector *connector) 1688 { 1689 struct tegra_output *output = connector_to_output(connector); 1690 unsigned int i, count = ARRAY_SIZE(debugfs_files); 1691 struct drm_minor *minor = connector->dev->primary; 1692 struct dentry *root = connector->debugfs_entry; 1693 struct tegra_sor *sor = to_sor(output); 1694 1695 sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), 1696 GFP_KERNEL); 1697 if (!sor->debugfs_files) 1698 return -ENOMEM; 1699 1700 for (i = 0; i < count; i++) 1701 sor->debugfs_files[i].data = sor; 1702 1703 drm_debugfs_create_files(sor->debugfs_files, count, root, minor); 1704 1705 return 0; 1706 } 1707 1708 static void tegra_sor_early_unregister(struct drm_connector *connector) 1709 { 1710 struct tegra_output *output = connector_to_output(connector); 1711 unsigned int count = ARRAY_SIZE(debugfs_files); 1712 struct tegra_sor *sor = to_sor(output); 1713 1714 drm_debugfs_remove_files(sor->debugfs_files, count, 1715 connector->debugfs_entry, 1716 connector->dev->primary); 1717 kfree(sor->debugfs_files); 1718 sor->debugfs_files = NULL; 1719 } 1720 1721 static void tegra_sor_connector_reset(struct drm_connector *connector) 1722 { 1723 struct tegra_sor_state *state; 1724 1725 state = kzalloc_obj(*state); 1726 if (!state) 1727 return; 1728 1729 if (connector->state) { 1730 __drm_atomic_helper_connector_destroy_state(connector->state); 1731 kfree(connector->state); 1732 } 1733 1734 __drm_atomic_helper_connector_reset(connector, &state->base); 1735 } 1736 1737 static enum drm_connector_status 1738 tegra_sor_connector_detect(struct drm_connector *connector, bool force) 1739 { 1740 struct tegra_output *output = connector_to_output(connector); 1741 struct tegra_sor *sor = to_sor(output); 1742 1743 if (sor->aux) 1744 return drm_dp_aux_detect(sor->aux); 1745 1746 return tegra_output_connector_detect(connector, force); 1747 } 1748 1749 static struct drm_connector_state * 1750 tegra_sor_connector_duplicate_state(struct drm_connector *connector) 1751 { 1752 struct tegra_sor_state *state = to_sor_state(connector->state); 1753 struct tegra_sor_state *copy; 1754 1755 copy = kmemdup(state, sizeof(*state), GFP_KERNEL); 1756 if (!copy) 1757 return NULL; 1758 1759 __drm_atomic_helper_connector_duplicate_state(connector, ©->base); 1760 1761 return ©->base; 1762 } 1763 1764 static const struct drm_connector_funcs tegra_sor_connector_funcs = { 1765 .reset = tegra_sor_connector_reset, 1766 .detect = tegra_sor_connector_detect, 1767 .fill_modes = drm_helper_probe_single_connector_modes, 1768 .destroy = tegra_output_connector_destroy, 1769 .atomic_duplicate_state = tegra_sor_connector_duplicate_state, 1770 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1771 .late_register = tegra_sor_late_register, 1772 .early_unregister = tegra_sor_early_unregister, 1773 }; 1774 1775 static int tegra_sor_connector_get_modes(struct drm_connector *connector) 1776 { 1777 struct tegra_output *output = connector_to_output(connector); 1778 struct tegra_sor *sor = to_sor(output); 1779 int err; 1780 1781 if (sor->aux) 1782 drm_dp_aux_enable(sor->aux); 1783 1784 err = tegra_output_connector_get_modes(connector); 1785 1786 if (sor->aux) 1787 drm_dp_aux_disable(sor->aux); 1788 1789 return err; 1790 } 1791 1792 static enum drm_mode_status 1793 tegra_sor_connector_mode_valid(struct drm_connector *connector, 1794 const struct drm_display_mode *mode) 1795 { 1796 return MODE_OK; 1797 } 1798 1799 static const struct drm_connector_helper_funcs tegra_sor_connector_helper_funcs = { 1800 .get_modes = tegra_sor_connector_get_modes, 1801 .mode_valid = tegra_sor_connector_mode_valid, 1802 }; 1803 1804 static int 1805 tegra_sor_encoder_atomic_check(struct drm_encoder *encoder, 1806 struct drm_crtc_state *crtc_state, 1807 struct drm_connector_state *conn_state) 1808 { 1809 struct tegra_output *output = encoder_to_output(encoder); 1810 struct tegra_sor_state *state = to_sor_state(conn_state); 1811 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc); 1812 unsigned long pclk = crtc_state->mode.clock * 1000; 1813 struct tegra_sor *sor = to_sor(output); 1814 struct drm_display_info *info; 1815 int err; 1816 1817 info = &output->connector.display_info; 1818 1819 /* 1820 * For HBR2 modes, the SOR brick needs to use the x20 multiplier, so 1821 * the pixel clock must be corrected accordingly. 1822 */ 1823 if (pclk >= 340000000) { 1824 state->link_speed = 20; 1825 state->pclk = pclk / 2; 1826 } else { 1827 state->link_speed = 10; 1828 state->pclk = pclk; 1829 } 1830 1831 err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent, 1832 pclk, 0); 1833 if (err < 0) { 1834 dev_err(output->dev, "failed to setup CRTC state: %d\n", err); 1835 return err; 1836 } 1837 1838 switch (info->bpc) { 1839 case 8: 1840 case 6: 1841 state->bpc = info->bpc; 1842 break; 1843 1844 default: 1845 DRM_DEBUG_KMS("%u bits-per-color not supported\n", info->bpc); 1846 state->bpc = 8; 1847 break; 1848 } 1849 1850 return 0; 1851 } 1852 1853 static inline u32 tegra_sor_hdmi_subpack(const u8 *ptr, size_t size) 1854 { 1855 u32 value = 0; 1856 size_t i; 1857 1858 for (i = size; i > 0; i--) 1859 value = (value << 8) | ptr[i - 1]; 1860 1861 return value; 1862 } 1863 1864 static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor, 1865 const void *data, size_t size) 1866 { 1867 const u8 *ptr = data; 1868 unsigned long offset; 1869 size_t i; 1870 u32 value; 1871 1872 switch (ptr[0]) { 1873 case HDMI_INFOFRAME_TYPE_AVI: 1874 offset = SOR_HDMI_AVI_INFOFRAME_HEADER; 1875 break; 1876 1877 case HDMI_INFOFRAME_TYPE_AUDIO: 1878 offset = SOR_HDMI_AUDIO_INFOFRAME_HEADER; 1879 break; 1880 1881 case HDMI_INFOFRAME_TYPE_VENDOR: 1882 offset = SOR_HDMI_VSI_INFOFRAME_HEADER; 1883 break; 1884 1885 default: 1886 dev_err(sor->dev, "unsupported infoframe type: %02x\n", 1887 ptr[0]); 1888 return; 1889 } 1890 1891 value = INFOFRAME_HEADER_TYPE(ptr[0]) | 1892 INFOFRAME_HEADER_VERSION(ptr[1]) | 1893 INFOFRAME_HEADER_LEN(ptr[2]); 1894 tegra_sor_writel(sor, value, offset); 1895 offset++; 1896 1897 /* 1898 * Each subpack contains 7 bytes, divided into: 1899 * - subpack_low: bytes 0 - 3 1900 * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00) 1901 */ 1902 for (i = 3; i < size; i += 7) { 1903 size_t rem = size - i, num = min_t(size_t, rem, 4); 1904 1905 value = tegra_sor_hdmi_subpack(&ptr[i], num); 1906 tegra_sor_writel(sor, value, offset++); 1907 1908 num = min_t(size_t, rem - num, 3); 1909 1910 value = tegra_sor_hdmi_subpack(&ptr[i + 4], num); 1911 tegra_sor_writel(sor, value, offset++); 1912 } 1913 } 1914 1915 static int 1916 tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor, 1917 const struct drm_display_mode *mode) 1918 { 1919 u8 buffer[HDMI_INFOFRAME_SIZE(AVI)]; 1920 struct hdmi_avi_infoframe frame; 1921 u32 value; 1922 int err; 1923 1924 /* disable AVI infoframe */ 1925 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); 1926 value &= ~INFOFRAME_CTRL_SINGLE; 1927 value &= ~INFOFRAME_CTRL_OTHER; 1928 value &= ~INFOFRAME_CTRL_ENABLE; 1929 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); 1930 1931 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, 1932 &sor->output.connector, mode); 1933 if (err < 0) { 1934 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); 1935 return err; 1936 } 1937 1938 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 1939 if (err < 0) { 1940 dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err); 1941 return err; 1942 } 1943 1944 tegra_sor_hdmi_write_infopack(sor, buffer, err); 1945 1946 /* enable AVI infoframe */ 1947 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); 1948 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE; 1949 value |= INFOFRAME_CTRL_ENABLE; 1950 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); 1951 1952 return 0; 1953 } 1954 1955 static void tegra_sor_write_eld(struct tegra_sor *sor) 1956 { 1957 size_t length = drm_eld_size(sor->output.connector.eld), i; 1958 1959 for (i = 0; i < length; i++) 1960 tegra_sor_writel(sor, i << 8 | sor->output.connector.eld[i], 1961 SOR_AUDIO_HDA_ELD_BUFWR); 1962 1963 /* 1964 * The HDA codec will always report an ELD buffer size of 96 bytes and 1965 * the HDA codec driver will check that each byte read from the buffer 1966 * is valid. Therefore every byte must be written, even if no 96 bytes 1967 * were parsed from EDID. 1968 */ 1969 for (i = length; i < 96; i++) 1970 tegra_sor_writel(sor, i << 8 | 0, SOR_AUDIO_HDA_ELD_BUFWR); 1971 } 1972 1973 static void tegra_sor_audio_prepare(struct tegra_sor *sor) 1974 { 1975 u32 value; 1976 1977 /* 1978 * Enable and unmask the HDA codec SCRATCH0 register interrupt. This 1979 * is used for interoperability between the HDA codec driver and the 1980 * HDMI/DP driver. 1981 */ 1982 value = SOR_INT_CODEC_SCRATCH1 | SOR_INT_CODEC_SCRATCH0; 1983 tegra_sor_writel(sor, value, SOR_INT_ENABLE); 1984 tegra_sor_writel(sor, value, SOR_INT_MASK); 1985 1986 tegra_sor_write_eld(sor); 1987 1988 value = SOR_AUDIO_HDA_PRESENSE_ELDV | SOR_AUDIO_HDA_PRESENSE_PD; 1989 tegra_sor_writel(sor, value, SOR_AUDIO_HDA_PRESENSE); 1990 } 1991 1992 static void tegra_sor_audio_unprepare(struct tegra_sor *sor) 1993 { 1994 tegra_sor_writel(sor, 0, SOR_AUDIO_HDA_PRESENSE); 1995 tegra_sor_writel(sor, 0, SOR_INT_MASK); 1996 tegra_sor_writel(sor, 0, SOR_INT_ENABLE); 1997 } 1998 1999 static void tegra_sor_audio_enable(struct tegra_sor *sor) 2000 { 2001 u32 value; 2002 2003 value = tegra_sor_readl(sor, SOR_AUDIO_CNTRL); 2004 2005 /* select HDA audio input */ 2006 value &= ~SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_MASK); 2007 value |= SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_HDA); 2008 2009 /* inject null samples */ 2010 if (sor->format.channels != 2) 2011 value &= ~SOR_AUDIO_CNTRL_INJECT_NULLSMPL; 2012 else 2013 value |= SOR_AUDIO_CNTRL_INJECT_NULLSMPL; 2014 2015 value |= SOR_AUDIO_CNTRL_AFIFO_FLUSH; 2016 2017 tegra_sor_writel(sor, value, SOR_AUDIO_CNTRL); 2018 2019 /* enable advertising HBR capability */ 2020 tegra_sor_writel(sor, SOR_AUDIO_SPARE_HBR_ENABLE, SOR_AUDIO_SPARE); 2021 } 2022 2023 static int tegra_sor_hdmi_enable_audio_infoframe(struct tegra_sor *sor) 2024 { 2025 u8 buffer[HDMI_INFOFRAME_SIZE(AUDIO)]; 2026 struct hdmi_audio_infoframe frame; 2027 u32 value; 2028 int err; 2029 2030 err = hdmi_audio_infoframe_init(&frame); 2031 if (err < 0) { 2032 dev_err(sor->dev, "failed to setup audio infoframe: %d\n", err); 2033 return err; 2034 } 2035 2036 frame.channels = sor->format.channels; 2037 2038 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer)); 2039 if (err < 0) { 2040 dev_err(sor->dev, "failed to pack audio infoframe: %d\n", err); 2041 return err; 2042 } 2043 2044 tegra_sor_hdmi_write_infopack(sor, buffer, err); 2045 2046 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); 2047 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE; 2048 value |= INFOFRAME_CTRL_ENABLE; 2049 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); 2050 2051 return 0; 2052 } 2053 2054 static void tegra_sor_hdmi_audio_enable(struct tegra_sor *sor) 2055 { 2056 u32 value; 2057 2058 tegra_sor_audio_enable(sor); 2059 2060 tegra_sor_writel(sor, 0, SOR_HDMI_ACR_CTRL); 2061 2062 value = SOR_HDMI_SPARE_ACR_PRIORITY_HIGH | 2063 SOR_HDMI_SPARE_CTS_RESET(1) | 2064 SOR_HDMI_SPARE_HW_CTS_ENABLE; 2065 tegra_sor_writel(sor, value, SOR_HDMI_SPARE); 2066 2067 /* enable HW CTS */ 2068 value = SOR_HDMI_ACR_SUBPACK_LOW_SB1(0); 2069 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_LOW); 2070 2071 /* allow packet to be sent */ 2072 value = SOR_HDMI_ACR_SUBPACK_HIGH_ENABLE; 2073 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_HIGH); 2074 2075 /* reset N counter and enable lookup */ 2076 value = SOR_HDMI_AUDIO_N_RESET | SOR_HDMI_AUDIO_N_LOOKUP; 2077 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N); 2078 2079 value = (24000 * 4096) / (128 * sor->format.sample_rate / 1000); 2080 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0320); 2081 tegra_sor_writel(sor, 4096, SOR_AUDIO_NVAL_0320); 2082 2083 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0441); 2084 tegra_sor_writel(sor, 4704, SOR_AUDIO_NVAL_0441); 2085 2086 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0882); 2087 tegra_sor_writel(sor, 9408, SOR_AUDIO_NVAL_0882); 2088 2089 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_1764); 2090 tegra_sor_writel(sor, 18816, SOR_AUDIO_NVAL_1764); 2091 2092 value = (24000 * 6144) / (128 * sor->format.sample_rate / 1000); 2093 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0480); 2094 tegra_sor_writel(sor, 6144, SOR_AUDIO_NVAL_0480); 2095 2096 value = (24000 * 12288) / (128 * sor->format.sample_rate / 1000); 2097 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0960); 2098 tegra_sor_writel(sor, 12288, SOR_AUDIO_NVAL_0960); 2099 2100 value = (24000 * 24576) / (128 * sor->format.sample_rate / 1000); 2101 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_1920); 2102 tegra_sor_writel(sor, 24576, SOR_AUDIO_NVAL_1920); 2103 2104 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_N); 2105 value &= ~SOR_HDMI_AUDIO_N_RESET; 2106 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N); 2107 2108 tegra_sor_hdmi_enable_audio_infoframe(sor); 2109 } 2110 2111 static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor) 2112 { 2113 u32 value; 2114 2115 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); 2116 value &= ~INFOFRAME_CTRL_ENABLE; 2117 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); 2118 } 2119 2120 static void tegra_sor_hdmi_audio_disable(struct tegra_sor *sor) 2121 { 2122 tegra_sor_hdmi_disable_audio_infoframe(sor); 2123 } 2124 2125 static struct tegra_sor_hdmi_settings * 2126 tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency) 2127 { 2128 unsigned int i; 2129 2130 for (i = 0; i < sor->num_settings; i++) 2131 if (frequency <= sor->settings[i].frequency) 2132 return &sor->settings[i]; 2133 2134 return NULL; 2135 } 2136 2137 static void tegra_sor_hdmi_disable_scrambling(struct tegra_sor *sor) 2138 { 2139 u32 value; 2140 2141 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); 2142 value &= ~SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4; 2143 value &= ~SOR_HDMI2_CTRL_SCRAMBLE; 2144 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); 2145 } 2146 2147 static void tegra_sor_hdmi_scdc_disable(struct tegra_sor *sor) 2148 { 2149 drm_scdc_set_high_tmds_clock_ratio(&sor->output.connector, false); 2150 drm_scdc_set_scrambling(&sor->output.connector, false); 2151 2152 tegra_sor_hdmi_disable_scrambling(sor); 2153 } 2154 2155 static void tegra_sor_hdmi_scdc_stop(struct tegra_sor *sor) 2156 { 2157 if (sor->scdc_enabled) { 2158 cancel_delayed_work_sync(&sor->scdc); 2159 tegra_sor_hdmi_scdc_disable(sor); 2160 } 2161 } 2162 2163 static void tegra_sor_hdmi_enable_scrambling(struct tegra_sor *sor) 2164 { 2165 u32 value; 2166 2167 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); 2168 value |= SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4; 2169 value |= SOR_HDMI2_CTRL_SCRAMBLE; 2170 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); 2171 } 2172 2173 static void tegra_sor_hdmi_scdc_enable(struct tegra_sor *sor) 2174 { 2175 drm_scdc_set_high_tmds_clock_ratio(&sor->output.connector, true); 2176 drm_scdc_set_scrambling(&sor->output.connector, true); 2177 2178 tegra_sor_hdmi_enable_scrambling(sor); 2179 } 2180 2181 static void tegra_sor_hdmi_scdc_work(struct work_struct *work) 2182 { 2183 struct tegra_sor *sor = container_of(work, struct tegra_sor, scdc.work); 2184 2185 if (!drm_scdc_get_scrambling_status(&sor->output.connector)) { 2186 DRM_DEBUG_KMS("SCDC not scrambled\n"); 2187 tegra_sor_hdmi_scdc_enable(sor); 2188 } 2189 2190 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000)); 2191 } 2192 2193 static void tegra_sor_hdmi_scdc_start(struct tegra_sor *sor) 2194 { 2195 struct drm_scdc *scdc = &sor->output.connector.display_info.hdmi.scdc; 2196 struct drm_display_mode *mode; 2197 2198 mode = &sor->output.encoder.crtc->state->adjusted_mode; 2199 2200 if (mode->clock >= 340000 && scdc->supported) { 2201 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000)); 2202 tegra_sor_hdmi_scdc_enable(sor); 2203 sor->scdc_enabled = true; 2204 } 2205 } 2206 2207 static void tegra_sor_hdmi_disable(struct drm_encoder *encoder) 2208 { 2209 struct tegra_output *output = encoder_to_output(encoder); 2210 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 2211 struct tegra_sor *sor = to_sor(output); 2212 u32 value; 2213 int err; 2214 2215 tegra_sor_audio_unprepare(sor); 2216 tegra_sor_hdmi_scdc_stop(sor); 2217 2218 err = tegra_sor_detach(sor); 2219 if (err < 0) 2220 dev_err(sor->dev, "failed to detach SOR: %d\n", err); 2221 2222 tegra_sor_writel(sor, 0, SOR_STATE1); 2223 tegra_sor_update(sor); 2224 2225 /* disable display to SOR clock */ 2226 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 2227 2228 if (!sor->soc->has_nvdisplay) 2229 value &= ~SOR1_TIMING_CYA; 2230 2231 value &= ~SOR_ENABLE(sor->index); 2232 2233 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 2234 2235 tegra_dc_commit(dc); 2236 2237 err = tegra_sor_power_down(sor); 2238 if (err < 0) 2239 dev_err(sor->dev, "failed to power down SOR: %d\n", err); 2240 2241 err = tegra_io_pad_power_disable(sor->pad); 2242 if (err < 0) 2243 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err); 2244 2245 host1x_client_suspend(&sor->client); 2246 } 2247 2248 static void tegra_sor_hdmi_enable(struct drm_encoder *encoder) 2249 { 2250 struct tegra_output *output = encoder_to_output(encoder); 2251 unsigned int h_ref_to_sync = 1, pulse_start, max_ac; 2252 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 2253 struct tegra_sor_hdmi_settings *settings; 2254 struct tegra_sor *sor = to_sor(output); 2255 struct tegra_sor_state *state; 2256 struct drm_display_mode *mode; 2257 unsigned long rate, pclk; 2258 unsigned int div, i; 2259 u32 value; 2260 int err; 2261 2262 state = to_sor_state(output->connector.state); 2263 mode = &encoder->crtc->state->adjusted_mode; 2264 pclk = mode->clock * 1000; 2265 2266 err = host1x_client_resume(&sor->client); 2267 if (err < 0) { 2268 dev_err(sor->dev, "failed to resume: %d\n", err); 2269 return; 2270 } 2271 2272 /* switch to safe parent clock */ 2273 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); 2274 if (err < 0) { 2275 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); 2276 return; 2277 } 2278 2279 div = clk_get_rate(sor->clk) / 1000000 * 4; 2280 2281 err = tegra_io_pad_power_enable(sor->pad); 2282 if (err < 0) 2283 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err); 2284 2285 usleep_range(20, 100); 2286 2287 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 2288 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; 2289 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 2290 2291 usleep_range(20, 100); 2292 2293 value = tegra_sor_readl(sor, sor->soc->regs->pll3); 2294 value &= ~SOR_PLL3_PLL_VDD_MODE_3V3; 2295 tegra_sor_writel(sor, value, sor->soc->regs->pll3); 2296 2297 value = tegra_sor_readl(sor, sor->soc->regs->pll0); 2298 value &= ~SOR_PLL0_VCOPD; 2299 value &= ~SOR_PLL0_PWR; 2300 tegra_sor_writel(sor, value, sor->soc->regs->pll0); 2301 2302 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 2303 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; 2304 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 2305 2306 usleep_range(200, 400); 2307 2308 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 2309 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; 2310 value &= ~SOR_PLL2_PORT_POWERDOWN; 2311 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 2312 2313 usleep_range(20, 100); 2314 2315 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 2316 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | 2317 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2; 2318 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 2319 2320 while (true) { 2321 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 2322 if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0) 2323 break; 2324 2325 usleep_range(250, 1000); 2326 } 2327 2328 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | 2329 SOR_LANE_SEQ_CTL_POWER_STATE_UP | SOR_LANE_SEQ_CTL_DELAY(5); 2330 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); 2331 2332 while (true) { 2333 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 2334 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) 2335 break; 2336 2337 usleep_range(250, 1000); 2338 } 2339 2340 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 2341 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; 2342 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; 2343 2344 if (mode->clock < 340000) { 2345 DRM_DEBUG_KMS("setting 2.7 GHz link speed\n"); 2346 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70; 2347 } else { 2348 DRM_DEBUG_KMS("setting 5.4 GHz link speed\n"); 2349 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40; 2350 } 2351 2352 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; 2353 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 2354 2355 /* SOR pad PLL stabilization time */ 2356 usleep_range(250, 1000); 2357 2358 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); 2359 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; 2360 value |= SOR_DP_LINKCTL_LANE_COUNT(4); 2361 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); 2362 2363 value = tegra_sor_readl(sor, SOR_DP_SPARE0); 2364 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE; 2365 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; 2366 value &= ~SOR_DP_SPARE_SEQ_ENABLE; 2367 value &= ~SOR_DP_SPARE_MACRO_SOR_CLK; 2368 tegra_sor_writel(sor, value, SOR_DP_SPARE0); 2369 2370 value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) | 2371 SOR_SEQ_CTL_PD_PC(8) | SOR_SEQ_CTL_PD_PC_ALT(8); 2372 tegra_sor_writel(sor, value, SOR_SEQ_CTL); 2373 2374 value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT | 2375 SOR_SEQ_INST_WAIT_VSYNC | SOR_SEQ_INST_WAIT(1); 2376 tegra_sor_writel(sor, value, SOR_SEQ_INST(0)); 2377 tegra_sor_writel(sor, value, SOR_SEQ_INST(8)); 2378 2379 if (!sor->soc->has_nvdisplay) { 2380 /* program the reference clock */ 2381 value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div); 2382 tegra_sor_writel(sor, value, SOR_REFCLK); 2383 } 2384 2385 /* XXX not in TRM */ 2386 for (value = 0, i = 0; i < 5; i++) 2387 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) | 2388 SOR_XBAR_CTRL_LINK1_XSEL(i, i); 2389 2390 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); 2391 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); 2392 2393 /* 2394 * Switch the pad clock to the DP clock. Note that we cannot actually 2395 * do this because Tegra186 and later don't support clk_set_parent() 2396 * on the sorX_pad_clkout clocks. We already do the equivalent above 2397 * using the DP_CLK_SEL mux of the SOR_CLK_CNTRL register. 2398 */ 2399 #if 0 2400 err = clk_set_parent(sor->clk_pad, sor->clk_dp); 2401 if (err < 0) { 2402 dev_err(sor->dev, "failed to select pad parent clock: %d\n", 2403 err); 2404 return; 2405 } 2406 #endif 2407 2408 /* switch the SOR clock to the pad clock */ 2409 err = tegra_sor_set_parent_clock(sor, sor->clk_pad); 2410 if (err < 0) { 2411 dev_err(sor->dev, "failed to select SOR parent clock: %d\n", 2412 err); 2413 return; 2414 } 2415 2416 /* switch the output clock to the parent pixel clock */ 2417 err = clk_set_parent(sor->clk, sor->clk_parent); 2418 if (err < 0) { 2419 dev_err(sor->dev, "failed to select output parent clock: %d\n", 2420 err); 2421 return; 2422 } 2423 2424 /* adjust clock rate for HDMI 2.0 modes */ 2425 rate = clk_get_rate(sor->clk_parent); 2426 2427 if (mode->clock >= 340000) 2428 rate /= 2; 2429 2430 DRM_DEBUG_KMS("setting clock to %lu Hz, mode: %lu Hz\n", rate, pclk); 2431 2432 clk_set_rate(sor->clk, rate); 2433 2434 if (!sor->soc->has_nvdisplay) { 2435 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe); 2436 2437 /* XXX is this the proper check? */ 2438 if (mode->clock < 75000) 2439 value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED; 2440 2441 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL); 2442 } 2443 2444 max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32; 2445 2446 value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) | 2447 SOR_HDMI_CTRL_AUDIO_LAYOUT | SOR_HDMI_CTRL_REKEY(SOR_REKEY); 2448 tegra_sor_writel(sor, value, SOR_HDMI_CTRL); 2449 2450 if (!dc->soc->has_nvdisplay) { 2451 /* H_PULSE2 setup */ 2452 pulse_start = h_ref_to_sync + 2453 (mode->hsync_end - mode->hsync_start) + 2454 (mode->htotal - mode->hsync_end) - 10; 2455 2456 value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE | 2457 PULSE_POLARITY_HIGH | PULSE_MODE_NORMAL; 2458 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL); 2459 2460 value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start); 2461 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A); 2462 2463 value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0); 2464 value |= H_PULSE2_ENABLE; 2465 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0); 2466 } 2467 2468 /* infoframe setup */ 2469 err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode); 2470 if (err < 0) 2471 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); 2472 2473 /* XXX HDMI audio support not implemented yet */ 2474 tegra_sor_hdmi_disable_audio_infoframe(sor); 2475 2476 /* use single TMDS protocol */ 2477 value = tegra_sor_readl(sor, SOR_STATE1); 2478 value &= ~SOR_STATE_ASY_PROTOCOL_MASK; 2479 value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A; 2480 tegra_sor_writel(sor, value, SOR_STATE1); 2481 2482 /* power up pad calibration */ 2483 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 2484 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; 2485 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 2486 2487 /* production settings */ 2488 settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000); 2489 if (!settings) { 2490 dev_err(sor->dev, "no settings for pixel clock %d Hz\n", 2491 mode->clock * 1000); 2492 return; 2493 } 2494 2495 value = tegra_sor_readl(sor, sor->soc->regs->pll0); 2496 value &= ~SOR_PLL0_ICHPMP_MASK; 2497 value &= ~SOR_PLL0_FILTER_MASK; 2498 value &= ~SOR_PLL0_VCOCAP_MASK; 2499 value |= SOR_PLL0_ICHPMP(settings->ichpmp); 2500 value |= SOR_PLL0_FILTER(settings->filter); 2501 value |= SOR_PLL0_VCOCAP(settings->vcocap); 2502 tegra_sor_writel(sor, value, sor->soc->regs->pll0); 2503 2504 /* XXX not in TRM */ 2505 value = tegra_sor_readl(sor, sor->soc->regs->pll1); 2506 value &= ~SOR_PLL1_LOADADJ_MASK; 2507 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; 2508 value |= SOR_PLL1_LOADADJ(settings->loadadj); 2509 value |= SOR_PLL1_TMDS_TERMADJ(settings->tmds_termadj); 2510 value |= SOR_PLL1_TMDS_TERM; 2511 tegra_sor_writel(sor, value, sor->soc->regs->pll1); 2512 2513 value = tegra_sor_readl(sor, sor->soc->regs->pll3); 2514 value &= ~SOR_PLL3_BG_TEMP_COEF_MASK; 2515 value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK; 2516 value &= ~SOR_PLL3_AVDD10_LEVEL_MASK; 2517 value &= ~SOR_PLL3_AVDD14_LEVEL_MASK; 2518 value |= SOR_PLL3_BG_TEMP_COEF(settings->bg_temp_coef); 2519 value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref_level); 2520 value |= SOR_PLL3_AVDD10_LEVEL(settings->avdd10_level); 2521 value |= SOR_PLL3_AVDD14_LEVEL(settings->avdd14_level); 2522 tegra_sor_writel(sor, value, sor->soc->regs->pll3); 2523 2524 value = settings->drive_current[3] << 24 | 2525 settings->drive_current[2] << 16 | 2526 settings->drive_current[1] << 8 | 2527 settings->drive_current[0] << 0; 2528 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); 2529 2530 value = settings->preemphasis[3] << 24 | 2531 settings->preemphasis[2] << 16 | 2532 settings->preemphasis[1] << 8 | 2533 settings->preemphasis[0] << 0; 2534 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); 2535 2536 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 2537 value &= ~SOR_DP_PADCTL_TX_PU_MASK; 2538 value |= SOR_DP_PADCTL_TX_PU_ENABLE; 2539 value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value); 2540 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 2541 2542 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2); 2543 value &= ~SOR_DP_PADCTL_SPAREPLL_MASK; 2544 value |= SOR_DP_PADCTL_SPAREPLL(settings->sparepll); 2545 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2); 2546 2547 /* power down pad calibration */ 2548 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 2549 value |= SOR_DP_PADCTL_PAD_CAL_PD; 2550 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 2551 2552 if (!dc->soc->has_nvdisplay) { 2553 /* miscellaneous display controller settings */ 2554 value = VSYNC_H_POSITION(1); 2555 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS); 2556 } 2557 2558 value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL); 2559 value &= ~DITHER_CONTROL_MASK; 2560 value &= ~BASE_COLOR_SIZE_MASK; 2561 if (dc->soc->has_nvdisplay) { 2562 tegra_dc_writel(dc, lower_32_bits(dc->cmu_output_lut_phys), 2563 DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE); 2564 tegra_dc_writel(dc, upper_32_bits(dc->cmu_output_lut_phys), 2565 DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_HI); 2566 2567 tegra_dc_writel(dc, OUTPUT_LUT_MODE_INTERPOLATE | OUTPUT_LUT_SIZE_SIZE_1025, 2568 DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT); 2569 2570 value |= CMU_ENABLE_ENABLE; 2571 } 2572 2573 switch (state->bpc) { 2574 case 6: 2575 value |= BASE_COLOR_SIZE_666; 2576 break; 2577 2578 case 8: 2579 value |= BASE_COLOR_SIZE_888; 2580 break; 2581 2582 case 10: 2583 value |= BASE_COLOR_SIZE_101010; 2584 break; 2585 2586 case 12: 2587 value |= BASE_COLOR_SIZE_121212; 2588 break; 2589 2590 default: 2591 WARN(1, "%u bits-per-color not supported\n", state->bpc); 2592 value |= BASE_COLOR_SIZE_888; 2593 break; 2594 } 2595 2596 tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL); 2597 2598 /* XXX set display head owner */ 2599 value = tegra_sor_readl(sor, SOR_STATE1); 2600 value &= ~SOR_STATE_ASY_OWNER_MASK; 2601 value |= SOR_STATE_ASY_OWNER(1 + dc->pipe); 2602 tegra_sor_writel(sor, value, SOR_STATE1); 2603 2604 err = tegra_sor_power_up(sor, 250); 2605 if (err < 0) 2606 dev_err(sor->dev, "failed to power up SOR: %d\n", err); 2607 2608 /* configure dynamic range of output */ 2609 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); 2610 value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK; 2611 value &= ~SOR_HEAD_STATE_DYNRANGE_MASK; 2612 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); 2613 2614 /* configure colorspace */ 2615 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); 2616 value &= ~SOR_HEAD_STATE_COLORSPACE_MASK; 2617 value |= SOR_HEAD_STATE_COLORSPACE_RGB; 2618 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); 2619 2620 tegra_sor_mode_set(sor, mode, state); 2621 2622 tegra_sor_update(sor); 2623 2624 /* program preamble timing in SOR (XXX) */ 2625 value = tegra_sor_readl(sor, SOR_DP_SPARE0); 2626 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE; 2627 tegra_sor_writel(sor, value, SOR_DP_SPARE0); 2628 2629 err = tegra_sor_attach(sor); 2630 if (err < 0) 2631 dev_err(sor->dev, "failed to attach SOR: %d\n", err); 2632 2633 /* enable display to SOR clock and generate HDMI preamble */ 2634 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 2635 2636 if (!sor->soc->has_nvdisplay) 2637 value |= SOR1_TIMING_CYA; 2638 2639 value |= SOR_ENABLE(sor->index); 2640 2641 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 2642 2643 if (dc->soc->has_nvdisplay) { 2644 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); 2645 value &= ~PROTOCOL_MASK; 2646 value |= PROTOCOL_SINGLE_TMDS_A; 2647 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); 2648 } 2649 2650 tegra_dc_commit(dc); 2651 2652 err = tegra_sor_wakeup(sor); 2653 if (err < 0) 2654 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err); 2655 2656 tegra_sor_hdmi_scdc_start(sor); 2657 tegra_sor_audio_prepare(sor); 2658 } 2659 2660 static const struct drm_encoder_helper_funcs tegra_sor_hdmi_helpers = { 2661 .disable = tegra_sor_hdmi_disable, 2662 .enable = tegra_sor_hdmi_enable, 2663 .atomic_check = tegra_sor_encoder_atomic_check, 2664 }; 2665 2666 static void tegra_sor_dp_disable(struct drm_encoder *encoder) 2667 { 2668 struct tegra_output *output = encoder_to_output(encoder); 2669 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 2670 struct tegra_sor *sor = to_sor(output); 2671 u32 value; 2672 int err; 2673 2674 if (output->panel) 2675 drm_panel_disable(output->panel); 2676 2677 /* 2678 * Do not attempt to power down a DP link if we're not connected since 2679 * the AUX transactions would just be timing out. 2680 */ 2681 if (output->connector.status != connector_status_disconnected) { 2682 err = drm_dp_link_power_down(sor->aux, sor->link.revision); 2683 if (err < 0) 2684 dev_err(sor->dev, "failed to power down link: %d\n", 2685 err); 2686 } 2687 2688 err = tegra_sor_detach(sor); 2689 if (err < 0) 2690 dev_err(sor->dev, "failed to detach SOR: %d\n", err); 2691 2692 tegra_sor_writel(sor, 0, SOR_STATE1); 2693 tegra_sor_update(sor); 2694 2695 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 2696 value &= ~SOR_ENABLE(sor->index); 2697 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 2698 tegra_dc_commit(dc); 2699 2700 value = tegra_sor_readl(sor, SOR_STATE1); 2701 value &= ~SOR_STATE_ASY_PROTOCOL_MASK; 2702 value &= ~SOR_STATE_ASY_SUBOWNER_MASK; 2703 value &= ~SOR_STATE_ASY_OWNER_MASK; 2704 tegra_sor_writel(sor, value, SOR_STATE1); 2705 tegra_sor_update(sor); 2706 2707 /* switch to safe parent clock */ 2708 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); 2709 if (err < 0) 2710 dev_err(sor->dev, "failed to set safe clock: %d\n", err); 2711 2712 err = tegra_sor_power_down(sor); 2713 if (err < 0) 2714 dev_err(sor->dev, "failed to power down SOR: %d\n", err); 2715 2716 err = tegra_io_pad_power_disable(sor->pad); 2717 if (err < 0) 2718 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err); 2719 2720 err = drm_dp_aux_disable(sor->aux); 2721 if (err < 0) 2722 dev_err(sor->dev, "failed disable DPAUX: %d\n", err); 2723 2724 if (output->panel) 2725 drm_panel_unprepare(output->panel); 2726 2727 host1x_client_suspend(&sor->client); 2728 } 2729 2730 static void tegra_sor_dp_enable(struct drm_encoder *encoder) 2731 { 2732 struct tegra_output *output = encoder_to_output(encoder); 2733 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 2734 struct tegra_sor *sor = to_sor(output); 2735 struct tegra_sor_config config; 2736 struct tegra_sor_state *state; 2737 struct drm_display_mode *mode; 2738 struct drm_display_info *info; 2739 unsigned int i; 2740 u32 value; 2741 int err; 2742 2743 state = to_sor_state(output->connector.state); 2744 mode = &encoder->crtc->state->adjusted_mode; 2745 info = &output->connector.display_info; 2746 2747 err = host1x_client_resume(&sor->client); 2748 if (err < 0) { 2749 dev_err(sor->dev, "failed to resume: %d\n", err); 2750 return; 2751 } 2752 2753 /* switch to safe parent clock */ 2754 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); 2755 if (err < 0) 2756 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); 2757 2758 err = tegra_io_pad_power_enable(sor->pad); 2759 if (err < 0) 2760 dev_err(sor->dev, "failed to power on LVDS rail: %d\n", err); 2761 2762 usleep_range(20, 100); 2763 2764 err = drm_dp_aux_enable(sor->aux); 2765 if (err < 0) 2766 dev_err(sor->dev, "failed to enable DPAUX: %d\n", err); 2767 2768 err = drm_dp_link_probe(sor->aux, &sor->link); 2769 if (err < 0) 2770 dev_err(sor->dev, "failed to probe DP link: %d\n", err); 2771 2772 tegra_sor_filter_rates(sor); 2773 2774 err = drm_dp_link_choose(&sor->link, mode, info); 2775 if (err < 0) 2776 dev_err(sor->dev, "failed to choose link: %d\n", err); 2777 2778 if (output->panel) 2779 drm_panel_prepare(output->panel); 2780 2781 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 2782 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; 2783 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 2784 2785 usleep_range(20, 40); 2786 2787 value = tegra_sor_readl(sor, sor->soc->regs->pll3); 2788 value |= SOR_PLL3_PLL_VDD_MODE_3V3; 2789 tegra_sor_writel(sor, value, sor->soc->regs->pll3); 2790 2791 value = tegra_sor_readl(sor, sor->soc->regs->pll0); 2792 value &= ~(SOR_PLL0_VCOPD | SOR_PLL0_PWR); 2793 tegra_sor_writel(sor, value, sor->soc->regs->pll0); 2794 2795 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 2796 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; 2797 value |= SOR_PLL2_SEQ_PLLCAPPD; 2798 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 2799 2800 usleep_range(200, 400); 2801 2802 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 2803 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; 2804 value &= ~SOR_PLL2_PORT_POWERDOWN; 2805 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 2806 2807 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 2808 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; 2809 2810 if (output->panel) 2811 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; 2812 else 2813 value |= SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK; 2814 2815 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 2816 2817 usleep_range(200, 400); 2818 2819 value = tegra_sor_readl(sor, SOR_DP_SPARE0); 2820 /* XXX not in TRM */ 2821 if (output->panel) 2822 value |= SOR_DP_SPARE_PANEL_INTERNAL; 2823 else 2824 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; 2825 2826 value |= SOR_DP_SPARE_SEQ_ENABLE; 2827 tegra_sor_writel(sor, value, SOR_DP_SPARE0); 2828 2829 /* XXX not in TRM */ 2830 tegra_sor_writel(sor, 0, SOR_LVDS); 2831 2832 value = tegra_sor_readl(sor, sor->soc->regs->pll0); 2833 value &= ~SOR_PLL0_ICHPMP_MASK; 2834 value &= ~SOR_PLL0_VCOCAP_MASK; 2835 value |= SOR_PLL0_ICHPMP(0x1); 2836 value |= SOR_PLL0_VCOCAP(0x3); 2837 value |= SOR_PLL0_RESISTOR_EXT; 2838 tegra_sor_writel(sor, value, sor->soc->regs->pll0); 2839 2840 /* XXX not in TRM */ 2841 for (value = 0, i = 0; i < 5; i++) 2842 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) | 2843 SOR_XBAR_CTRL_LINK1_XSEL(i, i); 2844 2845 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); 2846 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); 2847 2848 /* 2849 * Switch the pad clock to the DP clock. Note that we cannot actually 2850 * do this because Tegra186 and later don't support clk_set_parent() 2851 * on the sorX_pad_clkout clocks. We already do the equivalent above 2852 * using the DP_CLK_SEL mux of the SOR_CLK_CNTRL register. 2853 */ 2854 #if 0 2855 err = clk_set_parent(sor->clk_pad, sor->clk_parent); 2856 if (err < 0) { 2857 dev_err(sor->dev, "failed to select pad parent clock: %d\n", 2858 err); 2859 return; 2860 } 2861 #endif 2862 2863 /* switch the SOR clock to the pad clock */ 2864 err = tegra_sor_set_parent_clock(sor, sor->clk_pad); 2865 if (err < 0) { 2866 dev_err(sor->dev, "failed to select SOR parent clock: %d\n", 2867 err); 2868 return; 2869 } 2870 2871 /* switch the output clock to the parent pixel clock */ 2872 err = clk_set_parent(sor->clk, sor->clk_parent); 2873 if (err < 0) { 2874 dev_err(sor->dev, "failed to select output parent clock: %d\n", 2875 err); 2876 return; 2877 } 2878 2879 /* use DP-A protocol */ 2880 value = tegra_sor_readl(sor, SOR_STATE1); 2881 value &= ~SOR_STATE_ASY_PROTOCOL_MASK; 2882 value |= SOR_STATE_ASY_PROTOCOL_DP_A; 2883 tegra_sor_writel(sor, value, SOR_STATE1); 2884 2885 /* enable port */ 2886 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); 2887 value |= SOR_DP_LINKCTL_ENABLE; 2888 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); 2889 2890 tegra_sor_dp_term_calibrate(sor); 2891 2892 err = drm_dp_link_train(&sor->link); 2893 if (err < 0) 2894 dev_err(sor->dev, "link training failed: %d\n", err); 2895 else 2896 dev_dbg(sor->dev, "link training succeeded\n"); 2897 2898 err = drm_dp_link_power_up(sor->aux, sor->link.revision); 2899 if (err < 0) 2900 dev_err(sor->dev, "failed to power up DP link: %d\n", err); 2901 2902 /* compute configuration */ 2903 memset(&config, 0, sizeof(config)); 2904 config.bits_per_pixel = state->bpc * 3; 2905 2906 err = tegra_sor_compute_config(sor, mode, &config, &sor->link); 2907 if (err < 0) 2908 dev_err(sor->dev, "failed to compute configuration: %d\n", err); 2909 2910 tegra_sor_apply_config(sor, &config); 2911 tegra_sor_mode_set(sor, mode, state); 2912 2913 if (output->panel) { 2914 /* CSTM (LVDS, link A/B, upper) */ 2915 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B | 2916 SOR_CSTM_UPPER; 2917 tegra_sor_writel(sor, value, SOR_CSTM); 2918 2919 /* PWM setup */ 2920 err = tegra_sor_setup_pwm(sor, 250); 2921 if (err < 0) 2922 dev_err(sor->dev, "failed to setup PWM: %d\n", err); 2923 } 2924 2925 tegra_sor_update(sor); 2926 2927 err = tegra_sor_power_up(sor, 250); 2928 if (err < 0) 2929 dev_err(sor->dev, "failed to power up SOR: %d\n", err); 2930 2931 /* attach and wake up */ 2932 err = tegra_sor_attach(sor); 2933 if (err < 0) 2934 dev_err(sor->dev, "failed to attach SOR: %d\n", err); 2935 2936 if (dc->soc->has_nvdisplay) { 2937 value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL); 2938 tegra_dc_writel(dc, lower_32_bits(dc->cmu_output_lut_phys), 2939 DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE); 2940 tegra_dc_writel(dc, upper_32_bits(dc->cmu_output_lut_phys), 2941 DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_HI); 2942 2943 tegra_dc_writel(dc, OUTPUT_LUT_MODE_INTERPOLATE | OUTPUT_LUT_SIZE_SIZE_1025, 2944 DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT); 2945 2946 value |= CMU_ENABLE_ENABLE; 2947 tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL); 2948 } 2949 2950 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 2951 value |= SOR_ENABLE(sor->index); 2952 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 2953 2954 tegra_dc_commit(dc); 2955 2956 err = tegra_sor_wakeup(sor); 2957 if (err < 0) 2958 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err); 2959 2960 if (output->panel) 2961 drm_panel_enable(output->panel); 2962 } 2963 2964 static const struct drm_encoder_helper_funcs tegra_sor_dp_helpers = { 2965 .disable = tegra_sor_dp_disable, 2966 .enable = tegra_sor_dp_enable, 2967 .atomic_check = tegra_sor_encoder_atomic_check, 2968 }; 2969 2970 static void tegra_sor_disable_regulator(void *data) 2971 { 2972 struct regulator *reg = data; 2973 2974 regulator_disable(reg); 2975 } 2976 2977 static int tegra_sor_enable_regulator(struct tegra_sor *sor, struct regulator *reg) 2978 { 2979 int err; 2980 2981 err = regulator_enable(reg); 2982 if (err) 2983 return err; 2984 2985 return devm_add_action_or_reset(sor->dev, tegra_sor_disable_regulator, reg); 2986 } 2987 2988 static int tegra_sor_hdmi_probe(struct tegra_sor *sor) 2989 { 2990 int err; 2991 2992 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp"); 2993 if (IS_ERR(sor->avdd_io_supply)) 2994 return dev_err_probe(sor->dev, PTR_ERR(sor->avdd_io_supply), 2995 "cannot get AVDD I/O supply\n"); 2996 2997 err = tegra_sor_enable_regulator(sor, sor->avdd_io_supply); 2998 if (err < 0) { 2999 dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n", 3000 err); 3001 return err; 3002 } 3003 3004 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll"); 3005 if (IS_ERR(sor->vdd_pll_supply)) 3006 return dev_err_probe(sor->dev, PTR_ERR(sor->vdd_pll_supply), 3007 "cannot get VDD PLL supply\n"); 3008 3009 err = tegra_sor_enable_regulator(sor, sor->vdd_pll_supply); 3010 if (err < 0) { 3011 dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n", 3012 err); 3013 return err; 3014 } 3015 3016 sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi"); 3017 if (IS_ERR(sor->hdmi_supply)) 3018 return dev_err_probe(sor->dev, PTR_ERR(sor->hdmi_supply), 3019 "cannot get HDMI supply\n"); 3020 3021 err = tegra_sor_enable_regulator(sor, sor->hdmi_supply); 3022 if (err < 0) { 3023 dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err); 3024 return err; 3025 } 3026 3027 INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work); 3028 3029 return 0; 3030 } 3031 3032 static const struct tegra_sor_ops tegra_sor_hdmi_ops = { 3033 .name = "HDMI", 3034 .probe = tegra_sor_hdmi_probe, 3035 .audio_enable = tegra_sor_hdmi_audio_enable, 3036 .audio_disable = tegra_sor_hdmi_audio_disable, 3037 }; 3038 3039 static int tegra_sor_dp_probe(struct tegra_sor *sor) 3040 { 3041 int err; 3042 3043 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp"); 3044 if (IS_ERR(sor->avdd_io_supply)) 3045 return PTR_ERR(sor->avdd_io_supply); 3046 3047 err = tegra_sor_enable_regulator(sor, sor->avdd_io_supply); 3048 if (err < 0) 3049 return err; 3050 3051 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll"); 3052 if (IS_ERR(sor->vdd_pll_supply)) 3053 return PTR_ERR(sor->vdd_pll_supply); 3054 3055 err = tegra_sor_enable_regulator(sor, sor->vdd_pll_supply); 3056 if (err < 0) 3057 return err; 3058 3059 return 0; 3060 } 3061 3062 static const struct tegra_sor_ops tegra_sor_dp_ops = { 3063 .name = "DP", 3064 .probe = tegra_sor_dp_probe, 3065 }; 3066 3067 static const struct drm_encoder_funcs tegra_sor_encoder_funcs_cleanup = { 3068 .destroy = drm_encoder_cleanup, 3069 }; 3070 3071 static int tegra_sor_init(struct host1x_client *client) 3072 { 3073 struct drm_device *drm = dev_get_drvdata(client->host); 3074 const struct drm_encoder_helper_funcs *helpers = NULL; 3075 struct tegra_sor *sor = host1x_client_to_sor(client); 3076 int connector = DRM_MODE_CONNECTOR_Unknown; 3077 int encoder = DRM_MODE_ENCODER_NONE; 3078 int err; 3079 3080 if (!sor->aux) { 3081 if (sor->ops == &tegra_sor_hdmi_ops) { 3082 connector = DRM_MODE_CONNECTOR_HDMIA; 3083 encoder = DRM_MODE_ENCODER_TMDS; 3084 helpers = &tegra_sor_hdmi_helpers; 3085 } else if (sor->soc->supports_lvds) { 3086 connector = DRM_MODE_CONNECTOR_LVDS; 3087 encoder = DRM_MODE_ENCODER_LVDS; 3088 } 3089 } else { 3090 if (sor->output.panel) { 3091 connector = DRM_MODE_CONNECTOR_eDP; 3092 encoder = DRM_MODE_ENCODER_TMDS; 3093 helpers = &tegra_sor_dp_helpers; 3094 } else { 3095 connector = DRM_MODE_CONNECTOR_DisplayPort; 3096 encoder = DRM_MODE_ENCODER_TMDS; 3097 helpers = &tegra_sor_dp_helpers; 3098 } 3099 3100 sor->link.ops = &tegra_sor_dp_link_ops; 3101 sor->link.aux = sor->aux; 3102 } 3103 3104 sor->output.dev = sor->dev; 3105 3106 drm_connector_init_with_ddc(drm, &sor->output.connector, 3107 &tegra_sor_connector_funcs, 3108 connector, 3109 sor->output.ddc); 3110 drm_connector_helper_add(&sor->output.connector, 3111 &tegra_sor_connector_helper_funcs); 3112 sor->output.connector.dpms = DRM_MODE_DPMS_OFF; 3113 3114 drm_encoder_init(drm, &sor->output.encoder, 3115 &tegra_sor_encoder_funcs_cleanup, encoder, NULL); 3116 drm_encoder_helper_add(&sor->output.encoder, helpers); 3117 3118 drm_connector_attach_encoder(&sor->output.connector, 3119 &sor->output.encoder); 3120 drm_connector_register(&sor->output.connector); 3121 3122 err = tegra_output_init(drm, &sor->output); 3123 if (err < 0) { 3124 dev_err(client->dev, "failed to initialize output: %d\n", err); 3125 return err; 3126 } 3127 3128 tegra_output_find_possible_crtcs(&sor->output, drm); 3129 3130 if (sor->aux) { 3131 err = drm_dp_aux_attach(sor->aux, &sor->output); 3132 if (err < 0) { 3133 dev_err(sor->dev, "failed to attach DP: %d\n", err); 3134 return err; 3135 } 3136 } 3137 3138 /* 3139 * XXX: Remove this reset once proper hand-over from firmware to 3140 * kernel is possible. 3141 */ 3142 if (sor->rst) { 3143 err = pm_runtime_resume_and_get(sor->dev); 3144 if (err < 0) { 3145 dev_err(sor->dev, "failed to get runtime PM: %d\n", err); 3146 return err; 3147 } 3148 3149 err = reset_control_acquire(sor->rst); 3150 if (err < 0) { 3151 dev_err(sor->dev, "failed to acquire SOR reset: %d\n", 3152 err); 3153 goto rpm_put; 3154 } 3155 3156 err = reset_control_assert(sor->rst); 3157 if (err < 0) { 3158 dev_err(sor->dev, "failed to assert SOR reset: %d\n", 3159 err); 3160 goto rpm_put; 3161 } 3162 } 3163 3164 err = clk_prepare_enable(sor->clk); 3165 if (err < 0) { 3166 dev_err(sor->dev, "failed to enable clock: %d\n", err); 3167 goto rpm_put; 3168 } 3169 3170 usleep_range(1000, 3000); 3171 3172 if (sor->rst) { 3173 err = reset_control_deassert(sor->rst); 3174 if (err < 0) { 3175 dev_err(sor->dev, "failed to deassert SOR reset: %d\n", 3176 err); 3177 clk_disable_unprepare(sor->clk); 3178 goto rpm_put; 3179 } 3180 3181 reset_control_release(sor->rst); 3182 pm_runtime_put(sor->dev); 3183 } 3184 3185 err = clk_prepare_enable(sor->clk_safe); 3186 if (err < 0) { 3187 clk_disable_unprepare(sor->clk); 3188 return err; 3189 } 3190 3191 err = clk_prepare_enable(sor->clk_dp); 3192 if (err < 0) { 3193 clk_disable_unprepare(sor->clk_safe); 3194 clk_disable_unprepare(sor->clk); 3195 return err; 3196 } 3197 3198 return 0; 3199 3200 rpm_put: 3201 if (sor->rst) 3202 pm_runtime_put(sor->dev); 3203 3204 return err; 3205 } 3206 3207 static int tegra_sor_exit(struct host1x_client *client) 3208 { 3209 struct tegra_sor *sor = host1x_client_to_sor(client); 3210 int err; 3211 3212 tegra_output_exit(&sor->output); 3213 3214 if (sor->aux) { 3215 err = drm_dp_aux_detach(sor->aux); 3216 if (err < 0) { 3217 dev_err(sor->dev, "failed to detach DP: %d\n", err); 3218 return err; 3219 } 3220 } 3221 3222 clk_disable_unprepare(sor->clk_safe); 3223 clk_disable_unprepare(sor->clk_dp); 3224 clk_disable_unprepare(sor->clk); 3225 3226 return 0; 3227 } 3228 3229 static int tegra_sor_runtime_suspend(struct host1x_client *client) 3230 { 3231 struct tegra_sor *sor = host1x_client_to_sor(client); 3232 struct device *dev = client->dev; 3233 int err; 3234 3235 if (sor->rst) { 3236 err = reset_control_assert(sor->rst); 3237 if (err < 0) { 3238 dev_err(dev, "failed to assert reset: %d\n", err); 3239 return err; 3240 } 3241 3242 reset_control_release(sor->rst); 3243 } 3244 3245 usleep_range(1000, 2000); 3246 3247 clk_disable_unprepare(sor->clk); 3248 pm_runtime_put_sync(dev); 3249 3250 return 0; 3251 } 3252 3253 static int tegra_sor_runtime_resume(struct host1x_client *client) 3254 { 3255 struct tegra_sor *sor = host1x_client_to_sor(client); 3256 struct device *dev = client->dev; 3257 int err; 3258 3259 err = pm_runtime_resume_and_get(dev); 3260 if (err < 0) { 3261 dev_err(dev, "failed to get runtime PM: %d\n", err); 3262 return err; 3263 } 3264 3265 err = clk_prepare_enable(sor->clk); 3266 if (err < 0) { 3267 dev_err(dev, "failed to enable clock: %d\n", err); 3268 goto put_rpm; 3269 } 3270 3271 usleep_range(1000, 2000); 3272 3273 if (sor->rst) { 3274 err = reset_control_acquire(sor->rst); 3275 if (err < 0) { 3276 dev_err(dev, "failed to acquire reset: %d\n", err); 3277 goto disable_clk; 3278 } 3279 3280 err = reset_control_deassert(sor->rst); 3281 if (err < 0) { 3282 dev_err(dev, "failed to deassert reset: %d\n", err); 3283 goto release_reset; 3284 } 3285 } 3286 3287 return 0; 3288 3289 release_reset: 3290 reset_control_release(sor->rst); 3291 disable_clk: 3292 clk_disable_unprepare(sor->clk); 3293 put_rpm: 3294 pm_runtime_put_sync(dev); 3295 return err; 3296 } 3297 3298 static const struct host1x_client_ops sor_client_ops = { 3299 .init = tegra_sor_init, 3300 .exit = tegra_sor_exit, 3301 .suspend = tegra_sor_runtime_suspend, 3302 .resume = tegra_sor_runtime_resume, 3303 }; 3304 3305 static const u8 tegra124_sor_xbar_cfg[5] = { 3306 0, 1, 2, 3, 4 3307 }; 3308 3309 static const struct tegra_sor_regs tegra124_sor_regs = { 3310 .head_state0 = 0x05, 3311 .head_state1 = 0x07, 3312 .head_state2 = 0x09, 3313 .head_state3 = 0x0b, 3314 .head_state4 = 0x0d, 3315 .head_state5 = 0x0f, 3316 .pll0 = 0x17, 3317 .pll1 = 0x18, 3318 .pll2 = 0x19, 3319 .pll3 = 0x1a, 3320 .dp_padctl0 = 0x5c, 3321 .dp_padctl2 = 0x73, 3322 }; 3323 3324 /* Tegra124 and Tegra132 have lanes 0 and 2 swapped. */ 3325 static const u8 tegra124_sor_lane_map[4] = { 3326 2, 1, 0, 3, 3327 }; 3328 3329 static const u8 tegra124_sor_voltage_swing[4][4][4] = { 3330 { 3331 { 0x13, 0x19, 0x1e, 0x28 }, 3332 { 0x1e, 0x25, 0x2d, }, 3333 { 0x28, 0x32, }, 3334 { 0x3c, }, 3335 }, { 3336 { 0x12, 0x17, 0x1b, 0x25 }, 3337 { 0x1c, 0x23, 0x2a, }, 3338 { 0x25, 0x2f, }, 3339 { 0x39, } 3340 }, { 3341 { 0x12, 0x16, 0x1a, 0x22 }, 3342 { 0x1b, 0x20, 0x27, }, 3343 { 0x24, 0x2d, }, 3344 { 0x36, }, 3345 }, { 3346 { 0x11, 0x14, 0x17, 0x1f }, 3347 { 0x19, 0x1e, 0x24, }, 3348 { 0x22, 0x2a, }, 3349 { 0x32, }, 3350 }, 3351 }; 3352 3353 static const u8 tegra124_sor_pre_emphasis[4][4][4] = { 3354 { 3355 { 0x00, 0x09, 0x13, 0x25 }, 3356 { 0x00, 0x0f, 0x1e, }, 3357 { 0x00, 0x14, }, 3358 { 0x00, }, 3359 }, { 3360 { 0x00, 0x0a, 0x14, 0x28 }, 3361 { 0x00, 0x0f, 0x1e, }, 3362 { 0x00, 0x14, }, 3363 { 0x00 }, 3364 }, { 3365 { 0x00, 0x0a, 0x14, 0x28 }, 3366 { 0x00, 0x0f, 0x1e, }, 3367 { 0x00, 0x14, }, 3368 { 0x00, }, 3369 }, { 3370 { 0x00, 0x0a, 0x14, 0x28 }, 3371 { 0x00, 0x0f, 0x1e, }, 3372 { 0x00, 0x14, }, 3373 { 0x00, }, 3374 }, 3375 }; 3376 3377 static const u8 tegra124_sor_post_cursor[4][4][4] = { 3378 { 3379 { 0x00, 0x00, 0x00, 0x00 }, 3380 { 0x00, 0x00, 0x00, }, 3381 { 0x00, 0x00, }, 3382 { 0x00, }, 3383 }, { 3384 { 0x02, 0x02, 0x04, 0x05 }, 3385 { 0x02, 0x04, 0x05, }, 3386 { 0x04, 0x05, }, 3387 { 0x05, }, 3388 }, { 3389 { 0x04, 0x05, 0x08, 0x0b }, 3390 { 0x05, 0x09, 0x0b, }, 3391 { 0x08, 0x0a, }, 3392 { 0x0b, }, 3393 }, { 3394 { 0x05, 0x09, 0x0b, 0x12 }, 3395 { 0x09, 0x0d, 0x12, }, 3396 { 0x0b, 0x0f, }, 3397 { 0x12, }, 3398 }, 3399 }; 3400 3401 static const u8 tegra124_sor_tx_pu[4][4][4] = { 3402 { 3403 { 0x20, 0x30, 0x40, 0x60 }, 3404 { 0x30, 0x40, 0x60, }, 3405 { 0x40, 0x60, }, 3406 { 0x60, }, 3407 }, { 3408 { 0x20, 0x20, 0x30, 0x50 }, 3409 { 0x30, 0x40, 0x50, }, 3410 { 0x40, 0x50, }, 3411 { 0x60, }, 3412 }, { 3413 { 0x20, 0x20, 0x30, 0x40, }, 3414 { 0x30, 0x30, 0x40, }, 3415 { 0x40, 0x50, }, 3416 { 0x60, }, 3417 }, { 3418 { 0x20, 0x20, 0x20, 0x40, }, 3419 { 0x30, 0x30, 0x40, }, 3420 { 0x40, 0x40, }, 3421 { 0x60, }, 3422 }, 3423 }; 3424 3425 static const struct tegra_sor_soc tegra124_sor = { 3426 .supports_lvds = true, 3427 .supports_hdmi = false, 3428 .supports_dp = true, 3429 .supports_audio = false, 3430 .supports_hdcp = false, 3431 .regs = &tegra124_sor_regs, 3432 .has_nvdisplay = false, 3433 .xbar_cfg = tegra124_sor_xbar_cfg, 3434 .lane_map = tegra124_sor_lane_map, 3435 .voltage_swing = tegra124_sor_voltage_swing, 3436 .pre_emphasis = tegra124_sor_pre_emphasis, 3437 .post_cursor = tegra124_sor_post_cursor, 3438 .tx_pu = tegra124_sor_tx_pu, 3439 }; 3440 3441 static const u8 tegra132_sor_pre_emphasis[4][4][4] = { 3442 { 3443 { 0x00, 0x08, 0x12, 0x24 }, 3444 { 0x01, 0x0e, 0x1d, }, 3445 { 0x01, 0x13, }, 3446 { 0x00, }, 3447 }, { 3448 { 0x00, 0x08, 0x12, 0x24 }, 3449 { 0x00, 0x0e, 0x1d, }, 3450 { 0x00, 0x13, }, 3451 { 0x00 }, 3452 }, { 3453 { 0x00, 0x08, 0x12, 0x24 }, 3454 { 0x00, 0x0e, 0x1d, }, 3455 { 0x00, 0x13, }, 3456 { 0x00, }, 3457 }, { 3458 { 0x00, 0x08, 0x12, 0x24 }, 3459 { 0x00, 0x0e, 0x1d, }, 3460 { 0x00, 0x13, }, 3461 { 0x00, }, 3462 }, 3463 }; 3464 3465 static const struct tegra_sor_soc tegra132_sor = { 3466 .supports_lvds = true, 3467 .supports_hdmi = false, 3468 .supports_dp = true, 3469 .supports_audio = false, 3470 .supports_hdcp = false, 3471 .regs = &tegra124_sor_regs, 3472 .has_nvdisplay = false, 3473 .xbar_cfg = tegra124_sor_xbar_cfg, 3474 .lane_map = tegra124_sor_lane_map, 3475 .voltage_swing = tegra124_sor_voltage_swing, 3476 .pre_emphasis = tegra132_sor_pre_emphasis, 3477 .post_cursor = tegra124_sor_post_cursor, 3478 .tx_pu = tegra124_sor_tx_pu, 3479 }; 3480 3481 static const struct tegra_sor_regs tegra210_sor_regs = { 3482 .head_state0 = 0x05, 3483 .head_state1 = 0x07, 3484 .head_state2 = 0x09, 3485 .head_state3 = 0x0b, 3486 .head_state4 = 0x0d, 3487 .head_state5 = 0x0f, 3488 .pll0 = 0x17, 3489 .pll1 = 0x18, 3490 .pll2 = 0x19, 3491 .pll3 = 0x1a, 3492 .dp_padctl0 = 0x5c, 3493 .dp_padctl2 = 0x73, 3494 }; 3495 3496 static const u8 tegra210_sor_xbar_cfg[5] = { 3497 2, 1, 0, 3, 4 3498 }; 3499 3500 static const u8 tegra210_sor_lane_map[4] = { 3501 0, 1, 2, 3, 3502 }; 3503 3504 static const struct tegra_sor_soc tegra210_sor = { 3505 .supports_lvds = false, 3506 .supports_hdmi = false, 3507 .supports_dp = true, 3508 .supports_audio = false, 3509 .supports_hdcp = false, 3510 3511 .regs = &tegra210_sor_regs, 3512 .has_nvdisplay = false, 3513 3514 .xbar_cfg = tegra210_sor_xbar_cfg, 3515 .lane_map = tegra210_sor_lane_map, 3516 .voltage_swing = tegra124_sor_voltage_swing, 3517 .pre_emphasis = tegra124_sor_pre_emphasis, 3518 .post_cursor = tegra124_sor_post_cursor, 3519 .tx_pu = tegra124_sor_tx_pu, 3520 }; 3521 3522 static const struct tegra_sor_soc tegra210_sor1 = { 3523 .supports_lvds = false, 3524 .supports_hdmi = true, 3525 .supports_dp = true, 3526 .supports_audio = true, 3527 .supports_hdcp = true, 3528 3529 .regs = &tegra210_sor_regs, 3530 .has_nvdisplay = false, 3531 3532 .num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults), 3533 .settings = tegra210_sor_hdmi_defaults, 3534 .xbar_cfg = tegra210_sor_xbar_cfg, 3535 .lane_map = tegra210_sor_lane_map, 3536 .voltage_swing = tegra124_sor_voltage_swing, 3537 .pre_emphasis = tegra124_sor_pre_emphasis, 3538 .post_cursor = tegra124_sor_post_cursor, 3539 .tx_pu = tegra124_sor_tx_pu, 3540 }; 3541 3542 static const struct tegra_sor_regs tegra186_sor_regs = { 3543 .head_state0 = 0x151, 3544 .head_state1 = 0x154, 3545 .head_state2 = 0x157, 3546 .head_state3 = 0x15a, 3547 .head_state4 = 0x15d, 3548 .head_state5 = 0x160, 3549 .pll0 = 0x163, 3550 .pll1 = 0x164, 3551 .pll2 = 0x165, 3552 .pll3 = 0x166, 3553 .dp_padctl0 = 0x168, 3554 .dp_padctl2 = 0x16a, 3555 }; 3556 3557 static const u8 tegra186_sor_voltage_swing[4][4][4] = { 3558 { 3559 { 0x13, 0x19, 0x1e, 0x28 }, 3560 { 0x1e, 0x25, 0x2d, }, 3561 { 0x28, 0x32, }, 3562 { 0x39, }, 3563 }, { 3564 { 0x12, 0x16, 0x1b, 0x25 }, 3565 { 0x1c, 0x23, 0x2a, }, 3566 { 0x25, 0x2f, }, 3567 { 0x37, } 3568 }, { 3569 { 0x12, 0x16, 0x1a, 0x22 }, 3570 { 0x1b, 0x20, 0x27, }, 3571 { 0x24, 0x2d, }, 3572 { 0x35, }, 3573 }, { 3574 { 0x11, 0x14, 0x17, 0x1f }, 3575 { 0x19, 0x1e, 0x24, }, 3576 { 0x22, 0x2a, }, 3577 { 0x32, }, 3578 }, 3579 }; 3580 3581 static const u8 tegra186_sor_pre_emphasis[4][4][4] = { 3582 { 3583 { 0x00, 0x08, 0x12, 0x24 }, 3584 { 0x01, 0x0e, 0x1d, }, 3585 { 0x01, 0x13, }, 3586 { 0x00, }, 3587 }, { 3588 { 0x00, 0x08, 0x12, 0x24 }, 3589 { 0x00, 0x0e, 0x1d, }, 3590 { 0x00, 0x13, }, 3591 { 0x00 }, 3592 }, { 3593 { 0x00, 0x08, 0x14, 0x24 }, 3594 { 0x00, 0x0e, 0x1d, }, 3595 { 0x00, 0x13, }, 3596 { 0x00, }, 3597 }, { 3598 { 0x00, 0x08, 0x12, 0x24 }, 3599 { 0x00, 0x0e, 0x1d, }, 3600 { 0x00, 0x13, }, 3601 { 0x00, }, 3602 }, 3603 }; 3604 3605 static const struct tegra_sor_soc tegra186_sor = { 3606 .supports_lvds = false, 3607 .supports_hdmi = true, 3608 .supports_dp = true, 3609 .supports_audio = true, 3610 .supports_hdcp = true, 3611 3612 .regs = &tegra186_sor_regs, 3613 .has_nvdisplay = true, 3614 3615 .num_settings = ARRAY_SIZE(tegra186_sor_hdmi_defaults), 3616 .settings = tegra186_sor_hdmi_defaults, 3617 .xbar_cfg = tegra124_sor_xbar_cfg, 3618 .lane_map = tegra124_sor_lane_map, 3619 .voltage_swing = tegra186_sor_voltage_swing, 3620 .pre_emphasis = tegra186_sor_pre_emphasis, 3621 .post_cursor = tegra124_sor_post_cursor, 3622 .tx_pu = tegra124_sor_tx_pu, 3623 }; 3624 3625 static const struct tegra_sor_regs tegra194_sor_regs = { 3626 .head_state0 = 0x151, 3627 .head_state1 = 0x155, 3628 .head_state2 = 0x159, 3629 .head_state3 = 0x15d, 3630 .head_state4 = 0x161, 3631 .head_state5 = 0x165, 3632 .pll0 = 0x169, 3633 .pll1 = 0x16a, 3634 .pll2 = 0x16b, 3635 .pll3 = 0x16c, 3636 .dp_padctl0 = 0x16e, 3637 .dp_padctl2 = 0x16f, 3638 }; 3639 3640 static const struct tegra_sor_soc tegra194_sor = { 3641 .supports_lvds = false, 3642 .supports_hdmi = true, 3643 .supports_dp = true, 3644 .supports_audio = true, 3645 .supports_hdcp = true, 3646 3647 .regs = &tegra194_sor_regs, 3648 .has_nvdisplay = true, 3649 3650 .num_settings = ARRAY_SIZE(tegra194_sor_hdmi_defaults), 3651 .settings = tegra194_sor_hdmi_defaults, 3652 3653 .xbar_cfg = tegra210_sor_xbar_cfg, 3654 .lane_map = tegra124_sor_lane_map, 3655 .voltage_swing = tegra186_sor_voltage_swing, 3656 .pre_emphasis = tegra186_sor_pre_emphasis, 3657 .post_cursor = tegra124_sor_post_cursor, 3658 .tx_pu = tegra124_sor_tx_pu, 3659 }; 3660 3661 static const struct of_device_id tegra_sor_of_match[] = { 3662 { .compatible = "nvidia,tegra194-sor", .data = &tegra194_sor }, 3663 { .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor }, 3664 { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 }, 3665 { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor }, 3666 { .compatible = "nvidia,tegra132-sor", .data = &tegra132_sor }, 3667 { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor }, 3668 { }, 3669 }; 3670 MODULE_DEVICE_TABLE(of, tegra_sor_of_match); 3671 3672 static int tegra_sor_parse_dt(struct tegra_sor *sor) 3673 { 3674 struct device_node *np = sor->dev->of_node; 3675 u32 xbar_cfg[5]; 3676 unsigned int i; 3677 u32 value; 3678 int err; 3679 3680 if (sor->soc->has_nvdisplay) { 3681 err = of_property_read_u32(np, "nvidia,interface", &value); 3682 if (err < 0) 3683 return err; 3684 3685 sor->index = value; 3686 3687 /* 3688 * override the default that we already set for Tegra210 and 3689 * earlier 3690 */ 3691 sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index; 3692 } else { 3693 if (!sor->soc->supports_audio) 3694 sor->index = 0; 3695 else 3696 sor->index = 1; 3697 } 3698 3699 err = of_property_read_u32_array(np, "nvidia,xbar-cfg", xbar_cfg, 5); 3700 if (err < 0) { 3701 /* fall back to default per-SoC XBAR configuration */ 3702 for (i = 0; i < 5; i++) 3703 sor->xbar_cfg[i] = sor->soc->xbar_cfg[i]; 3704 } else { 3705 /* copy cells to SOR XBAR configuration */ 3706 for (i = 0; i < 5; i++) 3707 sor->xbar_cfg[i] = xbar_cfg[i]; 3708 } 3709 3710 return 0; 3711 } 3712 3713 static irqreturn_t tegra_sor_irq(int irq, void *data) 3714 { 3715 struct tegra_sor *sor = data; 3716 u32 value; 3717 3718 value = tegra_sor_readl(sor, SOR_INT_STATUS); 3719 tegra_sor_writel(sor, value, SOR_INT_STATUS); 3720 3721 if (value & SOR_INT_CODEC_SCRATCH0) { 3722 value = tegra_sor_readl(sor, SOR_AUDIO_HDA_CODEC_SCRATCH0); 3723 3724 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) { 3725 unsigned int format; 3726 3727 format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK; 3728 3729 tegra_hda_parse_format(format, &sor->format); 3730 3731 if (sor->ops->audio_enable) 3732 sor->ops->audio_enable(sor); 3733 } else { 3734 if (sor->ops->audio_disable) 3735 sor->ops->audio_disable(sor); 3736 } 3737 } 3738 3739 return IRQ_HANDLED; 3740 } 3741 3742 static int tegra_sor_probe(struct platform_device *pdev) 3743 { 3744 struct device_node *np; 3745 struct tegra_sor *sor; 3746 int err; 3747 3748 sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL); 3749 if (!sor) 3750 return -ENOMEM; 3751 3752 sor->soc = of_device_get_match_data(&pdev->dev); 3753 sor->output.dev = sor->dev = &pdev->dev; 3754 3755 sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings, 3756 sor->soc->num_settings * 3757 sizeof(*sor->settings), 3758 GFP_KERNEL); 3759 if (!sor->settings) 3760 return -ENOMEM; 3761 3762 sor->num_settings = sor->soc->num_settings; 3763 3764 np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0); 3765 if (np) { 3766 sor->aux = drm_dp_aux_find_by_of_node(np); 3767 of_node_put(np); 3768 3769 if (!sor->aux) 3770 return -EPROBE_DEFER; 3771 3772 if (get_device(sor->aux->dev)) 3773 sor->output.ddc = &sor->aux->ddc; 3774 } 3775 3776 if (!sor->aux) { 3777 if (sor->soc->supports_hdmi) { 3778 sor->ops = &tegra_sor_hdmi_ops; 3779 sor->pad = TEGRA_IO_PAD_HDMI; 3780 } else if (sor->soc->supports_lvds) { 3781 dev_err(&pdev->dev, "LVDS not supported yet\n"); 3782 return -ENODEV; 3783 } else { 3784 dev_err(&pdev->dev, "unknown (non-DP) support\n"); 3785 return -ENODEV; 3786 } 3787 } else { 3788 np = of_parse_phandle(pdev->dev.of_node, "nvidia,panel", 0); 3789 /* 3790 * No need to keep this around since we only use it as a check 3791 * to see if a panel is connected (eDP) or not (DP). 3792 */ 3793 of_node_put(np); 3794 3795 sor->ops = &tegra_sor_dp_ops; 3796 sor->pad = TEGRA_IO_PAD_LVDS; 3797 } 3798 3799 err = tegra_sor_parse_dt(sor); 3800 if (err < 0) 3801 goto put_aux; 3802 3803 err = tegra_output_probe(&sor->output); 3804 if (err < 0) { 3805 dev_err_probe(&pdev->dev, err, "failed to probe output\n"); 3806 goto put_aux; 3807 } 3808 3809 if (sor->ops && sor->ops->probe) { 3810 err = sor->ops->probe(sor); 3811 if (err < 0) { 3812 dev_err(&pdev->dev, "failed to probe %s: %d\n", 3813 sor->ops->name, err); 3814 goto remove; 3815 } 3816 } 3817 3818 sor->regs = devm_platform_ioremap_resource(pdev, 0); 3819 if (IS_ERR(sor->regs)) { 3820 err = PTR_ERR(sor->regs); 3821 goto remove; 3822 } 3823 3824 err = platform_get_irq(pdev, 0); 3825 if (err < 0) 3826 goto remove; 3827 3828 sor->irq = err; 3829 3830 err = devm_request_irq(sor->dev, sor->irq, tegra_sor_irq, 0, 3831 dev_name(sor->dev), sor); 3832 if (err < 0) { 3833 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err); 3834 goto remove; 3835 } 3836 3837 sor->rst = devm_reset_control_get_exclusive_released(&pdev->dev, "sor"); 3838 if (IS_ERR(sor->rst)) { 3839 err = PTR_ERR(sor->rst); 3840 3841 if (err != -EBUSY || WARN_ON(!pdev->dev.pm_domain)) { 3842 dev_err(&pdev->dev, "failed to get reset control: %d\n", 3843 err); 3844 goto remove; 3845 } 3846 3847 /* 3848 * At this point, the reset control is most likely being used 3849 * by the generic power domain implementation. With any luck 3850 * the power domain will have taken care of resetting the SOR 3851 * and we don't have to do anything. 3852 */ 3853 sor->rst = NULL; 3854 } 3855 3856 sor->clk = devm_clk_get(&pdev->dev, NULL); 3857 if (IS_ERR(sor->clk)) { 3858 err = PTR_ERR(sor->clk); 3859 dev_err(&pdev->dev, "failed to get module clock: %d\n", err); 3860 goto remove; 3861 } 3862 3863 if (sor->soc->supports_hdmi || sor->soc->supports_dp) { 3864 struct device_node *np = pdev->dev.of_node; 3865 const char *name; 3866 3867 /* 3868 * For backwards compatibility with Tegra210 device trees, 3869 * fall back to the old clock name "source" if the new "out" 3870 * clock is not available. 3871 */ 3872 if (of_property_match_string(np, "clock-names", "out") < 0) 3873 name = "source"; 3874 else 3875 name = "out"; 3876 3877 sor->clk_out = devm_clk_get(&pdev->dev, name); 3878 if (IS_ERR(sor->clk_out)) { 3879 err = PTR_ERR(sor->clk_out); 3880 dev_err(sor->dev, "failed to get %s clock: %d\n", 3881 name, err); 3882 goto remove; 3883 } 3884 } else { 3885 /* fall back to the module clock on SOR0 (eDP/LVDS only) */ 3886 sor->clk_out = sor->clk; 3887 } 3888 3889 sor->clk_parent = devm_clk_get(&pdev->dev, "parent"); 3890 if (IS_ERR(sor->clk_parent)) { 3891 err = PTR_ERR(sor->clk_parent); 3892 dev_err(&pdev->dev, "failed to get parent clock: %d\n", err); 3893 goto remove; 3894 } 3895 3896 sor->clk_safe = devm_clk_get(&pdev->dev, "safe"); 3897 if (IS_ERR(sor->clk_safe)) { 3898 err = PTR_ERR(sor->clk_safe); 3899 dev_err(&pdev->dev, "failed to get safe clock: %d\n", err); 3900 goto remove; 3901 } 3902 3903 sor->clk_dp = devm_clk_get(&pdev->dev, "dp"); 3904 if (IS_ERR(sor->clk_dp)) { 3905 err = PTR_ERR(sor->clk_dp); 3906 dev_err(&pdev->dev, "failed to get DP clock: %d\n", err); 3907 goto remove; 3908 } 3909 3910 /* 3911 * Starting with Tegra186, the BPMP provides an implementation for 3912 * the pad output clock, so we have to look it up from device tree. 3913 */ 3914 sor->clk_pad = devm_clk_get(&pdev->dev, "pad"); 3915 if (IS_ERR(sor->clk_pad)) { 3916 if (sor->clk_pad != ERR_PTR(-ENOENT)) { 3917 err = PTR_ERR(sor->clk_pad); 3918 goto remove; 3919 } 3920 3921 /* 3922 * If the pad output clock is not available, then we assume 3923 * we're on Tegra210 or earlier and have to provide our own 3924 * implementation. 3925 */ 3926 sor->clk_pad = NULL; 3927 } 3928 3929 /* 3930 * The bootloader may have set up the SOR such that it's module clock 3931 * is sourced by one of the display PLLs. However, that doesn't work 3932 * without properly having set up other bits of the SOR. 3933 */ 3934 err = clk_set_parent(sor->clk_out, sor->clk_safe); 3935 if (err < 0) { 3936 dev_err(&pdev->dev, "failed to use safe clock: %d\n", err); 3937 goto remove; 3938 } 3939 3940 platform_set_drvdata(pdev, sor); 3941 pm_runtime_enable(&pdev->dev); 3942 3943 host1x_client_init(&sor->client); 3944 sor->client.ops = &sor_client_ops; 3945 sor->client.dev = &pdev->dev; 3946 3947 /* 3948 * On Tegra210 and earlier, provide our own implementation for the 3949 * pad output clock. 3950 */ 3951 if (!sor->clk_pad) { 3952 char *name; 3953 3954 name = devm_kasprintf(sor->dev, GFP_KERNEL, "sor%u_pad_clkout", 3955 sor->index); 3956 if (!name) { 3957 err = -ENOMEM; 3958 goto uninit; 3959 } 3960 3961 err = host1x_client_resume(&sor->client); 3962 if (err < 0) { 3963 dev_err(sor->dev, "failed to resume: %d\n", err); 3964 goto uninit; 3965 } 3966 3967 sor->clk_pad = tegra_clk_sor_pad_register(sor, name); 3968 host1x_client_suspend(&sor->client); 3969 } 3970 3971 if (IS_ERR(sor->clk_pad)) { 3972 err = PTR_ERR(sor->clk_pad); 3973 dev_err(sor->dev, "failed to register SOR pad clock: %d\n", 3974 err); 3975 goto uninit; 3976 } 3977 3978 err = __host1x_client_register(&sor->client); 3979 if (err < 0) { 3980 dev_err(&pdev->dev, "failed to register host1x client: %d\n", 3981 err); 3982 goto uninit; 3983 } 3984 3985 return 0; 3986 3987 uninit: 3988 host1x_client_exit(&sor->client); 3989 pm_runtime_disable(&pdev->dev); 3990 remove: 3991 if (sor->aux) 3992 sor->output.ddc = NULL; 3993 3994 tegra_output_remove(&sor->output); 3995 put_aux: 3996 if (sor->aux) 3997 put_device(sor->aux->dev); 3998 3999 return err; 4000 } 4001 4002 static void tegra_sor_remove(struct platform_device *pdev) 4003 { 4004 struct tegra_sor *sor = platform_get_drvdata(pdev); 4005 4006 host1x_client_unregister(&sor->client); 4007 4008 pm_runtime_disable(&pdev->dev); 4009 4010 if (sor->aux) { 4011 put_device(sor->aux->dev); 4012 sor->output.ddc = NULL; 4013 } 4014 4015 tegra_output_remove(&sor->output); 4016 } 4017 4018 static int __maybe_unused tegra_sor_suspend(struct device *dev) 4019 { 4020 struct tegra_sor *sor = dev_get_drvdata(dev); 4021 int err; 4022 4023 err = tegra_output_suspend(&sor->output); 4024 if (err < 0) { 4025 dev_err(dev, "failed to suspend output: %d\n", err); 4026 return err; 4027 } 4028 4029 if (sor->hdmi_supply) { 4030 err = regulator_disable(sor->hdmi_supply); 4031 if (err < 0) { 4032 tegra_output_resume(&sor->output); 4033 return err; 4034 } 4035 } 4036 4037 return 0; 4038 } 4039 4040 static int __maybe_unused tegra_sor_resume(struct device *dev) 4041 { 4042 struct tegra_sor *sor = dev_get_drvdata(dev); 4043 int err; 4044 4045 if (sor->hdmi_supply) { 4046 err = regulator_enable(sor->hdmi_supply); 4047 if (err < 0) 4048 return err; 4049 } 4050 4051 err = tegra_output_resume(&sor->output); 4052 if (err < 0) { 4053 dev_err(dev, "failed to resume output: %d\n", err); 4054 4055 if (sor->hdmi_supply) 4056 regulator_disable(sor->hdmi_supply); 4057 4058 return err; 4059 } 4060 4061 return 0; 4062 } 4063 4064 static const struct dev_pm_ops tegra_sor_pm_ops = { 4065 SET_SYSTEM_SLEEP_PM_OPS(tegra_sor_suspend, tegra_sor_resume) 4066 }; 4067 4068 struct platform_driver tegra_sor_driver = { 4069 .driver = { 4070 .name = "tegra-sor", 4071 .of_match_table = tegra_sor_of_match, 4072 .pm = &tegra_sor_pm_ops, 4073 }, 4074 .probe = tegra_sor_probe, 4075 .remove = tegra_sor_remove, 4076 }; 4077