1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012 Avionic Design GmbH 4 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/of.h> 9 10 #include <drm/drm_atomic_helper.h> 11 #include <drm/drm_bridge_connector.h> 12 #include <drm/drm_simple_kms_helper.h> 13 14 #include "drm.h" 15 #include "dc.h" 16 17 struct tegra_rgb { 18 struct tegra_output output; 19 struct tegra_dc *dc; 20 21 struct clk *pll_d_out0; 22 struct clk *pll_d2_out0; 23 struct clk *clk_parent; 24 struct clk *clk; 25 }; 26 27 static inline struct tegra_rgb *to_rgb(struct tegra_output *output) 28 { 29 return container_of(output, struct tegra_rgb, output); 30 } 31 32 struct reg_entry { 33 unsigned long offset; 34 unsigned long value; 35 }; 36 37 static const struct reg_entry rgb_enable[] = { 38 { DC_COM_PIN_OUTPUT_ENABLE(0), 0x00000000 }, 39 { DC_COM_PIN_OUTPUT_ENABLE(1), 0x00000000 }, 40 { DC_COM_PIN_OUTPUT_ENABLE(2), 0x00000000 }, 41 { DC_COM_PIN_OUTPUT_ENABLE(3), 0x00000000 }, 42 { DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 }, 43 { DC_COM_PIN_OUTPUT_POLARITY(1), 0x01000000 }, 44 { DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 }, 45 { DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 }, 46 { DC_COM_PIN_OUTPUT_DATA(0), 0x00000000 }, 47 { DC_COM_PIN_OUTPUT_DATA(1), 0x00000000 }, 48 { DC_COM_PIN_OUTPUT_DATA(2), 0x00000000 }, 49 { DC_COM_PIN_OUTPUT_DATA(3), 0x00000000 }, 50 { DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 }, 51 { DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 }, 52 { DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 }, 53 { DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 }, 54 { DC_COM_PIN_OUTPUT_SELECT(4), 0x00210222 }, 55 { DC_COM_PIN_OUTPUT_SELECT(5), 0x00002200 }, 56 { DC_COM_PIN_OUTPUT_SELECT(6), 0x00020000 }, 57 }; 58 59 static const struct reg_entry rgb_disable[] = { 60 { DC_COM_PIN_OUTPUT_SELECT(6), 0x00000000 }, 61 { DC_COM_PIN_OUTPUT_SELECT(5), 0x00000000 }, 62 { DC_COM_PIN_OUTPUT_SELECT(4), 0x00000000 }, 63 { DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 }, 64 { DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 }, 65 { DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 }, 66 { DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 }, 67 { DC_COM_PIN_OUTPUT_DATA(3), 0xaaaaaaaa }, 68 { DC_COM_PIN_OUTPUT_DATA(2), 0xaaaaaaaa }, 69 { DC_COM_PIN_OUTPUT_DATA(1), 0xaaaaaaaa }, 70 { DC_COM_PIN_OUTPUT_DATA(0), 0xaaaaaaaa }, 71 { DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 }, 72 { DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 }, 73 { DC_COM_PIN_OUTPUT_POLARITY(1), 0x00000000 }, 74 { DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 }, 75 { DC_COM_PIN_OUTPUT_ENABLE(3), 0x55555555 }, 76 { DC_COM_PIN_OUTPUT_ENABLE(2), 0x55555555 }, 77 { DC_COM_PIN_OUTPUT_ENABLE(1), 0x55150005 }, 78 { DC_COM_PIN_OUTPUT_ENABLE(0), 0x55555555 }, 79 }; 80 81 static void tegra_dc_write_regs(struct tegra_dc *dc, 82 const struct reg_entry *table, 83 unsigned int num) 84 { 85 unsigned int i; 86 87 for (i = 0; i < num; i++) 88 tegra_dc_writel(dc, table[i].value, table[i].offset); 89 } 90 91 static void tegra_rgb_encoder_disable(struct drm_encoder *encoder) 92 { 93 struct tegra_output *output = encoder_to_output(encoder); 94 struct tegra_rgb *rgb = to_rgb(output); 95 96 tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable)); 97 tegra_dc_commit(rgb->dc); 98 } 99 100 static void tegra_rgb_encoder_enable(struct drm_encoder *encoder) 101 { 102 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 103 struct tegra_output *output = encoder_to_output(encoder); 104 struct tegra_rgb *rgb = to_rgb(output); 105 u32 value; 106 107 tegra_dc_write_regs(rgb->dc, rgb_enable, ARRAY_SIZE(rgb_enable)); 108 109 value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL; 110 tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS); 111 112 /* configure H- and V-sync signal polarities */ 113 value = tegra_dc_readl(rgb->dc, DC_COM_PIN_OUTPUT_POLARITY(1)); 114 115 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 116 value |= LHS_OUTPUT_POLARITY_LOW; 117 else 118 value &= ~LHS_OUTPUT_POLARITY_LOW; 119 120 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 121 value |= LVS_OUTPUT_POLARITY_LOW; 122 else 123 value &= ~LVS_OUTPUT_POLARITY_LOW; 124 125 tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(1)); 126 127 /* XXX: parameterize? */ 128 value = DISP_DATA_FORMAT_DF1P1C | DISP_ALIGNMENT_MSB | 129 DISP_ORDER_RED_BLUE; 130 tegra_dc_writel(rgb->dc, value, DC_DISP_DISP_INTERFACE_CONTROL); 131 132 tegra_dc_commit(rgb->dc); 133 } 134 135 static bool tegra_rgb_pll_rate_change_allowed(struct tegra_rgb *rgb) 136 { 137 if (!rgb->pll_d2_out0) 138 return false; 139 140 if (!clk_is_match(rgb->clk_parent, rgb->pll_d_out0) && 141 !clk_is_match(rgb->clk_parent, rgb->pll_d2_out0)) 142 return false; 143 144 return true; 145 } 146 147 static int 148 tegra_rgb_encoder_atomic_check(struct drm_encoder *encoder, 149 struct drm_crtc_state *crtc_state, 150 struct drm_connector_state *conn_state) 151 { 152 struct tegra_output *output = encoder_to_output(encoder); 153 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc); 154 unsigned long pclk = crtc_state->mode.clock * 1000; 155 struct tegra_rgb *rgb = to_rgb(output); 156 unsigned int div; 157 int err; 158 159 /* 160 * We may not want to change the frequency of the parent clock, since 161 * it may be a parent for other peripherals. This is due to the fact 162 * that on Tegra20 there's only a single clock dedicated to display 163 * (pll_d_out0), whereas later generations have a second one that can 164 * be used to independently drive a second output (pll_d2_out0). 165 * 166 * As a way to support multiple outputs on Tegra20 as well, pll_p is 167 * typically used as the parent clock for the display controllers. 168 * But this comes at a cost: pll_p is the parent of several other 169 * peripherals, so its frequency shouldn't change out of the blue. 170 * 171 * The best we can do at this point is to use the shift clock divider 172 * and hope that the desired frequency can be matched (or at least 173 * matched sufficiently close that the panel will still work). 174 */ 175 if (tegra_rgb_pll_rate_change_allowed(rgb)) { 176 /* 177 * Set display controller clock to x2 of PCLK in order to 178 * produce higher resolution pulse positions. 179 */ 180 div = 2; 181 pclk *= 2; 182 } else { 183 div = ((clk_get_rate(rgb->clk) * 2) / pclk) - 2; 184 pclk = 0; 185 } 186 187 err = tegra_dc_state_setup_clock(dc, crtc_state, rgb->clk_parent, 188 pclk, div); 189 if (err < 0) { 190 dev_err(output->dev, "failed to setup CRTC state: %d\n", err); 191 return err; 192 } 193 194 return err; 195 } 196 197 static const struct drm_encoder_helper_funcs tegra_rgb_encoder_helper_funcs = { 198 .disable = tegra_rgb_encoder_disable, 199 .enable = tegra_rgb_encoder_enable, 200 .atomic_check = tegra_rgb_encoder_atomic_check, 201 }; 202 203 static void tegra_dc_of_node_put(void *data) 204 { 205 of_node_put(data); 206 } 207 208 int tegra_dc_rgb_probe(struct tegra_dc *dc) 209 { 210 struct device_node *np; 211 struct tegra_rgb *rgb; 212 int err; 213 214 np = of_get_child_by_name(dc->dev->of_node, "rgb"); 215 if (!np) 216 return -ENODEV; 217 218 err = devm_add_action_or_reset(dc->dev, tegra_dc_of_node_put, np); 219 if (err < 0) 220 return err; 221 222 if (!of_device_is_available(np)) 223 return -ENODEV; 224 225 rgb = devm_kzalloc(dc->dev, sizeof(*rgb), GFP_KERNEL); 226 if (!rgb) 227 return -ENOMEM; 228 229 rgb->output.dev = dc->dev; 230 rgb->output.of_node = np; 231 rgb->dc = dc; 232 233 err = tegra_output_probe(&rgb->output); 234 if (err < 0) 235 return err; 236 237 rgb->clk = devm_clk_get(dc->dev, NULL); 238 if (IS_ERR(rgb->clk)) { 239 dev_err(dc->dev, "failed to get clock\n"); 240 err = PTR_ERR(rgb->clk); 241 goto remove; 242 } 243 244 rgb->clk_parent = devm_clk_get(dc->dev, "parent"); 245 if (IS_ERR(rgb->clk_parent)) { 246 dev_err(dc->dev, "failed to get parent clock\n"); 247 err = PTR_ERR(rgb->clk_parent); 248 goto remove; 249 } 250 251 err = clk_set_parent(rgb->clk, rgb->clk_parent); 252 if (err < 0) { 253 dev_err(dc->dev, "failed to set parent clock: %d\n", err); 254 goto remove; 255 } 256 257 rgb->pll_d_out0 = clk_get_sys(NULL, "pll_d_out0"); 258 if (IS_ERR(rgb->pll_d_out0)) { 259 err = PTR_ERR(rgb->pll_d_out0); 260 dev_err(dc->dev, "failed to get pll_d_out0: %d\n", err); 261 goto remove; 262 } 263 264 if (dc->soc->has_pll_d2_out0) { 265 rgb->pll_d2_out0 = clk_get_sys(NULL, "pll_d2_out0"); 266 if (IS_ERR(rgb->pll_d2_out0)) { 267 err = PTR_ERR(rgb->pll_d2_out0); 268 dev_err(dc->dev, "failed to get pll_d2_out0: %d\n", err); 269 goto put_pll; 270 } 271 } 272 273 dc->rgb = &rgb->output; 274 275 return 0; 276 277 put_pll: 278 clk_put(rgb->pll_d_out0); 279 remove: 280 tegra_output_remove(&rgb->output); 281 return err; 282 } 283 284 void tegra_dc_rgb_remove(struct tegra_dc *dc) 285 { 286 struct tegra_rgb *rgb; 287 288 if (!dc->rgb) 289 return; 290 291 rgb = to_rgb(dc->rgb); 292 clk_put(rgb->pll_d2_out0); 293 clk_put(rgb->pll_d_out0); 294 295 tegra_output_remove(dc->rgb); 296 dc->rgb = NULL; 297 } 298 299 int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc) 300 { 301 struct tegra_output *output = dc->rgb; 302 struct drm_connector *connector; 303 int err; 304 305 if (!dc->rgb) 306 return -ENODEV; 307 308 drm_simple_encoder_init(drm, &output->encoder, DRM_MODE_ENCODER_LVDS); 309 drm_encoder_helper_add(&output->encoder, 310 &tegra_rgb_encoder_helper_funcs); 311 312 /* 313 * Wrap directly-connected panel into DRM bridge in order to let 314 * DRM core to handle panel for us. 315 */ 316 if (output->panel) { 317 output->bridge = devm_drm_panel_bridge_add(output->dev, 318 output->panel); 319 if (IS_ERR(output->bridge)) { 320 dev_err(output->dev, 321 "failed to wrap panel into bridge: %pe\n", 322 output->bridge); 323 return PTR_ERR(output->bridge); 324 } 325 326 output->panel = NULL; 327 } 328 329 /* 330 * Tegra devices that have LVDS panel utilize LVDS encoder bridge 331 * for converting up to 28 LCD LVTTL lanes into 5/4 LVDS lanes that 332 * go to display panel's receiver. 333 * 334 * Encoder usually have a power-down control which needs to be enabled 335 * in order to transmit data to the panel. Historically devices that 336 * use an older device-tree version didn't model the bridge, assuming 337 * that encoder is turned ON by default, while today's DRM allows us 338 * to model LVDS encoder properly. 339 * 340 * Newer device-trees utilize LVDS encoder bridge, which provides 341 * us with a connector and handles the display panel. 342 * 343 * For older device-trees we wrapped panel into the panel-bridge. 344 */ 345 if (output->bridge) { 346 err = drm_bridge_attach(&output->encoder, output->bridge, 347 NULL, DRM_BRIDGE_ATTACH_NO_CONNECTOR); 348 if (err) 349 return err; 350 351 connector = drm_bridge_connector_init(drm, &output->encoder); 352 if (IS_ERR(connector)) { 353 dev_err(output->dev, 354 "failed to initialize bridge connector: %pe\n", 355 connector); 356 return PTR_ERR(connector); 357 } 358 359 drm_connector_attach_encoder(connector, &output->encoder); 360 } 361 362 err = tegra_output_init(drm, output); 363 if (err < 0) { 364 dev_err(output->dev, "failed to initialize output: %d\n", err); 365 return err; 366 } 367 368 /* 369 * Other outputs can be attached to either display controller. The RGB 370 * outputs are an exception and work only with their parent display 371 * controller. 372 */ 373 output->encoder.possible_crtcs = drm_crtc_mask(&dc->base); 374 375 return 0; 376 } 377 378 int tegra_dc_rgb_exit(struct tegra_dc *dc) 379 { 380 if (dc->rgb) 381 tegra_output_exit(dc->rgb); 382 383 return 0; 384 } 385