1 /* 2 * Copyright (C) 2017 NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/host1x.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/of_device.h> 14 #include <linux/of_graph.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/reset.h> 18 19 #include <drm/drmP.h> 20 #include <drm/drm_atomic.h> 21 #include <drm/drm_atomic_helper.h> 22 #include <drm/drm_probe_helper.h> 23 24 #include "drm.h" 25 #include "dc.h" 26 #include "plane.h" 27 28 static const u32 tegra_shared_plane_formats[] = { 29 DRM_FORMAT_ARGB1555, 30 DRM_FORMAT_RGB565, 31 DRM_FORMAT_RGBA5551, 32 DRM_FORMAT_ARGB8888, 33 DRM_FORMAT_ABGR8888, 34 /* new on Tegra114 */ 35 DRM_FORMAT_ABGR4444, 36 DRM_FORMAT_ABGR1555, 37 DRM_FORMAT_BGRA5551, 38 DRM_FORMAT_XRGB1555, 39 DRM_FORMAT_RGBX5551, 40 DRM_FORMAT_XBGR1555, 41 DRM_FORMAT_BGRX5551, 42 DRM_FORMAT_BGR565, 43 DRM_FORMAT_XRGB8888, 44 DRM_FORMAT_XBGR8888, 45 /* planar formats */ 46 DRM_FORMAT_UYVY, 47 DRM_FORMAT_YUYV, 48 DRM_FORMAT_YUV420, 49 DRM_FORMAT_YUV422, 50 }; 51 52 static const u64 tegra_shared_plane_modifiers[] = { 53 DRM_FORMAT_MOD_LINEAR, 54 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0), 55 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1), 56 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2), 57 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3), 58 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4), 59 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5), 60 DRM_FORMAT_MOD_INVALID 61 }; 62 63 static inline unsigned int tegra_plane_offset(struct tegra_plane *plane, 64 unsigned int offset) 65 { 66 if (offset >= 0x500 && offset <= 0x581) { 67 offset = 0x000 + (offset - 0x500); 68 return plane->offset + offset; 69 } 70 71 if (offset >= 0x700 && offset <= 0x73c) { 72 offset = 0x180 + (offset - 0x700); 73 return plane->offset + offset; 74 } 75 76 if (offset >= 0x800 && offset <= 0x83e) { 77 offset = 0x1c0 + (offset - 0x800); 78 return plane->offset + offset; 79 } 80 81 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset); 82 83 return plane->offset + offset; 84 } 85 86 static inline u32 tegra_plane_readl(struct tegra_plane *plane, 87 unsigned int offset) 88 { 89 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset)); 90 } 91 92 static inline void tegra_plane_writel(struct tegra_plane *plane, u32 value, 93 unsigned int offset) 94 { 95 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset)); 96 } 97 98 static int tegra_windowgroup_enable(struct tegra_windowgroup *wgrp) 99 { 100 mutex_lock(&wgrp->lock); 101 102 if (wgrp->usecount == 0) { 103 pm_runtime_get_sync(wgrp->parent); 104 reset_control_deassert(wgrp->rst); 105 } 106 107 wgrp->usecount++; 108 mutex_unlock(&wgrp->lock); 109 110 return 0; 111 } 112 113 static void tegra_windowgroup_disable(struct tegra_windowgroup *wgrp) 114 { 115 int err; 116 117 mutex_lock(&wgrp->lock); 118 119 if (wgrp->usecount == 1) { 120 err = reset_control_assert(wgrp->rst); 121 if (err < 0) { 122 pr_err("failed to assert reset for window group %u\n", 123 wgrp->index); 124 } 125 126 pm_runtime_put(wgrp->parent); 127 } 128 129 wgrp->usecount--; 130 mutex_unlock(&wgrp->lock); 131 } 132 133 int tegra_display_hub_prepare(struct tegra_display_hub *hub) 134 { 135 unsigned int i; 136 137 /* 138 * XXX Enabling/disabling windowgroups needs to happen when the owner 139 * display controller is disabled. There's currently no good point at 140 * which this could be executed, so unconditionally enable all window 141 * groups for now. 142 */ 143 for (i = 0; i < hub->soc->num_wgrps; i++) { 144 struct tegra_windowgroup *wgrp = &hub->wgrps[i]; 145 146 tegra_windowgroup_enable(wgrp); 147 } 148 149 return 0; 150 } 151 152 void tegra_display_hub_cleanup(struct tegra_display_hub *hub) 153 { 154 unsigned int i; 155 156 /* 157 * XXX Remove this once window groups can be more fine-grainedly 158 * enabled and disabled. 159 */ 160 for (i = 0; i < hub->soc->num_wgrps; i++) { 161 struct tegra_windowgroup *wgrp = &hub->wgrps[i]; 162 163 tegra_windowgroup_disable(wgrp); 164 } 165 } 166 167 static void tegra_shared_plane_update(struct tegra_plane *plane) 168 { 169 struct tegra_dc *dc = plane->dc; 170 unsigned long timeout; 171 u32 mask, value; 172 173 mask = COMMON_UPDATE | WIN_A_UPDATE << plane->base.index; 174 tegra_dc_writel(dc, mask, DC_CMD_STATE_CONTROL); 175 176 timeout = jiffies + msecs_to_jiffies(1000); 177 178 while (time_before(jiffies, timeout)) { 179 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); 180 if ((value & mask) == 0) 181 break; 182 183 usleep_range(100, 400); 184 } 185 } 186 187 static void tegra_shared_plane_activate(struct tegra_plane *plane) 188 { 189 struct tegra_dc *dc = plane->dc; 190 unsigned long timeout; 191 u32 mask, value; 192 193 mask = COMMON_ACTREQ | WIN_A_ACT_REQ << plane->base.index; 194 tegra_dc_writel(dc, mask, DC_CMD_STATE_CONTROL); 195 196 timeout = jiffies + msecs_to_jiffies(1000); 197 198 while (time_before(jiffies, timeout)) { 199 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); 200 if ((value & mask) == 0) 201 break; 202 203 usleep_range(100, 400); 204 } 205 } 206 207 static unsigned int 208 tegra_shared_plane_get_owner(struct tegra_plane *plane, struct tegra_dc *dc) 209 { 210 unsigned int offset = 211 tegra_plane_offset(plane, DC_WIN_CORE_WINDOWGROUP_SET_CONTROL); 212 213 return tegra_dc_readl(dc, offset) & OWNER_MASK; 214 } 215 216 static bool tegra_dc_owns_shared_plane(struct tegra_dc *dc, 217 struct tegra_plane *plane) 218 { 219 struct device *dev = dc->dev; 220 221 if (tegra_shared_plane_get_owner(plane, dc) == dc->pipe) { 222 if (plane->dc == dc) 223 return true; 224 225 dev_WARN(dev, "head %u owns window %u but is not attached\n", 226 dc->pipe, plane->index); 227 } 228 229 return false; 230 } 231 232 static int tegra_shared_plane_set_owner(struct tegra_plane *plane, 233 struct tegra_dc *new) 234 { 235 unsigned int offset = 236 tegra_plane_offset(plane, DC_WIN_CORE_WINDOWGROUP_SET_CONTROL); 237 struct tegra_dc *old = plane->dc, *dc = new ? new : old; 238 struct device *dev = new ? new->dev : old->dev; 239 unsigned int owner, index = plane->index; 240 u32 value; 241 242 value = tegra_dc_readl(dc, offset); 243 owner = value & OWNER_MASK; 244 245 if (new && (owner != OWNER_MASK && owner != new->pipe)) { 246 dev_WARN(dev, "window %u owned by head %u\n", index, owner); 247 return -EBUSY; 248 } 249 250 /* 251 * This seems to happen whenever the head has been disabled with one 252 * or more windows being active. This is harmless because we'll just 253 * reassign the window to the new head anyway. 254 */ 255 if (old && owner == OWNER_MASK) 256 dev_dbg(dev, "window %u not owned by head %u but %u\n", index, 257 old->pipe, owner); 258 259 value &= ~OWNER_MASK; 260 261 if (new) 262 value |= OWNER(new->pipe); 263 else 264 value |= OWNER_MASK; 265 266 tegra_dc_writel(dc, value, offset); 267 268 plane->dc = new; 269 270 return 0; 271 } 272 273 static void tegra_dc_assign_shared_plane(struct tegra_dc *dc, 274 struct tegra_plane *plane) 275 { 276 u32 value; 277 int err; 278 279 if (!tegra_dc_owns_shared_plane(dc, plane)) { 280 err = tegra_shared_plane_set_owner(plane, dc); 281 if (err < 0) 282 return; 283 } 284 285 value = tegra_plane_readl(plane, DC_WIN_CORE_IHUB_LINEBUF_CONFIG); 286 value |= MODE_FOUR_LINES; 287 tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_LINEBUF_CONFIG); 288 289 value = tegra_plane_readl(plane, DC_WIN_CORE_IHUB_WGRP_FETCH_METER); 290 value = SLOTS(1); 291 tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_WGRP_FETCH_METER); 292 293 /* disable watermark */ 294 value = tegra_plane_readl(plane, DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLA); 295 value &= ~LATENCY_CTL_MODE_ENABLE; 296 tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLA); 297 298 value = tegra_plane_readl(plane, DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLB); 299 value |= WATERMARK_MASK; 300 tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLB); 301 302 /* pipe meter */ 303 value = tegra_plane_readl(plane, DC_WIN_CORE_PRECOMP_WGRP_PIPE_METER); 304 value = PIPE_METER_INT(0) | PIPE_METER_FRAC(0); 305 tegra_plane_writel(plane, value, DC_WIN_CORE_PRECOMP_WGRP_PIPE_METER); 306 307 /* mempool entries */ 308 value = tegra_plane_readl(plane, DC_WIN_CORE_IHUB_WGRP_POOL_CONFIG); 309 value = MEMPOOL_ENTRIES(0x331); 310 tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_WGRP_POOL_CONFIG); 311 312 value = tegra_plane_readl(plane, DC_WIN_CORE_IHUB_THREAD_GROUP); 313 value &= ~THREAD_NUM_MASK; 314 value |= THREAD_NUM(plane->base.index); 315 value |= THREAD_GROUP_ENABLE; 316 tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_THREAD_GROUP); 317 318 tegra_shared_plane_update(plane); 319 tegra_shared_plane_activate(plane); 320 } 321 322 static void tegra_dc_remove_shared_plane(struct tegra_dc *dc, 323 struct tegra_plane *plane) 324 { 325 tegra_shared_plane_set_owner(plane, NULL); 326 } 327 328 static int tegra_shared_plane_atomic_check(struct drm_plane *plane, 329 struct drm_plane_state *state) 330 { 331 struct tegra_plane_state *plane_state = to_tegra_plane_state(state); 332 struct tegra_shared_plane *tegra = to_tegra_shared_plane(plane); 333 struct tegra_bo_tiling *tiling = &plane_state->tiling; 334 struct tegra_dc *dc = to_tegra_dc(state->crtc); 335 int err; 336 337 /* no need for further checks if the plane is being disabled */ 338 if (!state->crtc || !state->fb) 339 return 0; 340 341 err = tegra_plane_format(state->fb->format->format, 342 &plane_state->format, 343 &plane_state->swap); 344 if (err < 0) 345 return err; 346 347 err = tegra_fb_get_tiling(state->fb, tiling); 348 if (err < 0) 349 return err; 350 351 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK && 352 !dc->soc->supports_block_linear) { 353 DRM_ERROR("hardware doesn't support block linear mode\n"); 354 return -EINVAL; 355 } 356 357 /* 358 * Tegra doesn't support different strides for U and V planes so we 359 * error out if the user tries to display a framebuffer with such a 360 * configuration. 361 */ 362 if (state->fb->format->num_planes > 2) { 363 if (state->fb->pitches[2] != state->fb->pitches[1]) { 364 DRM_ERROR("unsupported UV-plane configuration\n"); 365 return -EINVAL; 366 } 367 } 368 369 /* XXX scaling is not yet supported, add a check here */ 370 371 err = tegra_plane_state_add(&tegra->base, state); 372 if (err < 0) 373 return err; 374 375 return 0; 376 } 377 378 static void tegra_shared_plane_atomic_disable(struct drm_plane *plane, 379 struct drm_plane_state *old_state) 380 { 381 struct tegra_plane *p = to_tegra_plane(plane); 382 struct tegra_dc *dc; 383 u32 value; 384 385 /* rien ne va plus */ 386 if (!old_state || !old_state->crtc) 387 return; 388 389 dc = to_tegra_dc(old_state->crtc); 390 391 /* 392 * XXX Legacy helpers seem to sometimes call ->atomic_disable() even 393 * on planes that are already disabled. Make sure we fallback to the 394 * head for this particular state instead of crashing. 395 */ 396 if (WARN_ON(p->dc == NULL)) 397 p->dc = dc; 398 399 pm_runtime_get_sync(dc->dev); 400 401 value = tegra_plane_readl(p, DC_WIN_WIN_OPTIONS); 402 value &= ~WIN_ENABLE; 403 tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS); 404 405 tegra_dc_remove_shared_plane(dc, p); 406 407 pm_runtime_put(dc->dev); 408 } 409 410 static void tegra_shared_plane_atomic_update(struct drm_plane *plane, 411 struct drm_plane_state *old_state) 412 { 413 struct tegra_plane_state *state = to_tegra_plane_state(plane->state); 414 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc); 415 unsigned int zpos = plane->state->normalized_zpos; 416 struct drm_framebuffer *fb = plane->state->fb; 417 struct tegra_plane *p = to_tegra_plane(plane); 418 struct tegra_bo *bo; 419 dma_addr_t base; 420 u32 value; 421 422 /* rien ne va plus */ 423 if (!plane->state->crtc || !plane->state->fb) 424 return; 425 426 if (!plane->state->visible) { 427 tegra_shared_plane_atomic_disable(plane, old_state); 428 return; 429 } 430 431 pm_runtime_get_sync(dc->dev); 432 433 tegra_dc_assign_shared_plane(dc, p); 434 435 tegra_plane_writel(p, VCOUNTER, DC_WIN_CORE_ACT_CONTROL); 436 437 /* blending */ 438 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 | 439 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC | 440 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC; 441 tegra_plane_writel(p, value, DC_WIN_BLEND_MATCH_SELECT); 442 443 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 | 444 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC | 445 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC; 446 tegra_plane_writel(p, value, DC_WIN_BLEND_NOMATCH_SELECT); 447 448 value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - zpos); 449 tegra_plane_writel(p, value, DC_WIN_BLEND_LAYER_CONTROL); 450 451 /* bypass scaling */ 452 value = HORIZONTAL_TAPS_5 | VERTICAL_TAPS_5; 453 tegra_plane_writel(p, value, DC_WIN_WINDOWGROUP_SET_CONTROL_INPUT_SCALER); 454 455 value = INPUT_SCALER_VBYPASS | INPUT_SCALER_HBYPASS; 456 tegra_plane_writel(p, value, DC_WIN_WINDOWGROUP_SET_INPUT_SCALER_USAGE); 457 458 /* disable compression */ 459 tegra_plane_writel(p, 0, DC_WINBUF_CDE_CONTROL); 460 461 bo = tegra_fb_get_plane(fb, 0); 462 base = bo->paddr; 463 464 tegra_plane_writel(p, state->format, DC_WIN_COLOR_DEPTH); 465 tegra_plane_writel(p, 0, DC_WIN_PRECOMP_WGRP_PARAMS); 466 467 value = V_POSITION(plane->state->crtc_y) | 468 H_POSITION(plane->state->crtc_x); 469 tegra_plane_writel(p, value, DC_WIN_POSITION); 470 471 value = V_SIZE(plane->state->crtc_h) | H_SIZE(plane->state->crtc_w); 472 tegra_plane_writel(p, value, DC_WIN_SIZE); 473 474 value = WIN_ENABLE | COLOR_EXPAND; 475 tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS); 476 477 value = V_SIZE(plane->state->crtc_h) | H_SIZE(plane->state->crtc_w); 478 tegra_plane_writel(p, value, DC_WIN_CROPPED_SIZE); 479 480 tegra_plane_writel(p, upper_32_bits(base), DC_WINBUF_START_ADDR_HI); 481 tegra_plane_writel(p, lower_32_bits(base), DC_WINBUF_START_ADDR); 482 483 value = PITCH(fb->pitches[0]); 484 tegra_plane_writel(p, value, DC_WIN_PLANAR_STORAGE); 485 486 value = CLAMP_BEFORE_BLEND | DEGAMMA_SRGB | INPUT_RANGE_FULL; 487 tegra_plane_writel(p, value, DC_WIN_SET_PARAMS); 488 489 value = OFFSET_X(plane->state->src_y >> 16) | 490 OFFSET_Y(plane->state->src_x >> 16); 491 tegra_plane_writel(p, value, DC_WINBUF_CROPPED_POINT); 492 493 if (dc->soc->supports_block_linear) { 494 unsigned long height = state->tiling.value; 495 496 /* XXX */ 497 switch (state->tiling.mode) { 498 case TEGRA_BO_TILING_MODE_PITCH: 499 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(0) | 500 DC_WINBUF_SURFACE_KIND_PITCH; 501 break; 502 503 /* XXX not supported on Tegra186 and later */ 504 case TEGRA_BO_TILING_MODE_TILED: 505 value = DC_WINBUF_SURFACE_KIND_TILED; 506 break; 507 508 case TEGRA_BO_TILING_MODE_BLOCK: 509 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) | 510 DC_WINBUF_SURFACE_KIND_BLOCK; 511 break; 512 } 513 514 tegra_plane_writel(p, value, DC_WINBUF_SURFACE_KIND); 515 } 516 517 /* disable gamut CSC */ 518 value = tegra_plane_readl(p, DC_WIN_WINDOW_SET_CONTROL); 519 value &= ~CONTROL_CSC_ENABLE; 520 tegra_plane_writel(p, value, DC_WIN_WINDOW_SET_CONTROL); 521 522 pm_runtime_put(dc->dev); 523 } 524 525 static const struct drm_plane_helper_funcs tegra_shared_plane_helper_funcs = { 526 .atomic_check = tegra_shared_plane_atomic_check, 527 .atomic_update = tegra_shared_plane_atomic_update, 528 .atomic_disable = tegra_shared_plane_atomic_disable, 529 }; 530 531 struct drm_plane *tegra_shared_plane_create(struct drm_device *drm, 532 struct tegra_dc *dc, 533 unsigned int wgrp, 534 unsigned int index) 535 { 536 enum drm_plane_type type = DRM_PLANE_TYPE_OVERLAY; 537 struct tegra_drm *tegra = drm->dev_private; 538 struct tegra_display_hub *hub = tegra->hub; 539 /* planes can be assigned to arbitrary CRTCs */ 540 unsigned int possible_crtcs = 0x7; 541 struct tegra_shared_plane *plane; 542 unsigned int num_formats; 543 const u64 *modifiers; 544 struct drm_plane *p; 545 const u32 *formats; 546 int err; 547 548 plane = kzalloc(sizeof(*plane), GFP_KERNEL); 549 if (!plane) 550 return ERR_PTR(-ENOMEM); 551 552 plane->base.offset = 0x0a00 + 0x0300 * index; 553 plane->base.index = index; 554 555 plane->wgrp = &hub->wgrps[wgrp]; 556 plane->wgrp->parent = dc->dev; 557 558 p = &plane->base.base; 559 560 num_formats = ARRAY_SIZE(tegra_shared_plane_formats); 561 formats = tegra_shared_plane_formats; 562 modifiers = tegra_shared_plane_modifiers; 563 564 err = drm_universal_plane_init(drm, p, possible_crtcs, 565 &tegra_plane_funcs, formats, 566 num_formats, modifiers, type, NULL); 567 if (err < 0) { 568 kfree(plane); 569 return ERR_PTR(err); 570 } 571 572 drm_plane_helper_add(p, &tegra_shared_plane_helper_funcs); 573 drm_plane_create_zpos_property(p, 0, 0, 255); 574 575 return p; 576 } 577 578 static struct drm_private_state * 579 tegra_display_hub_duplicate_state(struct drm_private_obj *obj) 580 { 581 struct tegra_display_hub_state *state; 582 583 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL); 584 if (!state) 585 return NULL; 586 587 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); 588 589 return &state->base; 590 } 591 592 static void tegra_display_hub_destroy_state(struct drm_private_obj *obj, 593 struct drm_private_state *state) 594 { 595 struct tegra_display_hub_state *hub_state = 596 to_tegra_display_hub_state(state); 597 598 kfree(hub_state); 599 } 600 601 static const struct drm_private_state_funcs tegra_display_hub_state_funcs = { 602 .atomic_duplicate_state = tegra_display_hub_duplicate_state, 603 .atomic_destroy_state = tegra_display_hub_destroy_state, 604 }; 605 606 static struct tegra_display_hub_state * 607 tegra_display_hub_get_state(struct tegra_display_hub *hub, 608 struct drm_atomic_state *state) 609 { 610 struct drm_device *drm = dev_get_drvdata(hub->client.parent); 611 struct drm_private_state *priv; 612 613 WARN_ON(!drm_modeset_is_locked(&drm->mode_config.connection_mutex)); 614 615 priv = drm_atomic_get_private_obj_state(state, &hub->base); 616 if (IS_ERR(priv)) 617 return ERR_CAST(priv); 618 619 return to_tegra_display_hub_state(priv); 620 } 621 622 int tegra_display_hub_atomic_check(struct drm_device *drm, 623 struct drm_atomic_state *state) 624 { 625 struct tegra_drm *tegra = drm->dev_private; 626 struct tegra_display_hub_state *hub_state; 627 struct drm_crtc_state *old, *new; 628 struct drm_crtc *crtc; 629 unsigned int i; 630 631 if (!tegra->hub) 632 return 0; 633 634 hub_state = tegra_display_hub_get_state(tegra->hub, state); 635 if (IS_ERR(hub_state)) 636 return PTR_ERR(hub_state); 637 638 /* 639 * The display hub display clock needs to be fed by the display clock 640 * with the highest frequency to ensure proper functioning of all the 641 * displays. 642 * 643 * Note that this isn't used before Tegra186, but it doesn't hurt and 644 * conditionalizing it would make the code less clean. 645 */ 646 for_each_oldnew_crtc_in_state(state, crtc, old, new, i) { 647 struct tegra_dc_state *dc = to_dc_state(new); 648 649 if (new->active) { 650 if (!hub_state->clk || dc->pclk > hub_state->rate) { 651 hub_state->dc = to_tegra_dc(dc->base.crtc); 652 hub_state->clk = hub_state->dc->clk; 653 hub_state->rate = dc->pclk; 654 } 655 } 656 } 657 658 return 0; 659 } 660 661 static void tegra_display_hub_update(struct tegra_dc *dc) 662 { 663 u32 value; 664 665 pm_runtime_get_sync(dc->dev); 666 667 value = tegra_dc_readl(dc, DC_CMD_IHUB_COMMON_MISC_CTL); 668 value &= ~LATENCY_EVENT; 669 tegra_dc_writel(dc, value, DC_CMD_IHUB_COMMON_MISC_CTL); 670 671 value = tegra_dc_readl(dc, DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER); 672 value = CURS_SLOTS(1) | WGRP_SLOTS(1); 673 tegra_dc_writel(dc, value, DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER); 674 675 tegra_dc_writel(dc, COMMON_UPDATE, DC_CMD_STATE_CONTROL); 676 tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); 677 tegra_dc_writel(dc, COMMON_ACTREQ, DC_CMD_STATE_CONTROL); 678 tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); 679 680 pm_runtime_put(dc->dev); 681 } 682 683 void tegra_display_hub_atomic_commit(struct drm_device *drm, 684 struct drm_atomic_state *state) 685 { 686 struct tegra_drm *tegra = drm->dev_private; 687 struct tegra_display_hub *hub = tegra->hub; 688 struct tegra_display_hub_state *hub_state; 689 struct device *dev = hub->client.dev; 690 int err; 691 692 hub_state = to_tegra_display_hub_state(hub->base.state); 693 694 if (hub_state->clk) { 695 err = clk_set_rate(hub_state->clk, hub_state->rate); 696 if (err < 0) 697 dev_err(dev, "failed to set rate of %pC to %lu Hz\n", 698 hub_state->clk, hub_state->rate); 699 700 err = clk_set_parent(hub->clk_disp, hub_state->clk); 701 if (err < 0) 702 dev_err(dev, "failed to set parent of %pC to %pC: %d\n", 703 hub->clk_disp, hub_state->clk, err); 704 } 705 706 if (hub_state->dc) 707 tegra_display_hub_update(hub_state->dc); 708 } 709 710 static int tegra_display_hub_init(struct host1x_client *client) 711 { 712 struct tegra_display_hub *hub = to_tegra_display_hub(client); 713 struct drm_device *drm = dev_get_drvdata(client->parent); 714 struct tegra_drm *tegra = drm->dev_private; 715 struct tegra_display_hub_state *state; 716 717 state = kzalloc(sizeof(*state), GFP_KERNEL); 718 if (!state) 719 return -ENOMEM; 720 721 drm_atomic_private_obj_init(drm, &hub->base, &state->base, 722 &tegra_display_hub_state_funcs); 723 724 tegra->hub = hub; 725 726 return 0; 727 } 728 729 static int tegra_display_hub_exit(struct host1x_client *client) 730 { 731 struct drm_device *drm = dev_get_drvdata(client->parent); 732 struct tegra_drm *tegra = drm->dev_private; 733 734 drm_atomic_private_obj_fini(&tegra->hub->base); 735 tegra->hub = NULL; 736 737 return 0; 738 } 739 740 static const struct host1x_client_ops tegra_display_hub_ops = { 741 .init = tegra_display_hub_init, 742 .exit = tegra_display_hub_exit, 743 }; 744 745 static int tegra_display_hub_probe(struct platform_device *pdev) 746 { 747 struct device_node *child = NULL; 748 struct tegra_display_hub *hub; 749 struct clk *clk; 750 unsigned int i; 751 int err; 752 753 hub = devm_kzalloc(&pdev->dev, sizeof(*hub), GFP_KERNEL); 754 if (!hub) 755 return -ENOMEM; 756 757 hub->soc = of_device_get_match_data(&pdev->dev); 758 759 hub->clk_disp = devm_clk_get(&pdev->dev, "disp"); 760 if (IS_ERR(hub->clk_disp)) { 761 err = PTR_ERR(hub->clk_disp); 762 return err; 763 } 764 765 if (hub->soc->supports_dsc) { 766 hub->clk_dsc = devm_clk_get(&pdev->dev, "dsc"); 767 if (IS_ERR(hub->clk_dsc)) { 768 err = PTR_ERR(hub->clk_dsc); 769 return err; 770 } 771 } 772 773 hub->clk_hub = devm_clk_get(&pdev->dev, "hub"); 774 if (IS_ERR(hub->clk_hub)) { 775 err = PTR_ERR(hub->clk_hub); 776 return err; 777 } 778 779 hub->rst = devm_reset_control_get(&pdev->dev, "misc"); 780 if (IS_ERR(hub->rst)) { 781 err = PTR_ERR(hub->rst); 782 return err; 783 } 784 785 hub->wgrps = devm_kcalloc(&pdev->dev, hub->soc->num_wgrps, 786 sizeof(*hub->wgrps), GFP_KERNEL); 787 if (!hub->wgrps) 788 return -ENOMEM; 789 790 for (i = 0; i < hub->soc->num_wgrps; i++) { 791 struct tegra_windowgroup *wgrp = &hub->wgrps[i]; 792 char id[8]; 793 794 snprintf(id, sizeof(id), "wgrp%u", i); 795 mutex_init(&wgrp->lock); 796 wgrp->usecount = 0; 797 wgrp->index = i; 798 799 wgrp->rst = devm_reset_control_get(&pdev->dev, id); 800 if (IS_ERR(wgrp->rst)) 801 return PTR_ERR(wgrp->rst); 802 803 err = reset_control_assert(wgrp->rst); 804 if (err < 0) 805 return err; 806 } 807 808 hub->num_heads = of_get_child_count(pdev->dev.of_node); 809 810 hub->clk_heads = devm_kcalloc(&pdev->dev, hub->num_heads, sizeof(clk), 811 GFP_KERNEL); 812 if (!hub->clk_heads) 813 return -ENOMEM; 814 815 for (i = 0; i < hub->num_heads; i++) { 816 child = of_get_next_child(pdev->dev.of_node, child); 817 if (!child) { 818 dev_err(&pdev->dev, "failed to find node for head %u\n", 819 i); 820 return -ENODEV; 821 } 822 823 clk = devm_get_clk_from_child(&pdev->dev, child, "dc"); 824 if (IS_ERR(clk)) { 825 dev_err(&pdev->dev, "failed to get clock for head %u\n", 826 i); 827 of_node_put(child); 828 return PTR_ERR(clk); 829 } 830 831 hub->clk_heads[i] = clk; 832 } 833 834 of_node_put(child); 835 836 /* XXX: enable clock across reset? */ 837 err = reset_control_assert(hub->rst); 838 if (err < 0) 839 return err; 840 841 platform_set_drvdata(pdev, hub); 842 pm_runtime_enable(&pdev->dev); 843 844 INIT_LIST_HEAD(&hub->client.list); 845 hub->client.ops = &tegra_display_hub_ops; 846 hub->client.dev = &pdev->dev; 847 848 err = host1x_client_register(&hub->client); 849 if (err < 0) 850 dev_err(&pdev->dev, "failed to register host1x client: %d\n", 851 err); 852 853 return err; 854 } 855 856 static int tegra_display_hub_remove(struct platform_device *pdev) 857 { 858 struct tegra_display_hub *hub = platform_get_drvdata(pdev); 859 int err; 860 861 err = host1x_client_unregister(&hub->client); 862 if (err < 0) { 863 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", 864 err); 865 } 866 867 pm_runtime_disable(&pdev->dev); 868 869 return err; 870 } 871 872 static int __maybe_unused tegra_display_hub_suspend(struct device *dev) 873 { 874 struct tegra_display_hub *hub = dev_get_drvdata(dev); 875 unsigned int i = hub->num_heads; 876 int err; 877 878 err = reset_control_assert(hub->rst); 879 if (err < 0) 880 return err; 881 882 while (i--) 883 clk_disable_unprepare(hub->clk_heads[i]); 884 885 clk_disable_unprepare(hub->clk_hub); 886 clk_disable_unprepare(hub->clk_dsc); 887 clk_disable_unprepare(hub->clk_disp); 888 889 return 0; 890 } 891 892 static int __maybe_unused tegra_display_hub_resume(struct device *dev) 893 { 894 struct tegra_display_hub *hub = dev_get_drvdata(dev); 895 unsigned int i; 896 int err; 897 898 err = clk_prepare_enable(hub->clk_disp); 899 if (err < 0) 900 return err; 901 902 err = clk_prepare_enable(hub->clk_dsc); 903 if (err < 0) 904 goto disable_disp; 905 906 err = clk_prepare_enable(hub->clk_hub); 907 if (err < 0) 908 goto disable_dsc; 909 910 for (i = 0; i < hub->num_heads; i++) { 911 err = clk_prepare_enable(hub->clk_heads[i]); 912 if (err < 0) 913 goto disable_heads; 914 } 915 916 err = reset_control_deassert(hub->rst); 917 if (err < 0) 918 goto disable_heads; 919 920 return 0; 921 922 disable_heads: 923 while (i--) 924 clk_disable_unprepare(hub->clk_heads[i]); 925 926 clk_disable_unprepare(hub->clk_hub); 927 disable_dsc: 928 clk_disable_unprepare(hub->clk_dsc); 929 disable_disp: 930 clk_disable_unprepare(hub->clk_disp); 931 return err; 932 } 933 934 static const struct dev_pm_ops tegra_display_hub_pm_ops = { 935 SET_RUNTIME_PM_OPS(tegra_display_hub_suspend, 936 tegra_display_hub_resume, NULL) 937 }; 938 939 static const struct tegra_display_hub_soc tegra186_display_hub = { 940 .num_wgrps = 6, 941 .supports_dsc = true, 942 }; 943 944 static const struct tegra_display_hub_soc tegra194_display_hub = { 945 .num_wgrps = 6, 946 .supports_dsc = false, 947 }; 948 949 static const struct of_device_id tegra_display_hub_of_match[] = { 950 { 951 .compatible = "nvidia,tegra194-display", 952 .data = &tegra194_display_hub 953 }, { 954 .compatible = "nvidia,tegra186-display", 955 .data = &tegra186_display_hub 956 }, { 957 /* sentinel */ 958 } 959 }; 960 MODULE_DEVICE_TABLE(of, tegra_display_hub_of_match); 961 962 struct platform_driver tegra_display_hub_driver = { 963 .driver = { 964 .name = "tegra-display-hub", 965 .of_match_table = tegra_display_hub_of_match, 966 .pm = &tegra_display_hub_pm_ops, 967 }, 968 .probe = tegra_display_hub_probe, 969 .remove = tegra_display_hub_remove, 970 }; 971