1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 Avionic Design GmbH 4 * Copyright (C) 2013 NVIDIA Corporation 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/delay.h> 9 #include <linux/host1x.h> 10 #include <linux/iommu.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/platform_device.h> 14 #include <linux/pm_domain.h> 15 #include <linux/pm_opp.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/reset.h> 18 19 #include <soc/tegra/common.h> 20 #include <soc/tegra/pmc.h> 21 22 #include "drm.h" 23 #include "gem.h" 24 #include "gr3d.h" 25 26 enum { 27 RST_MC, 28 RST_GR3D, 29 RST_MC2, 30 RST_GR3D2, 31 RST_GR3D_MAX, 32 }; 33 34 struct gr3d_soc { 35 unsigned int version; 36 unsigned int num_clocks; 37 unsigned int num_resets; 38 }; 39 40 struct gr3d { 41 struct tegra_drm_client client; 42 struct host1x_channel *channel; 43 44 const struct gr3d_soc *soc; 45 struct clk_bulk_data *clocks; 46 unsigned int nclocks; 47 struct reset_control_bulk_data resets[RST_GR3D_MAX]; 48 unsigned int nresets; 49 struct dev_pm_domain_list *pd_list; 50 51 DECLARE_BITMAP(addr_regs, GR3D_NUM_REGS); 52 }; 53 54 static inline struct gr3d *to_gr3d(struct tegra_drm_client *client) 55 { 56 return container_of(client, struct gr3d, client); 57 } 58 59 static int gr3d_init(struct host1x_client *client) 60 { 61 struct tegra_drm_client *drm = host1x_to_drm_client(client); 62 struct drm_device *dev = dev_get_drvdata(client->host); 63 unsigned long flags = HOST1X_SYNCPT_HAS_BASE; 64 struct gr3d *gr3d = to_gr3d(drm); 65 int err; 66 67 gr3d->channel = host1x_channel_request(client); 68 if (!gr3d->channel) 69 return -ENOMEM; 70 71 client->syncpts[0] = host1x_syncpt_request(client, flags); 72 if (!client->syncpts[0]) { 73 err = -ENOMEM; 74 dev_err(client->dev, "failed to request syncpoint: %d\n", err); 75 goto put; 76 } 77 78 err = host1x_client_iommu_attach(client); 79 if (err < 0) { 80 dev_err(client->dev, "failed to attach to domain: %d\n", err); 81 goto free; 82 } 83 84 err = tegra_drm_register_client(dev->dev_private, drm); 85 if (err < 0) { 86 dev_err(client->dev, "failed to register client: %d\n", err); 87 goto detach_iommu; 88 } 89 90 return 0; 91 92 detach_iommu: 93 host1x_client_iommu_detach(client); 94 free: 95 host1x_syncpt_put(client->syncpts[0]); 96 put: 97 host1x_channel_put(gr3d->channel); 98 return err; 99 } 100 101 static int gr3d_exit(struct host1x_client *client) 102 { 103 struct tegra_drm_client *drm = host1x_to_drm_client(client); 104 struct drm_device *dev = dev_get_drvdata(client->host); 105 struct gr3d *gr3d = to_gr3d(drm); 106 int err; 107 108 err = tegra_drm_unregister_client(dev->dev_private, drm); 109 if (err < 0) 110 return err; 111 112 pm_runtime_dont_use_autosuspend(client->dev); 113 pm_runtime_force_suspend(client->dev); 114 115 host1x_client_iommu_detach(client); 116 host1x_syncpt_put(client->syncpts[0]); 117 host1x_channel_put(gr3d->channel); 118 119 gr3d->channel = NULL; 120 121 return 0; 122 } 123 124 static const struct host1x_client_ops gr3d_client_ops = { 125 .init = gr3d_init, 126 .exit = gr3d_exit, 127 }; 128 129 static int gr3d_open_channel(struct tegra_drm_client *client, 130 struct tegra_drm_context *context) 131 { 132 struct gr3d *gr3d = to_gr3d(client); 133 134 context->channel = host1x_channel_get(gr3d->channel); 135 if (!context->channel) 136 return -ENOMEM; 137 138 return 0; 139 } 140 141 static void gr3d_close_channel(struct tegra_drm_context *context) 142 { 143 host1x_channel_put(context->channel); 144 } 145 146 static int gr3d_is_addr_reg(struct device *dev, u32 class, u32 offset) 147 { 148 struct gr3d *gr3d = dev_get_drvdata(dev); 149 150 switch (class) { 151 case HOST1X_CLASS_HOST1X: 152 if (offset == 0x2b) 153 return 1; 154 155 break; 156 157 case HOST1X_CLASS_GR3D: 158 if (offset >= GR3D_NUM_REGS) 159 break; 160 161 if (test_bit(offset, gr3d->addr_regs)) 162 return 1; 163 164 break; 165 } 166 167 return 0; 168 } 169 170 static const struct tegra_drm_client_ops gr3d_ops = { 171 .open_channel = gr3d_open_channel, 172 .close_channel = gr3d_close_channel, 173 .is_addr_reg = gr3d_is_addr_reg, 174 .submit = tegra_drm_submit, 175 }; 176 177 static const struct gr3d_soc tegra20_gr3d_soc = { 178 .version = 0x20, 179 .num_clocks = 1, 180 .num_resets = 2, 181 }; 182 183 static const struct gr3d_soc tegra30_gr3d_soc = { 184 .version = 0x30, 185 .num_clocks = 2, 186 .num_resets = 4, 187 }; 188 189 static const struct gr3d_soc tegra114_gr3d_soc = { 190 .version = 0x35, 191 .num_clocks = 1, 192 .num_resets = 2, 193 }; 194 195 static const struct of_device_id tegra_gr3d_match[] = { 196 { .compatible = "nvidia,tegra114-gr3d", .data = &tegra114_gr3d_soc }, 197 { .compatible = "nvidia,tegra30-gr3d", .data = &tegra30_gr3d_soc }, 198 { .compatible = "nvidia,tegra20-gr3d", .data = &tegra20_gr3d_soc }, 199 { } 200 }; 201 MODULE_DEVICE_TABLE(of, tegra_gr3d_match); 202 203 static const u32 gr3d_addr_regs[] = { 204 GR3D_IDX_ATTRIBUTE( 0), 205 GR3D_IDX_ATTRIBUTE( 1), 206 GR3D_IDX_ATTRIBUTE( 2), 207 GR3D_IDX_ATTRIBUTE( 3), 208 GR3D_IDX_ATTRIBUTE( 4), 209 GR3D_IDX_ATTRIBUTE( 5), 210 GR3D_IDX_ATTRIBUTE( 6), 211 GR3D_IDX_ATTRIBUTE( 7), 212 GR3D_IDX_ATTRIBUTE( 8), 213 GR3D_IDX_ATTRIBUTE( 9), 214 GR3D_IDX_ATTRIBUTE(10), 215 GR3D_IDX_ATTRIBUTE(11), 216 GR3D_IDX_ATTRIBUTE(12), 217 GR3D_IDX_ATTRIBUTE(13), 218 GR3D_IDX_ATTRIBUTE(14), 219 GR3D_IDX_ATTRIBUTE(15), 220 GR3D_IDX_INDEX_BASE, 221 GR3D_QR_ZTAG_ADDR, 222 GR3D_QR_CTAG_ADDR, 223 GR3D_QR_CZ_ADDR, 224 GR3D_TEX_TEX_ADDR( 0), 225 GR3D_TEX_TEX_ADDR( 1), 226 GR3D_TEX_TEX_ADDR( 2), 227 GR3D_TEX_TEX_ADDR( 3), 228 GR3D_TEX_TEX_ADDR( 4), 229 GR3D_TEX_TEX_ADDR( 5), 230 GR3D_TEX_TEX_ADDR( 6), 231 GR3D_TEX_TEX_ADDR( 7), 232 GR3D_TEX_TEX_ADDR( 8), 233 GR3D_TEX_TEX_ADDR( 9), 234 GR3D_TEX_TEX_ADDR(10), 235 GR3D_TEX_TEX_ADDR(11), 236 GR3D_TEX_TEX_ADDR(12), 237 GR3D_TEX_TEX_ADDR(13), 238 GR3D_TEX_TEX_ADDR(14), 239 GR3D_TEX_TEX_ADDR(15), 240 GR3D_DW_MEMORY_OUTPUT_ADDRESS, 241 GR3D_GLOBAL_SURFADDR( 0), 242 GR3D_GLOBAL_SURFADDR( 1), 243 GR3D_GLOBAL_SURFADDR( 2), 244 GR3D_GLOBAL_SURFADDR( 3), 245 GR3D_GLOBAL_SURFADDR( 4), 246 GR3D_GLOBAL_SURFADDR( 5), 247 GR3D_GLOBAL_SURFADDR( 6), 248 GR3D_GLOBAL_SURFADDR( 7), 249 GR3D_GLOBAL_SURFADDR( 8), 250 GR3D_GLOBAL_SURFADDR( 9), 251 GR3D_GLOBAL_SURFADDR(10), 252 GR3D_GLOBAL_SURFADDR(11), 253 GR3D_GLOBAL_SURFADDR(12), 254 GR3D_GLOBAL_SURFADDR(13), 255 GR3D_GLOBAL_SURFADDR(14), 256 GR3D_GLOBAL_SURFADDR(15), 257 GR3D_GLOBAL_SPILLSURFADDR, 258 GR3D_GLOBAL_SURFOVERADDR( 0), 259 GR3D_GLOBAL_SURFOVERADDR( 1), 260 GR3D_GLOBAL_SURFOVERADDR( 2), 261 GR3D_GLOBAL_SURFOVERADDR( 3), 262 GR3D_GLOBAL_SURFOVERADDR( 4), 263 GR3D_GLOBAL_SURFOVERADDR( 5), 264 GR3D_GLOBAL_SURFOVERADDR( 6), 265 GR3D_GLOBAL_SURFOVERADDR( 7), 266 GR3D_GLOBAL_SURFOVERADDR( 8), 267 GR3D_GLOBAL_SURFOVERADDR( 9), 268 GR3D_GLOBAL_SURFOVERADDR(10), 269 GR3D_GLOBAL_SURFOVERADDR(11), 270 GR3D_GLOBAL_SURFOVERADDR(12), 271 GR3D_GLOBAL_SURFOVERADDR(13), 272 GR3D_GLOBAL_SURFOVERADDR(14), 273 GR3D_GLOBAL_SURFOVERADDR(15), 274 GR3D_GLOBAL_SAMP01SURFADDR( 0), 275 GR3D_GLOBAL_SAMP01SURFADDR( 1), 276 GR3D_GLOBAL_SAMP01SURFADDR( 2), 277 GR3D_GLOBAL_SAMP01SURFADDR( 3), 278 GR3D_GLOBAL_SAMP01SURFADDR( 4), 279 GR3D_GLOBAL_SAMP01SURFADDR( 5), 280 GR3D_GLOBAL_SAMP01SURFADDR( 6), 281 GR3D_GLOBAL_SAMP01SURFADDR( 7), 282 GR3D_GLOBAL_SAMP01SURFADDR( 8), 283 GR3D_GLOBAL_SAMP01SURFADDR( 9), 284 GR3D_GLOBAL_SAMP01SURFADDR(10), 285 GR3D_GLOBAL_SAMP01SURFADDR(11), 286 GR3D_GLOBAL_SAMP01SURFADDR(12), 287 GR3D_GLOBAL_SAMP01SURFADDR(13), 288 GR3D_GLOBAL_SAMP01SURFADDR(14), 289 GR3D_GLOBAL_SAMP01SURFADDR(15), 290 GR3D_GLOBAL_SAMP23SURFADDR( 0), 291 GR3D_GLOBAL_SAMP23SURFADDR( 1), 292 GR3D_GLOBAL_SAMP23SURFADDR( 2), 293 GR3D_GLOBAL_SAMP23SURFADDR( 3), 294 GR3D_GLOBAL_SAMP23SURFADDR( 4), 295 GR3D_GLOBAL_SAMP23SURFADDR( 5), 296 GR3D_GLOBAL_SAMP23SURFADDR( 6), 297 GR3D_GLOBAL_SAMP23SURFADDR( 7), 298 GR3D_GLOBAL_SAMP23SURFADDR( 8), 299 GR3D_GLOBAL_SAMP23SURFADDR( 9), 300 GR3D_GLOBAL_SAMP23SURFADDR(10), 301 GR3D_GLOBAL_SAMP23SURFADDR(11), 302 GR3D_GLOBAL_SAMP23SURFADDR(12), 303 GR3D_GLOBAL_SAMP23SURFADDR(13), 304 GR3D_GLOBAL_SAMP23SURFADDR(14), 305 GR3D_GLOBAL_SAMP23SURFADDR(15), 306 }; 307 308 static int gr3d_power_up_legacy_domain(struct device *dev, const char *name, 309 unsigned int id) 310 { 311 struct gr3d *gr3d = dev_get_drvdata(dev); 312 struct reset_control *reset; 313 struct clk *clk; 314 unsigned int i; 315 int err; 316 317 /* 318 * Tegra20 device-tree doesn't specify 3d clock name and there is only 319 * one clock for Tegra20. Tegra30+ device-trees always specified names 320 * for the clocks. 321 */ 322 if (gr3d->nclocks == 1) { 323 if (id == TEGRA_POWERGATE_3D1) 324 return 0; 325 326 clk = gr3d->clocks[0].clk; 327 } else { 328 for (i = 0; i < gr3d->nclocks; i++) { 329 if (WARN_ON(!gr3d->clocks[i].id)) 330 continue; 331 332 if (!strcmp(gr3d->clocks[i].id, name)) { 333 clk = gr3d->clocks[i].clk; 334 break; 335 } 336 } 337 338 if (WARN_ON(i == gr3d->nclocks)) 339 return -EINVAL; 340 } 341 342 /* 343 * We use array of resets, which includes MC resets, and MC 344 * reset shouldn't be asserted while hardware is gated because 345 * MC flushing will fail for gated hardware. Hence for legacy 346 * PD we request the individual reset separately. 347 */ 348 reset = reset_control_get_exclusive_released(dev, name); 349 if (IS_ERR(reset)) 350 return PTR_ERR(reset); 351 352 err = reset_control_acquire(reset); 353 if (err) { 354 dev_err(dev, "failed to acquire %s reset: %d\n", name, err); 355 } else { 356 err = tegra_powergate_sequence_power_up(id, clk, reset); 357 reset_control_release(reset); 358 } 359 360 reset_control_put(reset); 361 if (err) 362 return err; 363 364 /* 365 * tegra_powergate_sequence_power_up() leaves clocks enabled, 366 * while GENPD not. Hence keep clock-enable balanced. 367 */ 368 clk_disable_unprepare(clk); 369 370 return 0; 371 } 372 373 static int gr3d_init_power(struct device *dev, struct gr3d *gr3d) 374 { 375 struct dev_pm_domain_attach_data pd_data = { 376 .pd_names = (const char *[]) { "3d0", "3d1" }, 377 .num_pd_names = 2, 378 }; 379 int err; 380 381 err = of_count_phandle_with_args(dev->of_node, "power-domains", 382 "#power-domain-cells"); 383 if (err < 0) { 384 if (err != -ENOENT) 385 return err; 386 387 /* 388 * Older device-trees don't use GENPD. In this case we should 389 * toggle power domain manually. 390 */ 391 err = gr3d_power_up_legacy_domain(dev, "3d", 392 TEGRA_POWERGATE_3D); 393 if (err) 394 return err; 395 396 err = gr3d_power_up_legacy_domain(dev, "3d2", 397 TEGRA_POWERGATE_3D1); 398 if (err) 399 return err; 400 401 return 0; 402 } 403 404 /* 405 * The PM domain core automatically attaches a single power domain, 406 * otherwise it skips attaching completely. We have a single domain 407 * on Tegra20 and two domains on Tegra30+. 408 */ 409 if (dev->pm_domain) 410 return 0; 411 412 err = dev_pm_domain_attach_list(dev, &pd_data, &gr3d->pd_list); 413 if (err < 0) 414 return err; 415 416 return 0; 417 } 418 419 static int gr3d_get_clocks(struct device *dev, struct gr3d *gr3d) 420 { 421 int err; 422 423 err = devm_clk_bulk_get_all(dev, &gr3d->clocks); 424 if (err < 0) { 425 dev_err(dev, "failed to get clock: %d\n", err); 426 return err; 427 } 428 gr3d->nclocks = err; 429 430 if (gr3d->nclocks != gr3d->soc->num_clocks) { 431 dev_err(dev, "invalid number of clocks: %u\n", gr3d->nclocks); 432 return -ENOENT; 433 } 434 435 return 0; 436 } 437 438 static int gr3d_get_resets(struct device *dev, struct gr3d *gr3d) 439 { 440 int err; 441 442 gr3d->resets[RST_MC].id = "mc"; 443 gr3d->resets[RST_MC2].id = "mc2"; 444 gr3d->resets[RST_GR3D].id = "3d"; 445 gr3d->resets[RST_GR3D2].id = "3d2"; 446 gr3d->nresets = gr3d->soc->num_resets; 447 448 err = devm_reset_control_bulk_get_optional_exclusive_released( 449 dev, gr3d->nresets, gr3d->resets); 450 if (err) { 451 dev_err(dev, "failed to get reset: %d\n", err); 452 return err; 453 } 454 455 if (WARN_ON(!gr3d->resets[RST_GR3D].rstc) || 456 WARN_ON(!gr3d->resets[RST_GR3D2].rstc && gr3d->nresets == 4)) 457 return -ENOENT; 458 459 return 0; 460 } 461 462 static int gr3d_probe(struct platform_device *pdev) 463 { 464 struct host1x_syncpt **syncpts; 465 struct gr3d *gr3d; 466 unsigned int i; 467 int err; 468 469 gr3d = devm_kzalloc(&pdev->dev, sizeof(*gr3d), GFP_KERNEL); 470 if (!gr3d) 471 return -ENOMEM; 472 473 platform_set_drvdata(pdev, gr3d); 474 475 gr3d->soc = of_device_get_match_data(&pdev->dev); 476 477 syncpts = devm_kzalloc(&pdev->dev, sizeof(*syncpts), GFP_KERNEL); 478 if (!syncpts) 479 return -ENOMEM; 480 481 err = gr3d_get_clocks(&pdev->dev, gr3d); 482 if (err) 483 return err; 484 485 err = gr3d_get_resets(&pdev->dev, gr3d); 486 if (err) 487 return err; 488 489 err = gr3d_init_power(&pdev->dev, gr3d); 490 if (err) 491 return err; 492 493 INIT_LIST_HEAD(&gr3d->client.base.list); 494 gr3d->client.base.ops = &gr3d_client_ops; 495 gr3d->client.base.dev = &pdev->dev; 496 gr3d->client.base.class = HOST1X_CLASS_GR3D; 497 gr3d->client.base.syncpts = syncpts; 498 gr3d->client.base.num_syncpts = 1; 499 500 INIT_LIST_HEAD(&gr3d->client.list); 501 gr3d->client.version = gr3d->soc->version; 502 gr3d->client.ops = &gr3d_ops; 503 504 err = devm_tegra_core_dev_init_opp_table_common(&pdev->dev); 505 if (err) 506 goto err; 507 508 err = host1x_client_register(&gr3d->client.base); 509 if (err < 0) { 510 dev_err(&pdev->dev, "failed to register host1x client: %d\n", 511 err); 512 goto err; 513 } 514 515 /* initialize address register map */ 516 for (i = 0; i < ARRAY_SIZE(gr3d_addr_regs); i++) 517 set_bit(gr3d_addr_regs[i], gr3d->addr_regs); 518 519 return 0; 520 err: 521 dev_pm_domain_detach_list(gr3d->pd_list); 522 return err; 523 } 524 525 static void gr3d_remove(struct platform_device *pdev) 526 { 527 struct gr3d *gr3d = platform_get_drvdata(pdev); 528 529 pm_runtime_disable(&pdev->dev); 530 host1x_client_unregister(&gr3d->client.base); 531 dev_pm_domain_detach_list(gr3d->pd_list); 532 } 533 534 static int __maybe_unused gr3d_runtime_suspend(struct device *dev) 535 { 536 struct gr3d *gr3d = dev_get_drvdata(dev); 537 int err; 538 539 host1x_channel_stop(gr3d->channel); 540 541 err = reset_control_bulk_assert(gr3d->nresets, gr3d->resets); 542 if (err) { 543 dev_err(dev, "failed to assert reset: %d\n", err); 544 return err; 545 } 546 547 usleep_range(10, 20); 548 549 /* 550 * Older device-trees don't specify MC resets and power-gating can't 551 * be done safely in that case. Hence we will keep the power ungated 552 * for older DTBs. For newer DTBs, GENPD will perform the power-gating. 553 */ 554 555 clk_bulk_disable_unprepare(gr3d->nclocks, gr3d->clocks); 556 reset_control_bulk_release(gr3d->nresets, gr3d->resets); 557 558 return 0; 559 } 560 561 static int __maybe_unused gr3d_runtime_resume(struct device *dev) 562 { 563 struct gr3d *gr3d = dev_get_drvdata(dev); 564 int err; 565 566 err = reset_control_bulk_acquire(gr3d->nresets, gr3d->resets); 567 if (err) { 568 dev_err(dev, "failed to acquire reset: %d\n", err); 569 return err; 570 } 571 572 err = clk_bulk_prepare_enable(gr3d->nclocks, gr3d->clocks); 573 if (err) { 574 dev_err(dev, "failed to enable clock: %d\n", err); 575 goto release_reset; 576 } 577 578 err = reset_control_bulk_deassert(gr3d->nresets, gr3d->resets); 579 if (err) { 580 dev_err(dev, "failed to deassert reset: %d\n", err); 581 goto disable_clk; 582 } 583 584 pm_runtime_enable(dev); 585 pm_runtime_use_autosuspend(dev); 586 pm_runtime_set_autosuspend_delay(dev, 500); 587 588 return 0; 589 590 disable_clk: 591 clk_bulk_disable_unprepare(gr3d->nclocks, gr3d->clocks); 592 release_reset: 593 reset_control_bulk_release(gr3d->nresets, gr3d->resets); 594 595 return err; 596 } 597 598 static const struct dev_pm_ops tegra_gr3d_pm = { 599 SET_RUNTIME_PM_OPS(gr3d_runtime_suspend, gr3d_runtime_resume, NULL) 600 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 601 pm_runtime_force_resume) 602 }; 603 604 struct platform_driver tegra_gr3d_driver = { 605 .driver = { 606 .name = "tegra-gr3d", 607 .of_match_table = tegra_gr3d_match, 608 .pm = &tegra_gr3d_pm, 609 }, 610 .probe = gr3d_probe, 611 .remove_new = gr3d_remove, 612 }; 613