1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 Avionic Design GmbH 4 * Copyright (C) 2013 NVIDIA Corporation 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/delay.h> 9 #include <linux/host1x.h> 10 #include <linux/iommu.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/platform_device.h> 14 #include <linux/pm_domain.h> 15 #include <linux/pm_opp.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/reset.h> 18 19 #include <soc/tegra/common.h> 20 #include <soc/tegra/pmc.h> 21 22 #include "drm.h" 23 #include "gem.h" 24 #include "gr3d.h" 25 26 enum { 27 RST_MC, 28 RST_GR3D, 29 RST_MC2, 30 RST_GR3D2, 31 RST_GR3D_MAX, 32 }; 33 34 struct gr3d_soc { 35 unsigned int version; 36 unsigned int num_clocks; 37 unsigned int num_resets; 38 }; 39 40 struct gr3d { 41 struct tegra_drm_client client; 42 struct host1x_channel *channel; 43 44 const struct gr3d_soc *soc; 45 struct clk_bulk_data *clocks; 46 unsigned int nclocks; 47 struct reset_control_bulk_data resets[RST_GR3D_MAX]; 48 unsigned int nresets; 49 struct dev_pm_domain_list *pd_list; 50 51 DECLARE_BITMAP(addr_regs, GR3D_NUM_REGS); 52 }; 53 54 static inline struct gr3d *to_gr3d(struct tegra_drm_client *client) 55 { 56 return container_of(client, struct gr3d, client); 57 } 58 59 static int gr3d_init(struct host1x_client *client) 60 { 61 struct tegra_drm_client *drm = host1x_to_drm_client(client); 62 struct drm_device *dev = dev_get_drvdata(client->host); 63 unsigned long flags = HOST1X_SYNCPT_HAS_BASE; 64 struct gr3d *gr3d = to_gr3d(drm); 65 int err; 66 67 gr3d->channel = host1x_channel_request(client); 68 if (!gr3d->channel) 69 return -ENOMEM; 70 71 client->syncpts[0] = host1x_syncpt_request(client, flags); 72 if (!client->syncpts[0]) { 73 err = -ENOMEM; 74 dev_err(client->dev, "failed to request syncpoint: %d\n", err); 75 goto put; 76 } 77 78 err = host1x_client_iommu_attach(client); 79 if (err < 0) { 80 dev_err(client->dev, "failed to attach to domain: %d\n", err); 81 goto free; 82 } 83 84 err = tegra_drm_register_client(dev->dev_private, drm); 85 if (err < 0) { 86 dev_err(client->dev, "failed to register client: %d\n", err); 87 goto detach_iommu; 88 } 89 90 return 0; 91 92 detach_iommu: 93 host1x_client_iommu_detach(client); 94 free: 95 host1x_syncpt_put(client->syncpts[0]); 96 put: 97 host1x_channel_put(gr3d->channel); 98 return err; 99 } 100 101 static int gr3d_exit(struct host1x_client *client) 102 { 103 struct tegra_drm_client *drm = host1x_to_drm_client(client); 104 struct drm_device *dev = dev_get_drvdata(client->host); 105 struct gr3d *gr3d = to_gr3d(drm); 106 int err; 107 108 err = tegra_drm_unregister_client(dev->dev_private, drm); 109 if (err < 0) 110 return err; 111 112 host1x_client_iommu_detach(client); 113 host1x_syncpt_put(client->syncpts[0]); 114 host1x_channel_put(gr3d->channel); 115 116 gr3d->channel = NULL; 117 118 return 0; 119 } 120 121 static const struct host1x_client_ops gr3d_client_ops = { 122 .init = gr3d_init, 123 .exit = gr3d_exit, 124 }; 125 126 static int gr3d_open_channel(struct tegra_drm_client *client, 127 struct tegra_drm_context *context) 128 { 129 struct gr3d *gr3d = to_gr3d(client); 130 131 context->channel = host1x_channel_get(gr3d->channel); 132 if (!context->channel) 133 return -ENOMEM; 134 135 return 0; 136 } 137 138 static void gr3d_close_channel(struct tegra_drm_context *context) 139 { 140 host1x_channel_put(context->channel); 141 } 142 143 static int gr3d_is_addr_reg(struct device *dev, u32 class, u32 offset) 144 { 145 struct gr3d *gr3d = dev_get_drvdata(dev); 146 147 switch (class) { 148 case HOST1X_CLASS_HOST1X: 149 if (offset == 0x2b) 150 return 1; 151 152 break; 153 154 case HOST1X_CLASS_GR3D: 155 if (offset >= GR3D_NUM_REGS) 156 break; 157 158 if (test_bit(offset, gr3d->addr_regs)) 159 return 1; 160 161 break; 162 } 163 164 return 0; 165 } 166 167 static const struct tegra_drm_client_ops gr3d_ops = { 168 .open_channel = gr3d_open_channel, 169 .close_channel = gr3d_close_channel, 170 .is_addr_reg = gr3d_is_addr_reg, 171 .submit = tegra_drm_submit, 172 }; 173 174 static const struct gr3d_soc tegra20_gr3d_soc = { 175 .version = 0x20, 176 .num_clocks = 1, 177 .num_resets = 2, 178 }; 179 180 static const struct gr3d_soc tegra30_gr3d_soc = { 181 .version = 0x30, 182 .num_clocks = 2, 183 .num_resets = 4, 184 }; 185 186 static const struct gr3d_soc tegra114_gr3d_soc = { 187 .version = 0x35, 188 .num_clocks = 1, 189 .num_resets = 2, 190 }; 191 192 static const struct of_device_id tegra_gr3d_match[] = { 193 { .compatible = "nvidia,tegra114-gr3d", .data = &tegra114_gr3d_soc }, 194 { .compatible = "nvidia,tegra30-gr3d", .data = &tegra30_gr3d_soc }, 195 { .compatible = "nvidia,tegra20-gr3d", .data = &tegra20_gr3d_soc }, 196 { } 197 }; 198 MODULE_DEVICE_TABLE(of, tegra_gr3d_match); 199 200 static const u32 gr3d_addr_regs[] = { 201 GR3D_IDX_ATTRIBUTE( 0), 202 GR3D_IDX_ATTRIBUTE( 1), 203 GR3D_IDX_ATTRIBUTE( 2), 204 GR3D_IDX_ATTRIBUTE( 3), 205 GR3D_IDX_ATTRIBUTE( 4), 206 GR3D_IDX_ATTRIBUTE( 5), 207 GR3D_IDX_ATTRIBUTE( 6), 208 GR3D_IDX_ATTRIBUTE( 7), 209 GR3D_IDX_ATTRIBUTE( 8), 210 GR3D_IDX_ATTRIBUTE( 9), 211 GR3D_IDX_ATTRIBUTE(10), 212 GR3D_IDX_ATTRIBUTE(11), 213 GR3D_IDX_ATTRIBUTE(12), 214 GR3D_IDX_ATTRIBUTE(13), 215 GR3D_IDX_ATTRIBUTE(14), 216 GR3D_IDX_ATTRIBUTE(15), 217 GR3D_IDX_INDEX_BASE, 218 GR3D_QR_ZTAG_ADDR, 219 GR3D_QR_CTAG_ADDR, 220 GR3D_QR_CZ_ADDR, 221 GR3D_TEX_TEX_ADDR( 0), 222 GR3D_TEX_TEX_ADDR( 1), 223 GR3D_TEX_TEX_ADDR( 2), 224 GR3D_TEX_TEX_ADDR( 3), 225 GR3D_TEX_TEX_ADDR( 4), 226 GR3D_TEX_TEX_ADDR( 5), 227 GR3D_TEX_TEX_ADDR( 6), 228 GR3D_TEX_TEX_ADDR( 7), 229 GR3D_TEX_TEX_ADDR( 8), 230 GR3D_TEX_TEX_ADDR( 9), 231 GR3D_TEX_TEX_ADDR(10), 232 GR3D_TEX_TEX_ADDR(11), 233 GR3D_TEX_TEX_ADDR(12), 234 GR3D_TEX_TEX_ADDR(13), 235 GR3D_TEX_TEX_ADDR(14), 236 GR3D_TEX_TEX_ADDR(15), 237 GR3D_DW_MEMORY_OUTPUT_ADDRESS, 238 GR3D_GLOBAL_SURFADDR( 0), 239 GR3D_GLOBAL_SURFADDR( 1), 240 GR3D_GLOBAL_SURFADDR( 2), 241 GR3D_GLOBAL_SURFADDR( 3), 242 GR3D_GLOBAL_SURFADDR( 4), 243 GR3D_GLOBAL_SURFADDR( 5), 244 GR3D_GLOBAL_SURFADDR( 6), 245 GR3D_GLOBAL_SURFADDR( 7), 246 GR3D_GLOBAL_SURFADDR( 8), 247 GR3D_GLOBAL_SURFADDR( 9), 248 GR3D_GLOBAL_SURFADDR(10), 249 GR3D_GLOBAL_SURFADDR(11), 250 GR3D_GLOBAL_SURFADDR(12), 251 GR3D_GLOBAL_SURFADDR(13), 252 GR3D_GLOBAL_SURFADDR(14), 253 GR3D_GLOBAL_SURFADDR(15), 254 GR3D_GLOBAL_SPILLSURFADDR, 255 GR3D_GLOBAL_SURFOVERADDR( 0), 256 GR3D_GLOBAL_SURFOVERADDR( 1), 257 GR3D_GLOBAL_SURFOVERADDR( 2), 258 GR3D_GLOBAL_SURFOVERADDR( 3), 259 GR3D_GLOBAL_SURFOVERADDR( 4), 260 GR3D_GLOBAL_SURFOVERADDR( 5), 261 GR3D_GLOBAL_SURFOVERADDR( 6), 262 GR3D_GLOBAL_SURFOVERADDR( 7), 263 GR3D_GLOBAL_SURFOVERADDR( 8), 264 GR3D_GLOBAL_SURFOVERADDR( 9), 265 GR3D_GLOBAL_SURFOVERADDR(10), 266 GR3D_GLOBAL_SURFOVERADDR(11), 267 GR3D_GLOBAL_SURFOVERADDR(12), 268 GR3D_GLOBAL_SURFOVERADDR(13), 269 GR3D_GLOBAL_SURFOVERADDR(14), 270 GR3D_GLOBAL_SURFOVERADDR(15), 271 GR3D_GLOBAL_SAMP01SURFADDR( 0), 272 GR3D_GLOBAL_SAMP01SURFADDR( 1), 273 GR3D_GLOBAL_SAMP01SURFADDR( 2), 274 GR3D_GLOBAL_SAMP01SURFADDR( 3), 275 GR3D_GLOBAL_SAMP01SURFADDR( 4), 276 GR3D_GLOBAL_SAMP01SURFADDR( 5), 277 GR3D_GLOBAL_SAMP01SURFADDR( 6), 278 GR3D_GLOBAL_SAMP01SURFADDR( 7), 279 GR3D_GLOBAL_SAMP01SURFADDR( 8), 280 GR3D_GLOBAL_SAMP01SURFADDR( 9), 281 GR3D_GLOBAL_SAMP01SURFADDR(10), 282 GR3D_GLOBAL_SAMP01SURFADDR(11), 283 GR3D_GLOBAL_SAMP01SURFADDR(12), 284 GR3D_GLOBAL_SAMP01SURFADDR(13), 285 GR3D_GLOBAL_SAMP01SURFADDR(14), 286 GR3D_GLOBAL_SAMP01SURFADDR(15), 287 GR3D_GLOBAL_SAMP23SURFADDR( 0), 288 GR3D_GLOBAL_SAMP23SURFADDR( 1), 289 GR3D_GLOBAL_SAMP23SURFADDR( 2), 290 GR3D_GLOBAL_SAMP23SURFADDR( 3), 291 GR3D_GLOBAL_SAMP23SURFADDR( 4), 292 GR3D_GLOBAL_SAMP23SURFADDR( 5), 293 GR3D_GLOBAL_SAMP23SURFADDR( 6), 294 GR3D_GLOBAL_SAMP23SURFADDR( 7), 295 GR3D_GLOBAL_SAMP23SURFADDR( 8), 296 GR3D_GLOBAL_SAMP23SURFADDR( 9), 297 GR3D_GLOBAL_SAMP23SURFADDR(10), 298 GR3D_GLOBAL_SAMP23SURFADDR(11), 299 GR3D_GLOBAL_SAMP23SURFADDR(12), 300 GR3D_GLOBAL_SAMP23SURFADDR(13), 301 GR3D_GLOBAL_SAMP23SURFADDR(14), 302 GR3D_GLOBAL_SAMP23SURFADDR(15), 303 }; 304 305 static int gr3d_power_up_legacy_domain(struct device *dev, const char *name, 306 unsigned int id) 307 { 308 struct gr3d *gr3d = dev_get_drvdata(dev); 309 struct reset_control *reset; 310 struct clk *clk; 311 unsigned int i; 312 int err; 313 314 /* 315 * Tegra20 device-tree doesn't specify 3d clock name and there is only 316 * one clock for Tegra20. Tegra30+ device-trees always specified names 317 * for the clocks. 318 */ 319 if (gr3d->nclocks == 1) { 320 if (id == TEGRA_POWERGATE_3D1) 321 return 0; 322 323 clk = gr3d->clocks[0].clk; 324 } else { 325 for (i = 0; i < gr3d->nclocks; i++) { 326 if (WARN_ON(!gr3d->clocks[i].id)) 327 continue; 328 329 if (!strcmp(gr3d->clocks[i].id, name)) { 330 clk = gr3d->clocks[i].clk; 331 break; 332 } 333 } 334 335 if (WARN_ON(i == gr3d->nclocks)) 336 return -EINVAL; 337 } 338 339 /* 340 * We use array of resets, which includes MC resets, and MC 341 * reset shouldn't be asserted while hardware is gated because 342 * MC flushing will fail for gated hardware. Hence for legacy 343 * PD we request the individual reset separately. 344 */ 345 reset = reset_control_get_exclusive_released(dev, name); 346 if (IS_ERR(reset)) 347 return PTR_ERR(reset); 348 349 err = reset_control_acquire(reset); 350 if (err) { 351 dev_err(dev, "failed to acquire %s reset: %d\n", name, err); 352 } else { 353 err = tegra_powergate_sequence_power_up(id, clk, reset); 354 reset_control_release(reset); 355 } 356 357 reset_control_put(reset); 358 if (err) 359 return err; 360 361 /* 362 * tegra_powergate_sequence_power_up() leaves clocks enabled, 363 * while GENPD not. Hence keep clock-enable balanced. 364 */ 365 clk_disable_unprepare(clk); 366 367 return 0; 368 } 369 370 static int gr3d_init_power(struct device *dev, struct gr3d *gr3d) 371 { 372 struct dev_pm_domain_attach_data pd_data = { 373 .pd_names = (const char *[]) { "3d0", "3d1" }, 374 .num_pd_names = 2, 375 .pd_flags = PD_FLAG_REQUIRED_OPP, 376 }; 377 int err; 378 379 err = of_count_phandle_with_args(dev->of_node, "power-domains", 380 "#power-domain-cells"); 381 if (err < 0) { 382 if (err != -ENOENT) 383 return err; 384 385 /* 386 * Older device-trees don't use GENPD. In this case we should 387 * toggle power domain manually. 388 */ 389 err = gr3d_power_up_legacy_domain(dev, "3d", 390 TEGRA_POWERGATE_3D); 391 if (err) 392 return err; 393 394 err = gr3d_power_up_legacy_domain(dev, "3d2", 395 TEGRA_POWERGATE_3D1); 396 if (err) 397 return err; 398 399 return 0; 400 } 401 402 /* 403 * The PM domain core automatically attaches a single power domain, 404 * otherwise it skips attaching completely. We have a single domain 405 * on Tegra20 and two domains on Tegra30+. 406 */ 407 if (dev->pm_domain) 408 return 0; 409 410 err = devm_pm_domain_attach_list(dev, &pd_data, &gr3d->pd_list); 411 if (err < 0) 412 return err; 413 414 return 0; 415 } 416 417 static int gr3d_get_clocks(struct device *dev, struct gr3d *gr3d) 418 { 419 int err; 420 421 err = devm_clk_bulk_get_all(dev, &gr3d->clocks); 422 if (err < 0) { 423 dev_err(dev, "failed to get clock: %d\n", err); 424 return err; 425 } 426 gr3d->nclocks = err; 427 428 if (gr3d->nclocks != gr3d->soc->num_clocks) { 429 dev_err(dev, "invalid number of clocks: %u\n", gr3d->nclocks); 430 return -ENOENT; 431 } 432 433 return 0; 434 } 435 436 static int gr3d_get_resets(struct device *dev, struct gr3d *gr3d) 437 { 438 int err; 439 440 gr3d->resets[RST_MC].id = "mc"; 441 gr3d->resets[RST_MC2].id = "mc2"; 442 gr3d->resets[RST_GR3D].id = "3d"; 443 gr3d->resets[RST_GR3D2].id = "3d2"; 444 gr3d->nresets = gr3d->soc->num_resets; 445 446 err = devm_reset_control_bulk_get_optional_exclusive_released( 447 dev, gr3d->nresets, gr3d->resets); 448 if (err) { 449 dev_err(dev, "failed to get reset: %d\n", err); 450 return err; 451 } 452 453 if (WARN_ON(!gr3d->resets[RST_GR3D].rstc) || 454 WARN_ON(!gr3d->resets[RST_GR3D2].rstc && gr3d->nresets == 4)) 455 return -ENOENT; 456 457 return 0; 458 } 459 460 static int gr3d_probe(struct platform_device *pdev) 461 { 462 struct host1x_syncpt **syncpts; 463 struct gr3d *gr3d; 464 unsigned int i; 465 int err; 466 467 gr3d = devm_kzalloc(&pdev->dev, sizeof(*gr3d), GFP_KERNEL); 468 if (!gr3d) 469 return -ENOMEM; 470 471 platform_set_drvdata(pdev, gr3d); 472 473 gr3d->soc = of_device_get_match_data(&pdev->dev); 474 475 syncpts = devm_kzalloc(&pdev->dev, sizeof(*syncpts), GFP_KERNEL); 476 if (!syncpts) 477 return -ENOMEM; 478 479 err = gr3d_get_clocks(&pdev->dev, gr3d); 480 if (err) 481 return err; 482 483 err = gr3d_get_resets(&pdev->dev, gr3d); 484 if (err) 485 return err; 486 487 err = gr3d_init_power(&pdev->dev, gr3d); 488 if (err) 489 return err; 490 491 INIT_LIST_HEAD(&gr3d->client.base.list); 492 gr3d->client.base.ops = &gr3d_client_ops; 493 gr3d->client.base.dev = &pdev->dev; 494 gr3d->client.base.class = HOST1X_CLASS_GR3D; 495 gr3d->client.base.syncpts = syncpts; 496 gr3d->client.base.num_syncpts = 1; 497 498 INIT_LIST_HEAD(&gr3d->client.list); 499 gr3d->client.version = gr3d->soc->version; 500 gr3d->client.ops = &gr3d_ops; 501 502 err = devm_tegra_core_dev_init_opp_table_common(&pdev->dev); 503 if (err) 504 return err; 505 506 /* initialize address register map */ 507 for (i = 0; i < ARRAY_SIZE(gr3d_addr_regs); i++) 508 set_bit(gr3d_addr_regs[i], gr3d->addr_regs); 509 510 pm_runtime_enable(&pdev->dev); 511 512 err = host1x_client_register(&gr3d->client.base); 513 if (err < 0) { 514 pm_runtime_disable(&pdev->dev); 515 dev_err(&pdev->dev, "failed to register host1x client: %d\n", 516 err); 517 return err; 518 } 519 520 pm_runtime_use_autosuspend(&pdev->dev); 521 pm_runtime_set_autosuspend_delay(&pdev->dev, 500); 522 523 return 0; 524 } 525 526 static void gr3d_remove(struct platform_device *pdev) 527 { 528 struct gr3d *gr3d = platform_get_drvdata(pdev); 529 530 pm_runtime_disable(&pdev->dev); 531 host1x_client_unregister(&gr3d->client.base); 532 } 533 534 static int __maybe_unused gr3d_runtime_suspend(struct device *dev) 535 { 536 struct gr3d *gr3d = dev_get_drvdata(dev); 537 int err; 538 539 host1x_channel_stop(gr3d->channel); 540 541 err = reset_control_bulk_assert(gr3d->nresets, gr3d->resets); 542 if (err) { 543 dev_err(dev, "failed to assert reset: %d\n", err); 544 return err; 545 } 546 547 usleep_range(10, 20); 548 549 /* 550 * Older device-trees don't specify MC resets and power-gating can't 551 * be done safely in that case. Hence we will keep the power ungated 552 * for older DTBs. For newer DTBs, GENPD will perform the power-gating. 553 */ 554 555 clk_bulk_disable_unprepare(gr3d->nclocks, gr3d->clocks); 556 reset_control_bulk_release(gr3d->nresets, gr3d->resets); 557 558 return 0; 559 } 560 561 static int __maybe_unused gr3d_runtime_resume(struct device *dev) 562 { 563 struct gr3d *gr3d = dev_get_drvdata(dev); 564 int err; 565 566 err = reset_control_bulk_acquire(gr3d->nresets, gr3d->resets); 567 if (err) { 568 dev_err(dev, "failed to acquire reset: %d\n", err); 569 return err; 570 } 571 572 err = clk_bulk_prepare_enable(gr3d->nclocks, gr3d->clocks); 573 if (err) { 574 dev_err(dev, "failed to enable clock: %d\n", err); 575 goto release_reset; 576 } 577 578 err = reset_control_bulk_deassert(gr3d->nresets, gr3d->resets); 579 if (err) { 580 dev_err(dev, "failed to deassert reset: %d\n", err); 581 goto disable_clk; 582 } 583 584 return 0; 585 586 disable_clk: 587 clk_bulk_disable_unprepare(gr3d->nclocks, gr3d->clocks); 588 release_reset: 589 reset_control_bulk_release(gr3d->nresets, gr3d->resets); 590 591 return err; 592 } 593 594 static const struct dev_pm_ops tegra_gr3d_pm = { 595 SET_RUNTIME_PM_OPS(gr3d_runtime_suspend, gr3d_runtime_resume, NULL) 596 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 597 pm_runtime_force_resume) 598 }; 599 600 struct platform_driver tegra_gr3d_driver = { 601 .driver = { 602 .name = "tegra-gr3d", 603 .of_match_table = tegra_gr3d_match, 604 .pm = &tegra_gr3d_pm, 605 }, 606 .probe = gr3d_probe, 607 .remove = gr3d_remove, 608 }; 609