1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015, NVIDIA Corporation. 4 */ 5 6 #include <linux/platform_device.h> 7 #include <linux/dma-mapping.h> 8 #include <linux/firmware.h> 9 #include <linux/pci_ids.h> 10 #include <linux/iopoll.h> 11 12 #include "falcon.h" 13 #include "drm.h" 14 15 enum falcon_memory { 16 FALCON_MEMORY_IMEM, 17 FALCON_MEMORY_DATA, 18 }; 19 20 static void falcon_writel(struct falcon *falcon, u32 value, u32 offset) 21 { 22 writel(value, falcon->regs + offset); 23 } 24 25 int falcon_wait_idle(struct falcon *falcon) 26 { 27 u32 value; 28 29 if (falcon->riscv) 30 return readl_poll_timeout(falcon->regs + RISCV_CPUCTL, value, 31 (value & RISCV_CPUCTL_ACTIVE_STAT_ACTIVE), 10, 100000); 32 else 33 return readl_poll_timeout(falcon->regs + FALCON_IDLESTATE, value, 34 (value == 0), 10, 100000); 35 } 36 37 static int falcon_dma_wait_not_full(struct falcon *falcon) 38 { 39 u32 value; 40 41 return readl_poll_timeout(falcon->regs + FALCON_DMATRFCMD, value, 42 !(value & FALCON_DMATRFCMD_FULL), 10, 100000); 43 } 44 45 static int falcon_dma_wait_idle(struct falcon *falcon) 46 { 47 u32 value; 48 49 return readl_poll_timeout(falcon->regs + FALCON_DMATRFCMD, value, 50 (value & FALCON_DMATRFCMD_IDLE), 10, 100000); 51 } 52 53 static int falcon_copy_chunk(struct falcon *falcon, 54 phys_addr_t base, 55 unsigned long offset, 56 enum falcon_memory target) 57 { 58 u32 cmd = FALCON_DMATRFCMD_SIZE_256B; 59 int err; 60 61 if (target == FALCON_MEMORY_IMEM) 62 cmd |= FALCON_DMATRFCMD_IMEM; 63 64 /* 65 * Use second DMA context (i.e. the one for firmware). Strictly 66 * speaking, at this point both DMA contexts point to the firmware 67 * stream ID, but this register's value will be reused by the firmware 68 * for later DMA transactions, so we need to use the correct value. 69 */ 70 cmd |= FALCON_DMATRFCMD_DMACTX(1); 71 72 err = falcon_dma_wait_not_full(falcon); 73 if (err < 0) 74 return err; 75 76 falcon_writel(falcon, offset, FALCON_DMATRFMOFFS); 77 falcon_writel(falcon, base, FALCON_DMATRFFBOFFS); 78 falcon_writel(falcon, cmd, FALCON_DMATRFCMD); 79 80 return 0; 81 } 82 83 static void falcon_copy_firmware_image(struct falcon *falcon, 84 const struct firmware *firmware) 85 { 86 u32 *virt = falcon->firmware.virt; 87 size_t i; 88 89 /* copy the whole thing taking into account endianness */ 90 for (i = 0; i < firmware->size / sizeof(u32); i++) 91 virt[i] = le32_to_cpu(((__le32 *)firmware->data)[i]); 92 } 93 94 static int falcon_parse_firmware_image(struct falcon *falcon) 95 { 96 struct falcon_fw_bin_header_v1 *bin = (void *)falcon->firmware.virt; 97 struct falcon_fw_os_header_v1 *os; 98 99 /* endian problems would show up right here */ 100 if (bin->magic != PCI_VENDOR_ID_NVIDIA && bin->magic != 0x10fe) { 101 dev_err(falcon->dev, "incorrect firmware magic\n"); 102 return -EINVAL; 103 } 104 105 /* currently only version 1 is supported */ 106 if (bin->version != 1) { 107 dev_err(falcon->dev, "unsupported firmware version\n"); 108 return -EINVAL; 109 } 110 111 /* check that the firmware size is consistent */ 112 if (bin->size > falcon->firmware.size) { 113 dev_err(falcon->dev, "firmware image size inconsistency\n"); 114 return -EINVAL; 115 } 116 117 os = falcon->firmware.virt + bin->os_header_offset; 118 119 falcon->firmware.bin_data.size = bin->os_size; 120 falcon->firmware.bin_data.offset = bin->os_data_offset; 121 falcon->firmware.code.offset = os->code_offset; 122 falcon->firmware.code.size = os->code_size; 123 falcon->firmware.data.offset = os->data_offset; 124 falcon->firmware.data.size = os->data_size; 125 126 return 0; 127 } 128 129 static void falcon_parse_firmware_desc(struct falcon *falcon) 130 { 131 struct falcon_fw_riscv_desc *desc = 132 (struct falcon_fw_riscv_desc *)falcon->firmware.desc_firmware->data; 133 134 falcon->firmware.code.offset = desc->code_offset; 135 falcon->firmware.code.size = desc->code_size; 136 falcon->firmware.data.offset = desc->data_offset; 137 falcon->firmware.data.size = desc->data_size; 138 } 139 140 int falcon_read_firmware(struct falcon *falcon, const char *name) 141 { 142 int err; 143 144 /* request_firmware prints error if it fails */ 145 err = request_firmware(&falcon->firmware.firmware, name, falcon->dev); 146 if (err < 0) 147 return err; 148 149 falcon->firmware.size = falcon->firmware.firmware->size; 150 151 if (falcon->riscv) { 152 /* Load separate descriptor */ 153 char desc_name[128]; 154 155 scnprintf(desc_name, sizeof(desc_name), "%s.desc", name); 156 err = request_firmware(&falcon->firmware.desc_firmware, desc_name, falcon->dev); 157 if (err < 0) 158 goto release_firmware; 159 } 160 161 return 0; 162 163 release_firmware: 164 release_firmware(falcon->firmware.firmware); 165 falcon->firmware.firmware = NULL; 166 167 return err; 168 } 169 170 int falcon_load_firmware(struct falcon *falcon) 171 { 172 const struct firmware *firmware = falcon->firmware.firmware; 173 int err; 174 175 /* copy firmware image into local area. this also ensures endianness */ 176 falcon_copy_firmware_image(falcon, firmware); 177 178 if (falcon->riscv) { 179 falcon_parse_firmware_desc(falcon); 180 } else { 181 err = falcon_parse_firmware_image(falcon); 182 if (err < 0) { 183 dev_err(falcon->dev, "failed to parse firmware image\n"); 184 return err; 185 } 186 } 187 188 release_firmware(firmware); 189 falcon->firmware.firmware = NULL; 190 191 release_firmware(falcon->firmware.desc_firmware); 192 falcon->firmware.desc_firmware = NULL; 193 194 return 0; 195 } 196 197 int falcon_init(struct falcon *falcon) 198 { 199 falcon->firmware.virt = NULL; 200 201 return 0; 202 } 203 204 void falcon_exit(struct falcon *falcon) 205 { 206 if (falcon->firmware.firmware) 207 release_firmware(falcon->firmware.firmware); 208 209 if (falcon->firmware.desc_firmware) 210 release_firmware(falcon->firmware.desc_firmware); 211 } 212 213 int falcon_boot(struct falcon *falcon) 214 { 215 unsigned long offset; 216 u32 value; 217 int err; 218 219 if (!falcon->firmware.virt) 220 return -EINVAL; 221 222 err = readl_poll_timeout(falcon->regs + FALCON_DMACTL, value, 223 (value & (FALCON_DMACTL_IMEM_SCRUBBING | 224 FALCON_DMACTL_DMEM_SCRUBBING)) == 0, 225 10, 10000); 226 if (err < 0) 227 return err; 228 229 falcon_writel(falcon, 0, FALCON_DMACTL); 230 231 /* setup the address of the binary data so Falcon can access it later */ 232 falcon_writel(falcon, (falcon->firmware.iova + 233 falcon->firmware.bin_data.offset) >> 8, 234 FALCON_DMATRFBASE); 235 236 /* copy the data segment into Falcon internal memory */ 237 for (offset = 0; offset < falcon->firmware.data.size; offset += 256) 238 falcon_copy_chunk(falcon, 239 falcon->firmware.data.offset + offset, 240 offset, FALCON_MEMORY_DATA); 241 242 /* copy the code segment into Falcon internal memory */ 243 for (offset = 0; offset < falcon->firmware.code.size; offset += 256) 244 falcon_copy_chunk(falcon, falcon->firmware.code.offset + offset, 245 offset, FALCON_MEMORY_IMEM); 246 247 /* wait for DMA to complete */ 248 err = falcon_dma_wait_idle(falcon); 249 if (err < 0) 250 return err; 251 252 /* setup falcon interrupts */ 253 falcon_writel(falcon, FALCON_IRQMSET_EXT(0xff) | 254 FALCON_IRQMSET_SWGEN1 | 255 FALCON_IRQMSET_SWGEN0 | 256 FALCON_IRQMSET_EXTERR | 257 FALCON_IRQMSET_HALT | 258 FALCON_IRQMSET_WDTMR, 259 FALCON_IRQMSET); 260 falcon_writel(falcon, FALCON_IRQDEST_EXT(0xff) | 261 FALCON_IRQDEST_SWGEN1 | 262 FALCON_IRQDEST_SWGEN0 | 263 FALCON_IRQDEST_EXTERR | 264 FALCON_IRQDEST_HALT, 265 FALCON_IRQDEST); 266 267 /* enable interface */ 268 falcon_writel(falcon, FALCON_ITFEN_MTHDEN | 269 FALCON_ITFEN_CTXEN, 270 FALCON_ITFEN); 271 272 if (falcon->riscv) { 273 falcon_writel(falcon, RISCV_BCR_CTRL_CORE_SELECT_RISCV, RISCV_BCR_CTRL); 274 falcon_writel(falcon, 0x0, RISCV_BOOT_VECTOR_HI); 275 falcon_writel(falcon, 0x100000, RISCV_BOOT_VECTOR_LO); 276 falcon_writel(falcon, RISCV_CPUCTL_STARTCPU, RISCV_CPUCTL); 277 } else { 278 falcon_writel(falcon, 0x00000000, FALCON_BOOTVEC); 279 falcon_writel(falcon, FALCON_CPUCTL_STARTCPU, FALCON_CPUCTL); 280 } 281 282 err = falcon_wait_idle(falcon); 283 if (err < 0) { 284 dev_err(falcon->dev, "Falcon boot failed due to timeout\n"); 285 return err; 286 } 287 288 return 0; 289 } 290 291 void falcon_execute_method(struct falcon *falcon, u32 method, u32 data) 292 { 293 falcon_writel(falcon, method >> 2, FALCON_UCLASS_METHOD_OFFSET); 294 falcon_writel(falcon, data, FALCON_UCLASS_METHOD_DATA); 295 } 296