1dec72739SThierry Reding /* 2dec72739SThierry Reding * Copyright (C) 2013 NVIDIA Corporation 3dec72739SThierry Reding * 49a2ac2dcSThierry Reding * This program is free software; you can redistribute it and/or modify 59a2ac2dcSThierry Reding * it under the terms of the GNU General Public License version 2 as 69a2ac2dcSThierry Reding * published by the Free Software Foundation. 7dec72739SThierry Reding */ 8dec72739SThierry Reding 9dec72739SThierry Reding #ifndef DRM_TEGRA_DSI_H 10dec72739SThierry Reding #define DRM_TEGRA_DSI_H 11dec72739SThierry Reding 12dec72739SThierry Reding #define DSI_INCR_SYNCPT 0x00 13dec72739SThierry Reding #define DSI_INCR_SYNCPT_CONTROL 0x01 14dec72739SThierry Reding #define DSI_INCR_SYNCPT_ERROR 0x02 15dec72739SThierry Reding #define DSI_CTXSW 0x08 16dec72739SThierry Reding #define DSI_RD_DATA 0x09 17dec72739SThierry Reding #define DSI_WR_DATA 0x0a 18dec72739SThierry Reding #define DSI_POWER_CONTROL 0x0b 19dec72739SThierry Reding #define DSI_POWER_CONTROL_ENABLE (1 << 0) 20dec72739SThierry Reding #define DSI_INT_ENABLE 0x0c 21dec72739SThierry Reding #define DSI_INT_STATUS 0x0d 22dec72739SThierry Reding #define DSI_INT_MASK 0x0e 23dec72739SThierry Reding #define DSI_HOST_CONTROL 0x0f 24*0fffdf6cSThierry Reding #define DSI_HOST_CONTROL_FIFO_RESET (1 << 21) 25*0fffdf6cSThierry Reding #define DSI_HOST_CONTROL_CRC_RESET (1 << 20) 26*0fffdf6cSThierry Reding #define DSI_HOST_CONTROL_TX_TRIG_SOL (0 << 12) 27*0fffdf6cSThierry Reding #define DSI_HOST_CONTROL_TX_TRIG_FIFO (1 << 12) 28*0fffdf6cSThierry Reding #define DSI_HOST_CONTROL_TX_TRIG_HOST (2 << 12) 29dec72739SThierry Reding #define DSI_HOST_CONTROL_RAW (1 << 6) 30dec72739SThierry Reding #define DSI_HOST_CONTROL_HS (1 << 5) 31*0fffdf6cSThierry Reding #define DSI_HOST_CONTROL_FIFO_SEL (1 << 4) 32*0fffdf6cSThierry Reding #define DSI_HOST_CONTROL_IMM_BTA (1 << 3) 33*0fffdf6cSThierry Reding #define DSI_HOST_CONTROL_PKT_BTA (1 << 2) 34dec72739SThierry Reding #define DSI_HOST_CONTROL_CS (1 << 1) 35dec72739SThierry Reding #define DSI_HOST_CONTROL_ECC (1 << 0) 36dec72739SThierry Reding #define DSI_CONTROL 0x10 37dec72739SThierry Reding #define DSI_CONTROL_HS_CLK_CTRL (1 << 20) 38dec72739SThierry Reding #define DSI_CONTROL_CHANNEL(c) (((c) & 0x3) << 16) 39dec72739SThierry Reding #define DSI_CONTROL_FORMAT(f) (((f) & 0x3) << 12) 40dec72739SThierry Reding #define DSI_CONTROL_TX_TRIG(x) (((x) & 0x3) << 8) 41dec72739SThierry Reding #define DSI_CONTROL_LANES(n) (((n) & 0x3) << 4) 42dec72739SThierry Reding #define DSI_CONTROL_DCS_ENABLE (1 << 3) 43dec72739SThierry Reding #define DSI_CONTROL_SOURCE(s) (((s) & 0x1) << 2) 44dec72739SThierry Reding #define DSI_CONTROL_VIDEO_ENABLE (1 << 1) 45dec72739SThierry Reding #define DSI_CONTROL_HOST_ENABLE (1 << 0) 46dec72739SThierry Reding #define DSI_SOL_DELAY 0x11 47dec72739SThierry Reding #define DSI_MAX_THRESHOLD 0x12 48dec72739SThierry Reding #define DSI_TRIGGER 0x13 49*0fffdf6cSThierry Reding #define DSI_TRIGGER_HOST (1 << 1) 50*0fffdf6cSThierry Reding #define DSI_TRIGGER_VIDEO (1 << 0) 51dec72739SThierry Reding #define DSI_TX_CRC 0x14 52dec72739SThierry Reding #define DSI_STATUS 0x15 53dec72739SThierry Reding #define DSI_STATUS_IDLE (1 << 10) 54*0fffdf6cSThierry Reding #define DSI_STATUS_UNDERFLOW (1 << 9) 55*0fffdf6cSThierry Reding #define DSI_STATUS_OVERFLOW (1 << 8) 56dec72739SThierry Reding #define DSI_INIT_SEQ_CONTROL 0x1a 57dec72739SThierry Reding #define DSI_INIT_SEQ_DATA_0 0x1b 58dec72739SThierry Reding #define DSI_INIT_SEQ_DATA_1 0x1c 59dec72739SThierry Reding #define DSI_INIT_SEQ_DATA_2 0x1d 60dec72739SThierry Reding #define DSI_INIT_SEQ_DATA_3 0x1e 61dec72739SThierry Reding #define DSI_INIT_SEQ_DATA_4 0x1f 62dec72739SThierry Reding #define DSI_INIT_SEQ_DATA_5 0x20 63dec72739SThierry Reding #define DSI_INIT_SEQ_DATA_6 0x21 64dec72739SThierry Reding #define DSI_INIT_SEQ_DATA_7 0x22 65dec72739SThierry Reding #define DSI_PKT_SEQ_0_LO 0x23 66dec72739SThierry Reding #define DSI_PKT_SEQ_0_HI 0x24 67dec72739SThierry Reding #define DSI_PKT_SEQ_1_LO 0x25 68dec72739SThierry Reding #define DSI_PKT_SEQ_1_HI 0x26 69dec72739SThierry Reding #define DSI_PKT_SEQ_2_LO 0x27 70dec72739SThierry Reding #define DSI_PKT_SEQ_2_HI 0x28 71dec72739SThierry Reding #define DSI_PKT_SEQ_3_LO 0x29 72dec72739SThierry Reding #define DSI_PKT_SEQ_3_HI 0x2a 73dec72739SThierry Reding #define DSI_PKT_SEQ_4_LO 0x2b 74dec72739SThierry Reding #define DSI_PKT_SEQ_4_HI 0x2c 75dec72739SThierry Reding #define DSI_PKT_SEQ_5_LO 0x2d 76dec72739SThierry Reding #define DSI_PKT_SEQ_5_HI 0x2e 77dec72739SThierry Reding #define DSI_DCS_CMDS 0x33 78dec72739SThierry Reding #define DSI_PKT_LEN_0_1 0x34 79dec72739SThierry Reding #define DSI_PKT_LEN_2_3 0x35 80dec72739SThierry Reding #define DSI_PKT_LEN_4_5 0x36 81dec72739SThierry Reding #define DSI_PKT_LEN_6_7 0x37 82dec72739SThierry Reding #define DSI_PHY_TIMING_0 0x3c 83dec72739SThierry Reding #define DSI_PHY_TIMING_1 0x3d 84dec72739SThierry Reding #define DSI_PHY_TIMING_2 0x3e 85dec72739SThierry Reding #define DSI_BTA_TIMING 0x3f 86dec72739SThierry Reding 87dec72739SThierry Reding #define DSI_TIMING_FIELD(value, period, hwinc) \ 88dec72739SThierry Reding ((DIV_ROUND_CLOSEST(value, period) - (hwinc)) & 0xff) 89dec72739SThierry Reding 90dec72739SThierry Reding #define DSI_TIMEOUT_0 0x44 91dec72739SThierry Reding #define DSI_TIMEOUT_LRX(x) (((x) & 0xffff) << 16) 92dec72739SThierry Reding #define DSI_TIMEOUT_HTX(x) (((x) & 0xffff) << 0) 93dec72739SThierry Reding #define DSI_TIMEOUT_1 0x45 94dec72739SThierry Reding #define DSI_TIMEOUT_PR(x) (((x) & 0xffff) << 16) 95dec72739SThierry Reding #define DSI_TIMEOUT_TA(x) (((x) & 0xffff) << 0) 96dec72739SThierry Reding #define DSI_TO_TALLY 0x46 97dec72739SThierry Reding #define DSI_TALLY_TA(x) (((x) & 0xff) << 16) 98dec72739SThierry Reding #define DSI_TALLY_LRX(x) (((x) & 0xff) << 8) 99dec72739SThierry Reding #define DSI_TALLY_HTX(x) (((x) & 0xff) << 0) 100dec72739SThierry Reding #define DSI_PAD_CONTROL_0 0x4b 101dec72739SThierry Reding #define DSI_PAD_CONTROL_VS1_PDIO(x) (((x) & 0xf) << 0) 102dec72739SThierry Reding #define DSI_PAD_CONTROL_VS1_PDIO_CLK (1 << 8) 103dec72739SThierry Reding #define DSI_PAD_CONTROL_VS1_PULLDN(x) (((x) & 0xf) << 16) 104dec72739SThierry Reding #define DSI_PAD_CONTROL_VS1_PULLDN_CLK (1 << 24) 105dec72739SThierry Reding #define DSI_PAD_CONTROL_CD 0x4c 106dec72739SThierry Reding #define DSI_PAD_CD_STATUS 0x4d 107dec72739SThierry Reding #define DSI_VIDEO_MODE_CONTROL 0x4e 108dec72739SThierry Reding #define DSI_PAD_CONTROL_1 0x4f 109dec72739SThierry Reding #define DSI_PAD_CONTROL_2 0x50 110dec72739SThierry Reding #define DSI_PAD_OUT_CLK(x) (((x) & 0x7) << 0) 111dec72739SThierry Reding #define DSI_PAD_LP_DN(x) (((x) & 0x7) << 4) 112dec72739SThierry Reding #define DSI_PAD_LP_UP(x) (((x) & 0x7) << 8) 113dec72739SThierry Reding #define DSI_PAD_SLEW_DN(x) (((x) & 0x7) << 12) 114dec72739SThierry Reding #define DSI_PAD_SLEW_UP(x) (((x) & 0x7) << 16) 115dec72739SThierry Reding #define DSI_PAD_CONTROL_3 0x51 116dec72739SThierry Reding #define DSI_PAD_CONTROL_4 0x52 117dec72739SThierry Reding #define DSI_GANGED_MODE_CONTROL 0x53 118e94236cdSThierry Reding #define DSI_GANGED_MODE_CONTROL_ENABLE (1 << 0) 119dec72739SThierry Reding #define DSI_GANGED_MODE_START 0x54 120dec72739SThierry Reding #define DSI_GANGED_MODE_SIZE 0x55 121dec72739SThierry Reding #define DSI_RAW_DATA_BYTE_COUNT 0x56 122dec72739SThierry Reding #define DSI_ULTRA_LOW_POWER_CONTROL 0x57 123dec72739SThierry Reding #define DSI_INIT_SEQ_DATA_8 0x58 124dec72739SThierry Reding #define DSI_INIT_SEQ_DATA_9 0x59 125dec72739SThierry Reding #define DSI_INIT_SEQ_DATA_10 0x5a 126dec72739SThierry Reding #define DSI_INIT_SEQ_DATA_11 0x5b 127dec72739SThierry Reding #define DSI_INIT_SEQ_DATA_12 0x5c 128dec72739SThierry Reding #define DSI_INIT_SEQ_DATA_13 0x5d 129dec72739SThierry Reding #define DSI_INIT_SEQ_DATA_14 0x5e 130dec72739SThierry Reding #define DSI_INIT_SEQ_DATA_15 0x5f 131dec72739SThierry Reding 132f7d6889bSThierry Reding /* 133f7d6889bSThierry Reding * pixel format as used in the DSI_CONTROL_FORMAT field 134f7d6889bSThierry Reding */ 135f7d6889bSThierry Reding enum tegra_dsi_format { 136f7d6889bSThierry Reding TEGRA_DSI_FORMAT_16P, 137f7d6889bSThierry Reding TEGRA_DSI_FORMAT_18NP, 138f7d6889bSThierry Reding TEGRA_DSI_FORMAT_18P, 139f7d6889bSThierry Reding TEGRA_DSI_FORMAT_24P, 140f7d6889bSThierry Reding }; 141f7d6889bSThierry Reding 142dec72739SThierry Reding #endif 143