1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 NVIDIA Corporation 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/debugfs.h> 8 #include <linux/delay.h> 9 #include <linux/host1x.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_platform.h> 13 #include <linux/platform_device.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/reset.h> 17 18 #include <video/mipi_display.h> 19 20 #include <drm/drm_atomic_helper.h> 21 #include <drm/drm_debugfs.h> 22 #include <drm/drm_file.h> 23 #include <drm/drm_mipi_dsi.h> 24 #include <drm/drm_panel.h> 25 #include <drm/drm_print.h> 26 #include <drm/drm_simple_kms_helper.h> 27 28 #include "dc.h" 29 #include "drm.h" 30 #include "dsi.h" 31 #include "mipi-phy.h" 32 #include "trace.h" 33 34 struct tegra_dsi_state { 35 struct drm_connector_state base; 36 37 struct mipi_dphy_timing timing; 38 unsigned long period; 39 40 unsigned int vrefresh; 41 unsigned int lanes; 42 unsigned long pclk; 43 unsigned long bclk; 44 45 enum tegra_dsi_format format; 46 unsigned int mul; 47 unsigned int div; 48 }; 49 50 static inline struct tegra_dsi_state * 51 to_dsi_state(struct drm_connector_state *state) 52 { 53 return container_of(state, struct tegra_dsi_state, base); 54 } 55 56 struct tegra_dsi { 57 struct host1x_client client; 58 struct tegra_output output; 59 struct device *dev; 60 61 void __iomem *regs; 62 63 struct reset_control *rst; 64 struct clk *clk_parent; 65 struct clk *clk_lp; 66 struct clk *clk; 67 68 struct drm_info_list *debugfs_files; 69 70 unsigned long flags; 71 enum mipi_dsi_pixel_format format; 72 unsigned int lanes; 73 74 struct tegra_mipi_device *mipi; 75 struct mipi_dsi_host host; 76 77 struct regulator *vdd; 78 79 unsigned int video_fifo_depth; 80 unsigned int host_fifo_depth; 81 82 /* for ganged-mode support */ 83 struct tegra_dsi *master; 84 struct tegra_dsi *slave; 85 }; 86 87 static inline struct tegra_dsi * 88 host1x_client_to_dsi(struct host1x_client *client) 89 { 90 return container_of(client, struct tegra_dsi, client); 91 } 92 93 static inline struct tegra_dsi *host_to_tegra(struct mipi_dsi_host *host) 94 { 95 return container_of(host, struct tegra_dsi, host); 96 } 97 98 static inline struct tegra_dsi *to_dsi(struct tegra_output *output) 99 { 100 return container_of(output, struct tegra_dsi, output); 101 } 102 103 static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi) 104 { 105 return to_dsi_state(dsi->output.connector.state); 106 } 107 108 static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned int offset) 109 { 110 u32 value = readl(dsi->regs + (offset << 2)); 111 112 trace_dsi_readl(dsi->dev, offset, value); 113 114 return value; 115 } 116 117 static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value, 118 unsigned int offset) 119 { 120 trace_dsi_writel(dsi->dev, offset, value); 121 writel(value, dsi->regs + (offset << 2)); 122 } 123 124 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name } 125 126 static const struct debugfs_reg32 tegra_dsi_regs[] = { 127 DEBUGFS_REG32(DSI_INCR_SYNCPT), 128 DEBUGFS_REG32(DSI_INCR_SYNCPT_CONTROL), 129 DEBUGFS_REG32(DSI_INCR_SYNCPT_ERROR), 130 DEBUGFS_REG32(DSI_CTXSW), 131 DEBUGFS_REG32(DSI_RD_DATA), 132 DEBUGFS_REG32(DSI_WR_DATA), 133 DEBUGFS_REG32(DSI_POWER_CONTROL), 134 DEBUGFS_REG32(DSI_INT_ENABLE), 135 DEBUGFS_REG32(DSI_INT_STATUS), 136 DEBUGFS_REG32(DSI_INT_MASK), 137 DEBUGFS_REG32(DSI_HOST_CONTROL), 138 DEBUGFS_REG32(DSI_CONTROL), 139 DEBUGFS_REG32(DSI_SOL_DELAY), 140 DEBUGFS_REG32(DSI_MAX_THRESHOLD), 141 DEBUGFS_REG32(DSI_TRIGGER), 142 DEBUGFS_REG32(DSI_TX_CRC), 143 DEBUGFS_REG32(DSI_STATUS), 144 DEBUGFS_REG32(DSI_INIT_SEQ_CONTROL), 145 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_0), 146 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_1), 147 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_2), 148 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_3), 149 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_4), 150 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_5), 151 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_6), 152 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_7), 153 DEBUGFS_REG32(DSI_PKT_SEQ_0_LO), 154 DEBUGFS_REG32(DSI_PKT_SEQ_0_HI), 155 DEBUGFS_REG32(DSI_PKT_SEQ_1_LO), 156 DEBUGFS_REG32(DSI_PKT_SEQ_1_HI), 157 DEBUGFS_REG32(DSI_PKT_SEQ_2_LO), 158 DEBUGFS_REG32(DSI_PKT_SEQ_2_HI), 159 DEBUGFS_REG32(DSI_PKT_SEQ_3_LO), 160 DEBUGFS_REG32(DSI_PKT_SEQ_3_HI), 161 DEBUGFS_REG32(DSI_PKT_SEQ_4_LO), 162 DEBUGFS_REG32(DSI_PKT_SEQ_4_HI), 163 DEBUGFS_REG32(DSI_PKT_SEQ_5_LO), 164 DEBUGFS_REG32(DSI_PKT_SEQ_5_HI), 165 DEBUGFS_REG32(DSI_DCS_CMDS), 166 DEBUGFS_REG32(DSI_PKT_LEN_0_1), 167 DEBUGFS_REG32(DSI_PKT_LEN_2_3), 168 DEBUGFS_REG32(DSI_PKT_LEN_4_5), 169 DEBUGFS_REG32(DSI_PKT_LEN_6_7), 170 DEBUGFS_REG32(DSI_PHY_TIMING_0), 171 DEBUGFS_REG32(DSI_PHY_TIMING_1), 172 DEBUGFS_REG32(DSI_PHY_TIMING_2), 173 DEBUGFS_REG32(DSI_BTA_TIMING), 174 DEBUGFS_REG32(DSI_TIMEOUT_0), 175 DEBUGFS_REG32(DSI_TIMEOUT_1), 176 DEBUGFS_REG32(DSI_TO_TALLY), 177 DEBUGFS_REG32(DSI_PAD_CONTROL_0), 178 DEBUGFS_REG32(DSI_PAD_CONTROL_CD), 179 DEBUGFS_REG32(DSI_PAD_CD_STATUS), 180 DEBUGFS_REG32(DSI_VIDEO_MODE_CONTROL), 181 DEBUGFS_REG32(DSI_PAD_CONTROL_1), 182 DEBUGFS_REG32(DSI_PAD_CONTROL_2), 183 DEBUGFS_REG32(DSI_PAD_CONTROL_3), 184 DEBUGFS_REG32(DSI_PAD_CONTROL_4), 185 DEBUGFS_REG32(DSI_GANGED_MODE_CONTROL), 186 DEBUGFS_REG32(DSI_GANGED_MODE_START), 187 DEBUGFS_REG32(DSI_GANGED_MODE_SIZE), 188 DEBUGFS_REG32(DSI_RAW_DATA_BYTE_COUNT), 189 DEBUGFS_REG32(DSI_ULTRA_LOW_POWER_CONTROL), 190 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_8), 191 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_9), 192 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_10), 193 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_11), 194 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_12), 195 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_13), 196 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_14), 197 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_15), 198 }; 199 200 static int tegra_dsi_show_regs(struct seq_file *s, void *data) 201 { 202 struct drm_info_node *node = s->private; 203 struct tegra_dsi *dsi = node->info_ent->data; 204 struct drm_crtc *crtc = dsi->output.encoder.crtc; 205 struct drm_device *drm = node->minor->dev; 206 unsigned int i; 207 int err = 0; 208 209 drm_modeset_lock_all(drm); 210 211 if (!crtc || !crtc->state->active) { 212 err = -EBUSY; 213 goto unlock; 214 } 215 216 for (i = 0; i < ARRAY_SIZE(tegra_dsi_regs); i++) { 217 unsigned int offset = tegra_dsi_regs[i].offset; 218 219 seq_printf(s, "%-32s %#05x %08x\n", tegra_dsi_regs[i].name, 220 offset, tegra_dsi_readl(dsi, offset)); 221 } 222 223 unlock: 224 drm_modeset_unlock_all(drm); 225 return err; 226 } 227 228 static struct drm_info_list debugfs_files[] = { 229 { "regs", tegra_dsi_show_regs, 0, NULL }, 230 }; 231 232 static int tegra_dsi_late_register(struct drm_connector *connector) 233 { 234 struct tegra_output *output = connector_to_output(connector); 235 unsigned int i, count = ARRAY_SIZE(debugfs_files); 236 struct drm_minor *minor = connector->dev->primary; 237 struct dentry *root = connector->debugfs_entry; 238 struct tegra_dsi *dsi = to_dsi(output); 239 240 dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), 241 GFP_KERNEL); 242 if (!dsi->debugfs_files) 243 return -ENOMEM; 244 245 for (i = 0; i < count; i++) 246 dsi->debugfs_files[i].data = dsi; 247 248 drm_debugfs_create_files(dsi->debugfs_files, count, root, minor); 249 250 return 0; 251 } 252 253 static void tegra_dsi_early_unregister(struct drm_connector *connector) 254 { 255 struct tegra_output *output = connector_to_output(connector); 256 unsigned int count = ARRAY_SIZE(debugfs_files); 257 struct tegra_dsi *dsi = to_dsi(output); 258 259 drm_debugfs_remove_files(dsi->debugfs_files, count, 260 connector->debugfs_entry, 261 connector->dev->primary); 262 kfree(dsi->debugfs_files); 263 dsi->debugfs_files = NULL; 264 } 265 266 #define PKT_ID0(id) ((((id) & 0x3f) << 3) | (1 << 9)) 267 #define PKT_LEN0(len) (((len) & 0x07) << 0) 268 #define PKT_ID1(id) ((((id) & 0x3f) << 13) | (1 << 19)) 269 #define PKT_LEN1(len) (((len) & 0x07) << 10) 270 #define PKT_ID2(id) ((((id) & 0x3f) << 23) | (1 << 29)) 271 #define PKT_LEN2(len) (((len) & 0x07) << 20) 272 273 #define PKT_LP (1 << 30) 274 #define NUM_PKT_SEQ 12 275 276 /* 277 * non-burst mode with sync pulses 278 */ 279 static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = { 280 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) | 281 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 282 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | 283 PKT_LP, 284 [ 1] = 0, 285 [ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) | 286 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 287 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | 288 PKT_LP, 289 [ 3] = 0, 290 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 291 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 292 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | 293 PKT_LP, 294 [ 5] = 0, 295 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 296 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 297 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0), 298 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) | 299 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) | 300 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4), 301 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 302 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 303 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | 304 PKT_LP, 305 [ 9] = 0, 306 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 307 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 308 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0), 309 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) | 310 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) | 311 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4), 312 }; 313 314 /* 315 * non-burst mode with sync events 316 */ 317 static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = { 318 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) | 319 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | 320 PKT_LP, 321 [ 1] = 0, 322 [ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 323 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | 324 PKT_LP, 325 [ 3] = 0, 326 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 327 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | 328 PKT_LP, 329 [ 5] = 0, 330 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 331 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) | 332 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3), 333 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4), 334 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 335 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | 336 PKT_LP, 337 [ 9] = 0, 338 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 339 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) | 340 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3), 341 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4), 342 }; 343 344 static const u32 pkt_seq_command_mode[NUM_PKT_SEQ] = { 345 [ 0] = 0, 346 [ 1] = 0, 347 [ 2] = 0, 348 [ 3] = 0, 349 [ 4] = 0, 350 [ 5] = 0, 351 [ 6] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(3) | PKT_LP, 352 [ 7] = 0, 353 [ 8] = 0, 354 [ 9] = 0, 355 [10] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(5) | PKT_LP, 356 [11] = 0, 357 }; 358 359 static void tegra_dsi_set_phy_timing(struct tegra_dsi *dsi, 360 unsigned long period, 361 const struct mipi_dphy_timing *timing) 362 { 363 u32 value; 364 365 value = DSI_TIMING_FIELD(timing->hsexit, period, 1) << 24 | 366 DSI_TIMING_FIELD(timing->hstrail, period, 0) << 16 | 367 DSI_TIMING_FIELD(timing->hszero, period, 3) << 8 | 368 DSI_TIMING_FIELD(timing->hsprepare, period, 1); 369 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0); 370 371 value = DSI_TIMING_FIELD(timing->clktrail, period, 1) << 24 | 372 DSI_TIMING_FIELD(timing->clkpost, period, 1) << 16 | 373 DSI_TIMING_FIELD(timing->clkzero, period, 1) << 8 | 374 DSI_TIMING_FIELD(timing->lpx, period, 1); 375 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1); 376 377 value = DSI_TIMING_FIELD(timing->clkprepare, period, 1) << 16 | 378 DSI_TIMING_FIELD(timing->clkpre, period, 1) << 8 | 379 DSI_TIMING_FIELD(0xff * period, period, 0) << 0; 380 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2); 381 382 value = DSI_TIMING_FIELD(timing->taget, period, 1) << 16 | 383 DSI_TIMING_FIELD(timing->tasure, period, 1) << 8 | 384 DSI_TIMING_FIELD(timing->tago, period, 1); 385 tegra_dsi_writel(dsi, value, DSI_BTA_TIMING); 386 387 if (dsi->slave) 388 tegra_dsi_set_phy_timing(dsi->slave, period, timing); 389 } 390 391 static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format, 392 unsigned int *mulp, unsigned int *divp) 393 { 394 switch (format) { 395 case MIPI_DSI_FMT_RGB666_PACKED: 396 case MIPI_DSI_FMT_RGB888: 397 *mulp = 3; 398 *divp = 1; 399 break; 400 401 case MIPI_DSI_FMT_RGB565: 402 *mulp = 2; 403 *divp = 1; 404 break; 405 406 case MIPI_DSI_FMT_RGB666: 407 *mulp = 9; 408 *divp = 4; 409 break; 410 411 default: 412 return -EINVAL; 413 } 414 415 return 0; 416 } 417 418 static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format, 419 enum tegra_dsi_format *fmt) 420 { 421 switch (format) { 422 case MIPI_DSI_FMT_RGB888: 423 *fmt = TEGRA_DSI_FORMAT_24P; 424 break; 425 426 case MIPI_DSI_FMT_RGB666: 427 *fmt = TEGRA_DSI_FORMAT_18NP; 428 break; 429 430 case MIPI_DSI_FMT_RGB666_PACKED: 431 *fmt = TEGRA_DSI_FORMAT_18P; 432 break; 433 434 case MIPI_DSI_FMT_RGB565: 435 *fmt = TEGRA_DSI_FORMAT_16P; 436 break; 437 438 default: 439 return -EINVAL; 440 } 441 442 return 0; 443 } 444 445 static void tegra_dsi_ganged_enable(struct tegra_dsi *dsi, unsigned int start, 446 unsigned int size) 447 { 448 u32 value; 449 450 tegra_dsi_writel(dsi, start, DSI_GANGED_MODE_START); 451 tegra_dsi_writel(dsi, size << 16 | size, DSI_GANGED_MODE_SIZE); 452 453 value = DSI_GANGED_MODE_CONTROL_ENABLE; 454 tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL); 455 } 456 457 static void tegra_dsi_enable(struct tegra_dsi *dsi) 458 { 459 u32 value; 460 461 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 462 value |= DSI_POWER_CONTROL_ENABLE; 463 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); 464 465 if (dsi->slave) 466 tegra_dsi_enable(dsi->slave); 467 } 468 469 static unsigned int tegra_dsi_get_lanes(struct tegra_dsi *dsi) 470 { 471 if (dsi->master) 472 return dsi->master->lanes + dsi->lanes; 473 474 if (dsi->slave) 475 return dsi->lanes + dsi->slave->lanes; 476 477 return dsi->lanes; 478 } 479 480 static void tegra_dsi_configure(struct tegra_dsi *dsi, unsigned int pipe, 481 const struct drm_display_mode *mode) 482 { 483 unsigned int hact, hsw, hbp, hfp, i, mul, div; 484 struct tegra_dsi_state *state; 485 const u32 *pkt_seq; 486 u32 value; 487 488 /* XXX: pass in state into this function? */ 489 if (dsi->master) 490 state = tegra_dsi_get_state(dsi->master); 491 else 492 state = tegra_dsi_get_state(dsi); 493 494 mul = state->mul; 495 div = state->div; 496 497 if (dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { 498 DRM_DEBUG_KMS("Non-burst video mode with sync pulses\n"); 499 pkt_seq = pkt_seq_video_non_burst_sync_pulses; 500 } else if (dsi->flags & MIPI_DSI_MODE_VIDEO) { 501 DRM_DEBUG_KMS("Non-burst video mode with sync events\n"); 502 pkt_seq = pkt_seq_video_non_burst_sync_events; 503 } else { 504 DRM_DEBUG_KMS("Command mode\n"); 505 pkt_seq = pkt_seq_command_mode; 506 } 507 508 value = DSI_CONTROL_CHANNEL(0) | 509 DSI_CONTROL_FORMAT(state->format) | 510 DSI_CONTROL_LANES(dsi->lanes - 1) | 511 DSI_CONTROL_SOURCE(pipe); 512 tegra_dsi_writel(dsi, value, DSI_CONTROL); 513 514 tegra_dsi_writel(dsi, dsi->video_fifo_depth, DSI_MAX_THRESHOLD); 515 516 value = DSI_HOST_CONTROL_HS; 517 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); 518 519 value = tegra_dsi_readl(dsi, DSI_CONTROL); 520 521 if (dsi->flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) 522 value |= DSI_CONTROL_HS_CLK_CTRL; 523 524 value &= ~DSI_CONTROL_TX_TRIG(3); 525 526 /* enable DCS commands for command mode */ 527 if (dsi->flags & MIPI_DSI_MODE_VIDEO) 528 value &= ~DSI_CONTROL_DCS_ENABLE; 529 else 530 value |= DSI_CONTROL_DCS_ENABLE; 531 532 value |= DSI_CONTROL_VIDEO_ENABLE; 533 value &= ~DSI_CONTROL_HOST_ENABLE; 534 tegra_dsi_writel(dsi, value, DSI_CONTROL); 535 536 for (i = 0; i < NUM_PKT_SEQ; i++) 537 tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i); 538 539 if (dsi->flags & MIPI_DSI_MODE_VIDEO) { 540 /* horizontal active pixels */ 541 hact = mode->hdisplay * mul / div; 542 543 /* horizontal sync width */ 544 hsw = (mode->hsync_end - mode->hsync_start) * mul / div; 545 546 /* horizontal back porch */ 547 hbp = (mode->htotal - mode->hsync_end) * mul / div; 548 549 /* horizontal front porch */ 550 hfp = (mode->hsync_start - mode->hdisplay) * mul / div; 551 552 if (dsi->master || dsi->slave) { 553 hact /= 2; 554 hsw /= 2; 555 hbp /= 2; 556 hfp /= 2; 557 } 558 559 if ((dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) == 0) 560 hbp += hsw; 561 562 /* subtract packet overhead */ 563 hsw -= 10; 564 hbp -= 14; 565 hfp -= 8; 566 567 tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1); 568 tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3); 569 tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5); 570 tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7); 571 } else { 572 u16 bytes; 573 574 if (dsi->master || dsi->slave) { 575 /* 576 * For ganged mode, assume symmetric left-right mode. 577 */ 578 bytes = 1 + (mode->hdisplay / 2) * mul / div; 579 } else { 580 /* 1 byte (DCS command) + pixel data */ 581 bytes = 1 + mode->hdisplay * mul / div; 582 } 583 584 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1); 585 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_2_3); 586 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_4_5); 587 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_6_7); 588 589 value = MIPI_DCS_WRITE_MEMORY_START << 8 | 590 MIPI_DCS_WRITE_MEMORY_CONTINUE; 591 tegra_dsi_writel(dsi, value, DSI_DCS_CMDS); 592 } 593 594 /* set SOL delay */ 595 if (dsi->master || dsi->slave) { 596 unsigned long delay, bclk, bclk_ganged; 597 unsigned int lanes = state->lanes; 598 599 /* SOL to valid, valid to FIFO and FIFO write delay */ 600 delay = 4 + 4 + 2; 601 delay = DIV_ROUND_UP(delay * mul, div * lanes); 602 /* FIFO read delay */ 603 delay = delay + 6; 604 605 bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes); 606 bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes); 607 value = bclk - bclk_ganged + delay + 20; 608 } else { 609 value = 8 * mul / div; 610 } 611 612 tegra_dsi_writel(dsi, value, DSI_SOL_DELAY); 613 614 if (dsi->slave) { 615 tegra_dsi_configure(dsi->slave, pipe, mode); 616 617 /* 618 * TODO: Support modes other than symmetrical left-right 619 * split. 620 */ 621 tegra_dsi_ganged_enable(dsi, 0, mode->hdisplay / 2); 622 tegra_dsi_ganged_enable(dsi->slave, mode->hdisplay / 2, 623 mode->hdisplay / 2); 624 } 625 } 626 627 static int tegra_dsi_wait_idle(struct tegra_dsi *dsi, unsigned long timeout) 628 { 629 u32 value; 630 631 timeout = jiffies + msecs_to_jiffies(timeout); 632 633 while (time_before(jiffies, timeout)) { 634 value = tegra_dsi_readl(dsi, DSI_STATUS); 635 if (value & DSI_STATUS_IDLE) 636 return 0; 637 638 usleep_range(1000, 2000); 639 } 640 641 return -ETIMEDOUT; 642 } 643 644 static void tegra_dsi_video_disable(struct tegra_dsi *dsi) 645 { 646 u32 value; 647 648 value = tegra_dsi_readl(dsi, DSI_CONTROL); 649 value &= ~DSI_CONTROL_VIDEO_ENABLE; 650 tegra_dsi_writel(dsi, value, DSI_CONTROL); 651 652 if (dsi->slave) 653 tegra_dsi_video_disable(dsi->slave); 654 } 655 656 static void tegra_dsi_ganged_disable(struct tegra_dsi *dsi) 657 { 658 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_START); 659 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_SIZE); 660 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_CONTROL); 661 } 662 663 static int tegra_dsi_pad_enable(struct tegra_dsi *dsi) 664 { 665 u32 value; 666 667 value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0); 668 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0); 669 670 return 0; 671 } 672 673 static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi) 674 { 675 u32 value; 676 int err; 677 678 /* 679 * XXX Is this still needed? The module reset is deasserted right 680 * before this function is called. 681 */ 682 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0); 683 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1); 684 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2); 685 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3); 686 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4); 687 688 /* start calibration */ 689 tegra_dsi_pad_enable(dsi); 690 691 value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) | 692 DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) | 693 DSI_PAD_OUT_CLK(0x0); 694 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2); 695 696 value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | 697 DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3); 698 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3); 699 700 err = tegra_mipi_start_calibration(dsi->mipi); 701 if (err < 0) 702 return err; 703 704 return tegra_mipi_finish_calibration(dsi->mipi); 705 } 706 707 static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk, 708 unsigned int vrefresh) 709 { 710 unsigned int timeout; 711 u32 value; 712 713 /* one frame high-speed transmission timeout */ 714 timeout = (bclk / vrefresh) / 512; 715 value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout); 716 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0); 717 718 /* 2 ms peripheral timeout for panel */ 719 timeout = 2 * bclk / 512 * 1000; 720 value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000); 721 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1); 722 723 value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0); 724 tegra_dsi_writel(dsi, value, DSI_TO_TALLY); 725 726 if (dsi->slave) 727 tegra_dsi_set_timeout(dsi->slave, bclk, vrefresh); 728 } 729 730 static void tegra_dsi_disable(struct tegra_dsi *dsi) 731 { 732 u32 value; 733 734 if (dsi->slave) { 735 tegra_dsi_ganged_disable(dsi->slave); 736 tegra_dsi_ganged_disable(dsi); 737 } 738 739 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 740 value &= ~DSI_POWER_CONTROL_ENABLE; 741 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); 742 743 if (dsi->slave) 744 tegra_dsi_disable(dsi->slave); 745 746 usleep_range(5000, 10000); 747 } 748 749 static void tegra_dsi_soft_reset(struct tegra_dsi *dsi) 750 { 751 u32 value; 752 753 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 754 value &= ~DSI_POWER_CONTROL_ENABLE; 755 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); 756 757 usleep_range(300, 1000); 758 759 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 760 value |= DSI_POWER_CONTROL_ENABLE; 761 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); 762 763 usleep_range(300, 1000); 764 765 value = tegra_dsi_readl(dsi, DSI_TRIGGER); 766 if (value) 767 tegra_dsi_writel(dsi, 0, DSI_TRIGGER); 768 769 if (dsi->slave) 770 tegra_dsi_soft_reset(dsi->slave); 771 } 772 773 static void tegra_dsi_connector_reset(struct drm_connector *connector) 774 { 775 struct tegra_dsi_state *state = kzalloc(sizeof(*state), GFP_KERNEL); 776 777 if (!state) 778 return; 779 780 if (connector->state) { 781 __drm_atomic_helper_connector_destroy_state(connector->state); 782 kfree(connector->state); 783 } 784 785 __drm_atomic_helper_connector_reset(connector, &state->base); 786 } 787 788 static struct drm_connector_state * 789 tegra_dsi_connector_duplicate_state(struct drm_connector *connector) 790 { 791 struct tegra_dsi_state *state = to_dsi_state(connector->state); 792 struct tegra_dsi_state *copy; 793 794 copy = kmemdup(state, sizeof(*state), GFP_KERNEL); 795 if (!copy) 796 return NULL; 797 798 __drm_atomic_helper_connector_duplicate_state(connector, 799 ©->base); 800 801 return ©->base; 802 } 803 804 static const struct drm_connector_funcs tegra_dsi_connector_funcs = { 805 .reset = tegra_dsi_connector_reset, 806 .detect = tegra_output_connector_detect, 807 .fill_modes = drm_helper_probe_single_connector_modes, 808 .destroy = tegra_output_connector_destroy, 809 .atomic_duplicate_state = tegra_dsi_connector_duplicate_state, 810 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 811 .late_register = tegra_dsi_late_register, 812 .early_unregister = tegra_dsi_early_unregister, 813 }; 814 815 static enum drm_mode_status 816 tegra_dsi_connector_mode_valid(struct drm_connector *connector, 817 const struct drm_display_mode *mode) 818 { 819 return MODE_OK; 820 } 821 822 static const struct drm_connector_helper_funcs tegra_dsi_connector_helper_funcs = { 823 .get_modes = tegra_output_connector_get_modes, 824 .mode_valid = tegra_dsi_connector_mode_valid, 825 }; 826 827 static void tegra_dsi_unprepare(struct tegra_dsi *dsi) 828 { 829 int err; 830 831 if (dsi->slave) 832 tegra_dsi_unprepare(dsi->slave); 833 834 err = tegra_mipi_disable(dsi->mipi); 835 if (err < 0) 836 dev_err(dsi->dev, "failed to disable MIPI calibration: %d\n", 837 err); 838 839 err = host1x_client_suspend(&dsi->client); 840 if (err < 0) 841 dev_err(dsi->dev, "failed to suspend: %d\n", err); 842 } 843 844 static void tegra_dsi_encoder_disable(struct drm_encoder *encoder) 845 { 846 struct tegra_output *output = encoder_to_output(encoder); 847 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 848 struct tegra_dsi *dsi = to_dsi(output); 849 u32 value; 850 int err; 851 852 if (output->panel) 853 drm_panel_disable(output->panel); 854 855 tegra_dsi_video_disable(dsi); 856 857 /* 858 * The following accesses registers of the display controller, so make 859 * sure it's only executed when the output is attached to one. 860 */ 861 if (dc) { 862 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 863 value &= ~DSI_ENABLE; 864 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 865 866 tegra_dc_commit(dc); 867 } 868 869 err = tegra_dsi_wait_idle(dsi, 100); 870 if (err < 0) 871 dev_dbg(dsi->dev, "failed to idle DSI: %d\n", err); 872 873 tegra_dsi_soft_reset(dsi); 874 875 if (output->panel) 876 drm_panel_unprepare(output->panel); 877 878 tegra_dsi_disable(dsi); 879 880 tegra_dsi_unprepare(dsi); 881 } 882 883 static int tegra_dsi_prepare(struct tegra_dsi *dsi) 884 { 885 int err; 886 887 err = host1x_client_resume(&dsi->client); 888 if (err < 0) { 889 dev_err(dsi->dev, "failed to resume: %d\n", err); 890 return err; 891 } 892 893 err = tegra_mipi_enable(dsi->mipi); 894 if (err < 0) 895 dev_err(dsi->dev, "failed to enable MIPI calibration: %d\n", 896 err); 897 898 err = tegra_dsi_pad_calibrate(dsi); 899 if (err < 0) 900 dev_err(dsi->dev, "MIPI calibration failed: %d\n", err); 901 902 if (dsi->slave) 903 tegra_dsi_prepare(dsi->slave); 904 905 return 0; 906 } 907 908 static void tegra_dsi_encoder_enable(struct drm_encoder *encoder) 909 { 910 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 911 struct tegra_output *output = encoder_to_output(encoder); 912 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 913 struct tegra_dsi *dsi = to_dsi(output); 914 struct tegra_dsi_state *state; 915 u32 value; 916 int err; 917 918 /* If the bootloader enabled DSI it needs to be disabled 919 * in order for the panel initialization commands to be 920 * properly sent. 921 */ 922 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 923 924 if (value & DSI_POWER_CONTROL_ENABLE) 925 tegra_dsi_disable(dsi); 926 927 err = tegra_dsi_prepare(dsi); 928 if (err < 0) { 929 dev_err(dsi->dev, "failed to prepare: %d\n", err); 930 return; 931 } 932 933 state = tegra_dsi_get_state(dsi); 934 935 tegra_dsi_set_timeout(dsi, state->bclk, state->vrefresh); 936 937 /* 938 * The D-PHY timing fields are expressed in byte-clock cycles, so 939 * multiply the period by 8. 940 */ 941 tegra_dsi_set_phy_timing(dsi, state->period * 8, &state->timing); 942 943 if (output->panel) 944 drm_panel_prepare(output->panel); 945 946 tegra_dsi_configure(dsi, dc->pipe, mode); 947 948 /* enable display controller */ 949 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 950 value |= DSI_ENABLE; 951 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 952 953 tegra_dc_commit(dc); 954 955 /* enable DSI controller */ 956 tegra_dsi_enable(dsi); 957 958 if (output->panel) 959 drm_panel_enable(output->panel); 960 } 961 962 static int 963 tegra_dsi_encoder_atomic_check(struct drm_encoder *encoder, 964 struct drm_crtc_state *crtc_state, 965 struct drm_connector_state *conn_state) 966 { 967 struct tegra_output *output = encoder_to_output(encoder); 968 struct tegra_dsi_state *state = to_dsi_state(conn_state); 969 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc); 970 struct tegra_dsi *dsi = to_dsi(output); 971 unsigned int scdiv; 972 unsigned long plld; 973 int err; 974 975 state->pclk = crtc_state->mode.clock * 1000; 976 977 err = tegra_dsi_get_muldiv(dsi->format, &state->mul, &state->div); 978 if (err < 0) 979 return err; 980 981 state->lanes = tegra_dsi_get_lanes(dsi); 982 983 err = tegra_dsi_get_format(dsi->format, &state->format); 984 if (err < 0) 985 return err; 986 987 state->vrefresh = drm_mode_vrefresh(&crtc_state->mode); 988 989 /* compute byte clock */ 990 state->bclk = (state->pclk * state->mul) / (state->div * state->lanes); 991 992 DRM_DEBUG_KMS("mul: %u, div: %u, lanes: %u\n", state->mul, state->div, 993 state->lanes); 994 DRM_DEBUG_KMS("format: %u, vrefresh: %u\n", state->format, 995 state->vrefresh); 996 DRM_DEBUG_KMS("bclk: %lu\n", state->bclk); 997 998 /* 999 * Compute bit clock and round up to the next MHz. 1000 */ 1001 plld = DIV_ROUND_UP(state->bclk * 8, USEC_PER_SEC) * USEC_PER_SEC; 1002 state->period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, plld); 1003 1004 err = mipi_dphy_timing_get_default(&state->timing, state->period); 1005 if (err < 0) 1006 return err; 1007 1008 err = mipi_dphy_timing_validate(&state->timing, state->period); 1009 if (err < 0) { 1010 dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err); 1011 return err; 1012 } 1013 1014 /* 1015 * We divide the frequency by two here, but we make up for that by 1016 * setting the shift clock divider (further below) to half of the 1017 * correct value. 1018 */ 1019 plld /= 2; 1020 1021 /* 1022 * Derive pixel clock from bit clock using the shift clock divider. 1023 * Note that this is only half of what we would expect, but we need 1024 * that to make up for the fact that we divided the bit clock by a 1025 * factor of two above. 1026 * 1027 * It's not clear exactly why this is necessary, but the display is 1028 * not working properly otherwise. Perhaps the PLLs cannot generate 1029 * frequencies sufficiently high. 1030 */ 1031 scdiv = ((8 * state->mul) / (state->div * state->lanes)) - 2; 1032 1033 err = tegra_dc_state_setup_clock(dc, crtc_state, dsi->clk_parent, 1034 plld, scdiv); 1035 if (err < 0) { 1036 dev_err(output->dev, "failed to setup CRTC state: %d\n", err); 1037 return err; 1038 } 1039 1040 return err; 1041 } 1042 1043 static const struct drm_encoder_helper_funcs tegra_dsi_encoder_helper_funcs = { 1044 .disable = tegra_dsi_encoder_disable, 1045 .enable = tegra_dsi_encoder_enable, 1046 .atomic_check = tegra_dsi_encoder_atomic_check, 1047 }; 1048 1049 static int tegra_dsi_init(struct host1x_client *client) 1050 { 1051 struct drm_device *drm = dev_get_drvdata(client->host); 1052 struct tegra_dsi *dsi = host1x_client_to_dsi(client); 1053 int err; 1054 1055 /* Gangsters must not register their own outputs. */ 1056 if (!dsi->master) { 1057 dsi->output.dev = client->dev; 1058 1059 drm_connector_init(drm, &dsi->output.connector, 1060 &tegra_dsi_connector_funcs, 1061 DRM_MODE_CONNECTOR_DSI); 1062 drm_connector_helper_add(&dsi->output.connector, 1063 &tegra_dsi_connector_helper_funcs); 1064 dsi->output.connector.dpms = DRM_MODE_DPMS_OFF; 1065 1066 drm_simple_encoder_init(drm, &dsi->output.encoder, 1067 DRM_MODE_ENCODER_DSI); 1068 drm_encoder_helper_add(&dsi->output.encoder, 1069 &tegra_dsi_encoder_helper_funcs); 1070 1071 drm_connector_attach_encoder(&dsi->output.connector, 1072 &dsi->output.encoder); 1073 drm_connector_register(&dsi->output.connector); 1074 1075 err = tegra_output_init(drm, &dsi->output); 1076 if (err < 0) 1077 dev_err(dsi->dev, "failed to initialize output: %d\n", 1078 err); 1079 1080 dsi->output.encoder.possible_crtcs = 0x3; 1081 } 1082 1083 return 0; 1084 } 1085 1086 static int tegra_dsi_exit(struct host1x_client *client) 1087 { 1088 struct tegra_dsi *dsi = host1x_client_to_dsi(client); 1089 1090 tegra_output_exit(&dsi->output); 1091 1092 return 0; 1093 } 1094 1095 static int tegra_dsi_runtime_suspend(struct host1x_client *client) 1096 { 1097 struct tegra_dsi *dsi = host1x_client_to_dsi(client); 1098 struct device *dev = client->dev; 1099 int err; 1100 1101 if (dsi->rst) { 1102 err = reset_control_assert(dsi->rst); 1103 if (err < 0) { 1104 dev_err(dev, "failed to assert reset: %d\n", err); 1105 return err; 1106 } 1107 } 1108 1109 usleep_range(1000, 2000); 1110 1111 clk_disable_unprepare(dsi->clk_lp); 1112 clk_disable_unprepare(dsi->clk); 1113 1114 regulator_disable(dsi->vdd); 1115 pm_runtime_put_sync(dev); 1116 1117 return 0; 1118 } 1119 1120 static int tegra_dsi_runtime_resume(struct host1x_client *client) 1121 { 1122 struct tegra_dsi *dsi = host1x_client_to_dsi(client); 1123 struct device *dev = client->dev; 1124 int err; 1125 1126 err = pm_runtime_resume_and_get(dev); 1127 if (err < 0) { 1128 dev_err(dev, "failed to get runtime PM: %d\n", err); 1129 return err; 1130 } 1131 1132 err = regulator_enable(dsi->vdd); 1133 if (err < 0) { 1134 dev_err(dev, "failed to enable VDD supply: %d\n", err); 1135 goto put_rpm; 1136 } 1137 1138 err = clk_prepare_enable(dsi->clk); 1139 if (err < 0) { 1140 dev_err(dev, "cannot enable DSI clock: %d\n", err); 1141 goto disable_vdd; 1142 } 1143 1144 err = clk_prepare_enable(dsi->clk_lp); 1145 if (err < 0) { 1146 dev_err(dev, "cannot enable low-power clock: %d\n", err); 1147 goto disable_clk; 1148 } 1149 1150 usleep_range(1000, 2000); 1151 1152 if (dsi->rst) { 1153 err = reset_control_deassert(dsi->rst); 1154 if (err < 0) { 1155 dev_err(dev, "cannot assert reset: %d\n", err); 1156 goto disable_clk_lp; 1157 } 1158 } 1159 1160 return 0; 1161 1162 disable_clk_lp: 1163 clk_disable_unprepare(dsi->clk_lp); 1164 disable_clk: 1165 clk_disable_unprepare(dsi->clk); 1166 disable_vdd: 1167 regulator_disable(dsi->vdd); 1168 put_rpm: 1169 pm_runtime_put_sync(dev); 1170 return err; 1171 } 1172 1173 static const struct host1x_client_ops dsi_client_ops = { 1174 .init = tegra_dsi_init, 1175 .exit = tegra_dsi_exit, 1176 .suspend = tegra_dsi_runtime_suspend, 1177 .resume = tegra_dsi_runtime_resume, 1178 }; 1179 1180 static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi) 1181 { 1182 struct clk *parent; 1183 int err; 1184 1185 parent = clk_get_parent(dsi->clk); 1186 if (!parent) 1187 return -EINVAL; 1188 1189 err = clk_set_parent(parent, dsi->clk_parent); 1190 if (err < 0) 1191 return err; 1192 1193 return 0; 1194 } 1195 1196 static const char * const error_report[16] = { 1197 "SoT Error", 1198 "SoT Sync Error", 1199 "EoT Sync Error", 1200 "Escape Mode Entry Command Error", 1201 "Low-Power Transmit Sync Error", 1202 "Peripheral Timeout Error", 1203 "False Control Error", 1204 "Contention Detected", 1205 "ECC Error, single-bit", 1206 "ECC Error, multi-bit", 1207 "Checksum Error", 1208 "DSI Data Type Not Recognized", 1209 "DSI VC ID Invalid", 1210 "Invalid Transmission Length", 1211 "Reserved", 1212 "DSI Protocol Violation", 1213 }; 1214 1215 static ssize_t tegra_dsi_read_response(struct tegra_dsi *dsi, 1216 const struct mipi_dsi_msg *msg, 1217 size_t count) 1218 { 1219 u8 *rx = msg->rx_buf; 1220 unsigned int i, j, k; 1221 size_t size = 0; 1222 u16 errors; 1223 u32 value; 1224 1225 /* read and parse packet header */ 1226 value = tegra_dsi_readl(dsi, DSI_RD_DATA); 1227 1228 switch (value & 0x3f) { 1229 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 1230 errors = (value >> 8) & 0xffff; 1231 dev_dbg(dsi->dev, "Acknowledge and error report: %04x\n", 1232 errors); 1233 for (i = 0; i < ARRAY_SIZE(error_report); i++) 1234 if (errors & BIT(i)) 1235 dev_dbg(dsi->dev, " %2u: %s\n", i, 1236 error_report[i]); 1237 break; 1238 1239 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 1240 rx[0] = (value >> 8) & 0xff; 1241 size = 1; 1242 break; 1243 1244 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 1245 rx[0] = (value >> 8) & 0xff; 1246 rx[1] = (value >> 16) & 0xff; 1247 size = 2; 1248 break; 1249 1250 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE: 1251 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff); 1252 break; 1253 1254 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE: 1255 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff); 1256 break; 1257 1258 default: 1259 dev_err(dsi->dev, "unhandled response type: %02x\n", 1260 value & 0x3f); 1261 return -EPROTO; 1262 } 1263 1264 size = min(size, msg->rx_len); 1265 1266 if (msg->rx_buf && size > 0) { 1267 for (i = 0, j = 0; i < count - 1; i++, j += 4) { 1268 u8 *rx = msg->rx_buf + j; 1269 1270 value = tegra_dsi_readl(dsi, DSI_RD_DATA); 1271 1272 for (k = 0; k < 4 && (j + k) < msg->rx_len; k++) 1273 rx[j + k] = (value >> (k << 3)) & 0xff; 1274 } 1275 } 1276 1277 return size; 1278 } 1279 1280 static int tegra_dsi_transmit(struct tegra_dsi *dsi, unsigned long timeout) 1281 { 1282 tegra_dsi_writel(dsi, DSI_TRIGGER_HOST, DSI_TRIGGER); 1283 1284 timeout = jiffies + msecs_to_jiffies(timeout); 1285 1286 while (time_before(jiffies, timeout)) { 1287 u32 value = tegra_dsi_readl(dsi, DSI_TRIGGER); 1288 if ((value & DSI_TRIGGER_HOST) == 0) 1289 return 0; 1290 1291 usleep_range(1000, 2000); 1292 } 1293 1294 DRM_DEBUG_KMS("timeout waiting for transmission to complete\n"); 1295 return -ETIMEDOUT; 1296 } 1297 1298 static int tegra_dsi_wait_for_response(struct tegra_dsi *dsi, 1299 unsigned long timeout) 1300 { 1301 timeout = jiffies + msecs_to_jiffies(250); 1302 1303 while (time_before(jiffies, timeout)) { 1304 u32 value = tegra_dsi_readl(dsi, DSI_STATUS); 1305 u8 count = value & 0x1f; 1306 1307 if (count > 0) 1308 return count; 1309 1310 usleep_range(1000, 2000); 1311 } 1312 1313 DRM_DEBUG_KMS("peripheral returned no data\n"); 1314 return -ETIMEDOUT; 1315 } 1316 1317 static void tegra_dsi_writesl(struct tegra_dsi *dsi, unsigned long offset, 1318 const void *buffer, size_t size) 1319 { 1320 const u8 *buf = buffer; 1321 size_t i, j; 1322 u32 value; 1323 1324 for (j = 0; j < size; j += 4) { 1325 value = 0; 1326 1327 for (i = 0; i < 4 && j + i < size; i++) 1328 value |= buf[j + i] << (i << 3); 1329 1330 tegra_dsi_writel(dsi, value, DSI_WR_DATA); 1331 } 1332 } 1333 1334 static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host, 1335 const struct mipi_dsi_msg *msg) 1336 { 1337 struct tegra_dsi *dsi = host_to_tegra(host); 1338 struct mipi_dsi_packet packet; 1339 const u8 *header; 1340 size_t count; 1341 ssize_t err; 1342 u32 value; 1343 1344 err = mipi_dsi_create_packet(&packet, msg); 1345 if (err < 0) 1346 return err; 1347 1348 header = packet.header; 1349 1350 /* maximum FIFO depth is 1920 words */ 1351 if (packet.size > dsi->video_fifo_depth * 4) 1352 return -ENOSPC; 1353 1354 /* reset underflow/overflow flags */ 1355 value = tegra_dsi_readl(dsi, DSI_STATUS); 1356 if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) { 1357 value = DSI_HOST_CONTROL_FIFO_RESET; 1358 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); 1359 usleep_range(10, 20); 1360 } 1361 1362 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 1363 value |= DSI_POWER_CONTROL_ENABLE; 1364 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); 1365 1366 usleep_range(5000, 10000); 1367 1368 value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | 1369 DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC; 1370 1371 if ((msg->flags & MIPI_DSI_MSG_USE_LPM) == 0) 1372 value |= DSI_HOST_CONTROL_HS; 1373 1374 /* 1375 * The host FIFO has a maximum of 64 words, so larger transmissions 1376 * need to use the video FIFO. 1377 */ 1378 if (packet.size > dsi->host_fifo_depth * 4) 1379 value |= DSI_HOST_CONTROL_FIFO_SEL; 1380 1381 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); 1382 1383 /* 1384 * For reads and messages with explicitly requested ACK, generate a 1385 * BTA sequence after the transmission of the packet. 1386 */ 1387 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) || 1388 (msg->rx_buf && msg->rx_len > 0)) { 1389 value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL); 1390 value |= DSI_HOST_CONTROL_PKT_BTA; 1391 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); 1392 } 1393 1394 value = DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE; 1395 tegra_dsi_writel(dsi, value, DSI_CONTROL); 1396 1397 /* write packet header, ECC is generated by hardware */ 1398 value = header[2] << 16 | header[1] << 8 | header[0]; 1399 tegra_dsi_writel(dsi, value, DSI_WR_DATA); 1400 1401 /* write payload (if any) */ 1402 if (packet.payload_length > 0) 1403 tegra_dsi_writesl(dsi, DSI_WR_DATA, packet.payload, 1404 packet.payload_length); 1405 1406 err = tegra_dsi_transmit(dsi, 250); 1407 if (err < 0) 1408 return err; 1409 1410 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) || 1411 (msg->rx_buf && msg->rx_len > 0)) { 1412 err = tegra_dsi_wait_for_response(dsi, 250); 1413 if (err < 0) 1414 return err; 1415 1416 count = err; 1417 1418 value = tegra_dsi_readl(dsi, DSI_RD_DATA); 1419 switch (value) { 1420 case 0x84: 1421 /* 1422 dev_dbg(dsi->dev, "ACK\n"); 1423 */ 1424 break; 1425 1426 case 0x87: 1427 /* 1428 dev_dbg(dsi->dev, "ESCAPE\n"); 1429 */ 1430 break; 1431 1432 default: 1433 dev_err(dsi->dev, "unknown status: %08x\n", value); 1434 break; 1435 } 1436 1437 if (count > 1) { 1438 err = tegra_dsi_read_response(dsi, msg, count); 1439 if (err < 0) 1440 dev_err(dsi->dev, 1441 "failed to parse response: %zd\n", 1442 err); 1443 else { 1444 /* 1445 * For read commands, return the number of 1446 * bytes returned by the peripheral. 1447 */ 1448 count = err; 1449 } 1450 } 1451 } else { 1452 /* 1453 * For write commands, we have transmitted the 4-byte header 1454 * plus the variable-length payload. 1455 */ 1456 count = 4 + packet.payload_length; 1457 } 1458 1459 return count; 1460 } 1461 1462 static int tegra_dsi_ganged_setup(struct tegra_dsi *dsi) 1463 { 1464 struct clk *parent; 1465 int err; 1466 1467 /* make sure both DSI controllers share the same PLL */ 1468 parent = clk_get_parent(dsi->slave->clk); 1469 if (!parent) 1470 return -EINVAL; 1471 1472 err = clk_set_parent(parent, dsi->clk_parent); 1473 if (err < 0) 1474 return err; 1475 1476 return 0; 1477 } 1478 1479 static int tegra_dsi_host_attach(struct mipi_dsi_host *host, 1480 struct mipi_dsi_device *device) 1481 { 1482 struct tegra_dsi *dsi = host_to_tegra(host); 1483 1484 dsi->flags = device->mode_flags; 1485 dsi->format = device->format; 1486 dsi->lanes = device->lanes; 1487 1488 if (dsi->slave) { 1489 int err; 1490 1491 dev_dbg(dsi->dev, "attaching dual-channel device %s\n", 1492 dev_name(&device->dev)); 1493 1494 err = tegra_dsi_ganged_setup(dsi); 1495 if (err < 0) { 1496 dev_err(dsi->dev, "failed to set up ganged mode: %d\n", 1497 err); 1498 return err; 1499 } 1500 } 1501 1502 /* 1503 * Slaves don't have a panel associated with them, so they provide 1504 * merely the second channel. 1505 */ 1506 if (!dsi->master) { 1507 struct tegra_output *output = &dsi->output; 1508 1509 output->panel = of_drm_find_panel(device->dev.of_node); 1510 if (IS_ERR(output->panel)) 1511 output->panel = NULL; 1512 1513 if (output->panel && output->connector.dev) 1514 drm_helper_hpd_irq_event(output->connector.dev); 1515 } 1516 1517 return 0; 1518 } 1519 1520 static int tegra_dsi_host_detach(struct mipi_dsi_host *host, 1521 struct mipi_dsi_device *device) 1522 { 1523 struct tegra_dsi *dsi = host_to_tegra(host); 1524 struct tegra_output *output = &dsi->output; 1525 1526 if (output->panel && &device->dev == output->panel->dev) { 1527 output->panel = NULL; 1528 1529 if (output->connector.dev) 1530 drm_helper_hpd_irq_event(output->connector.dev); 1531 } 1532 1533 return 0; 1534 } 1535 1536 static const struct mipi_dsi_host_ops tegra_dsi_host_ops = { 1537 .attach = tegra_dsi_host_attach, 1538 .detach = tegra_dsi_host_detach, 1539 .transfer = tegra_dsi_host_transfer, 1540 }; 1541 1542 static int tegra_dsi_ganged_probe(struct tegra_dsi *dsi) 1543 { 1544 struct device_node *np; 1545 1546 np = of_parse_phandle(dsi->dev->of_node, "nvidia,ganged-mode", 0); 1547 if (np) { 1548 struct platform_device *gangster = of_find_device_by_node(np); 1549 of_node_put(np); 1550 if (!gangster) 1551 return -EPROBE_DEFER; 1552 1553 dsi->slave = platform_get_drvdata(gangster); 1554 1555 if (!dsi->slave) { 1556 put_device(&gangster->dev); 1557 return -EPROBE_DEFER; 1558 } 1559 1560 dsi->slave->master = dsi; 1561 } 1562 1563 return 0; 1564 } 1565 1566 static int tegra_dsi_probe(struct platform_device *pdev) 1567 { 1568 struct tegra_dsi *dsi; 1569 int err; 1570 1571 dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL); 1572 if (!dsi) 1573 return -ENOMEM; 1574 1575 dsi->output.dev = dsi->dev = &pdev->dev; 1576 dsi->video_fifo_depth = 1920; 1577 dsi->host_fifo_depth = 64; 1578 1579 err = tegra_dsi_ganged_probe(dsi); 1580 if (err < 0) 1581 return err; 1582 1583 err = tegra_output_probe(&dsi->output); 1584 if (err < 0) 1585 return err; 1586 1587 dsi->output.connector.polled = DRM_CONNECTOR_POLL_HPD; 1588 1589 /* 1590 * Assume these values by default. When a DSI peripheral driver 1591 * attaches to the DSI host, the parameters will be taken from 1592 * the attached device. 1593 */ 1594 dsi->flags = MIPI_DSI_MODE_VIDEO; 1595 dsi->format = MIPI_DSI_FMT_RGB888; 1596 dsi->lanes = 4; 1597 1598 if (!pdev->dev.pm_domain) { 1599 dsi->rst = devm_reset_control_get(&pdev->dev, "dsi"); 1600 if (IS_ERR(dsi->rst)) { 1601 err = PTR_ERR(dsi->rst); 1602 goto remove; 1603 } 1604 } 1605 1606 dsi->clk = devm_clk_get(&pdev->dev, NULL); 1607 if (IS_ERR(dsi->clk)) { 1608 err = dev_err_probe(&pdev->dev, PTR_ERR(dsi->clk), 1609 "cannot get DSI clock\n"); 1610 goto remove; 1611 } 1612 1613 dsi->clk_lp = devm_clk_get(&pdev->dev, "lp"); 1614 if (IS_ERR(dsi->clk_lp)) { 1615 err = dev_err_probe(&pdev->dev, PTR_ERR(dsi->clk_lp), 1616 "cannot get low-power clock\n"); 1617 goto remove; 1618 } 1619 1620 dsi->clk_parent = devm_clk_get(&pdev->dev, "parent"); 1621 if (IS_ERR(dsi->clk_parent)) { 1622 err = dev_err_probe(&pdev->dev, PTR_ERR(dsi->clk_parent), 1623 "cannot get parent clock\n"); 1624 goto remove; 1625 } 1626 1627 dsi->vdd = devm_regulator_get(&pdev->dev, "avdd-dsi-csi"); 1628 if (IS_ERR(dsi->vdd)) { 1629 err = dev_err_probe(&pdev->dev, PTR_ERR(dsi->vdd), 1630 "cannot get VDD supply\n"); 1631 goto remove; 1632 } 1633 1634 err = tegra_dsi_setup_clocks(dsi); 1635 if (err < 0) { 1636 dev_err(&pdev->dev, "cannot setup clocks\n"); 1637 goto remove; 1638 } 1639 1640 dsi->regs = devm_platform_ioremap_resource(pdev, 0); 1641 if (IS_ERR(dsi->regs)) { 1642 err = PTR_ERR(dsi->regs); 1643 goto remove; 1644 } 1645 1646 dsi->mipi = tegra_mipi_request(&pdev->dev, pdev->dev.of_node); 1647 if (IS_ERR(dsi->mipi)) { 1648 err = PTR_ERR(dsi->mipi); 1649 goto remove; 1650 } 1651 1652 dsi->host.ops = &tegra_dsi_host_ops; 1653 dsi->host.dev = &pdev->dev; 1654 1655 err = mipi_dsi_host_register(&dsi->host); 1656 if (err < 0) { 1657 dev_err(&pdev->dev, "failed to register DSI host: %d\n", err); 1658 goto mipi_free; 1659 } 1660 1661 platform_set_drvdata(pdev, dsi); 1662 pm_runtime_enable(&pdev->dev); 1663 1664 INIT_LIST_HEAD(&dsi->client.list); 1665 dsi->client.ops = &dsi_client_ops; 1666 dsi->client.dev = &pdev->dev; 1667 1668 err = host1x_client_register(&dsi->client); 1669 if (err < 0) { 1670 dev_err(&pdev->dev, "failed to register host1x client: %d\n", 1671 err); 1672 goto unregister; 1673 } 1674 1675 return 0; 1676 1677 unregister: 1678 pm_runtime_disable(&pdev->dev); 1679 mipi_dsi_host_unregister(&dsi->host); 1680 mipi_free: 1681 tegra_mipi_free(dsi->mipi); 1682 remove: 1683 tegra_output_remove(&dsi->output); 1684 return err; 1685 } 1686 1687 static void tegra_dsi_remove(struct platform_device *pdev) 1688 { 1689 struct tegra_dsi *dsi = platform_get_drvdata(pdev); 1690 1691 pm_runtime_disable(&pdev->dev); 1692 1693 host1x_client_unregister(&dsi->client); 1694 1695 tegra_output_remove(&dsi->output); 1696 1697 mipi_dsi_host_unregister(&dsi->host); 1698 tegra_mipi_free(dsi->mipi); 1699 } 1700 1701 static const struct of_device_id tegra_dsi_of_match[] = { 1702 { .compatible = "nvidia,tegra210-dsi", }, 1703 { .compatible = "nvidia,tegra132-dsi", }, 1704 { .compatible = "nvidia,tegra124-dsi", }, 1705 { .compatible = "nvidia,tegra114-dsi", }, 1706 { }, 1707 }; 1708 MODULE_DEVICE_TABLE(of, tegra_dsi_of_match); 1709 1710 struct platform_driver tegra_dsi_driver = { 1711 .driver = { 1712 .name = "tegra-dsi", 1713 .of_match_table = tegra_dsi_of_match, 1714 }, 1715 .probe = tegra_dsi_probe, 1716 .remove = tegra_dsi_remove, 1717 }; 1718