xref: /linux/drivers/gpu/drm/tegra/dsi.c (revision a8fe58cec351c25e09c393bf46117c0c47b5a17c)
1 /*
2  * Copyright (C) 2013 NVIDIA Corporation
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  */
8 
9 #include <linux/clk.h>
10 #include <linux/debugfs.h>
11 #include <linux/host1x.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/of_platform.h>
15 #include <linux/platform_device.h>
16 #include <linux/reset.h>
17 
18 #include <linux/regulator/consumer.h>
19 
20 #include <drm/drm_atomic_helper.h>
21 #include <drm/drm_mipi_dsi.h>
22 #include <drm/drm_panel.h>
23 
24 #include <video/mipi_display.h>
25 
26 #include "dc.h"
27 #include "drm.h"
28 #include "dsi.h"
29 #include "mipi-phy.h"
30 
31 struct tegra_dsi_state {
32 	struct drm_connector_state base;
33 
34 	struct mipi_dphy_timing timing;
35 	unsigned long period;
36 
37 	unsigned int vrefresh;
38 	unsigned int lanes;
39 	unsigned long pclk;
40 	unsigned long bclk;
41 
42 	enum tegra_dsi_format format;
43 	unsigned int mul;
44 	unsigned int div;
45 };
46 
47 static inline struct tegra_dsi_state *
48 to_dsi_state(struct drm_connector_state *state)
49 {
50 	return container_of(state, struct tegra_dsi_state, base);
51 }
52 
53 struct tegra_dsi {
54 	struct host1x_client client;
55 	struct tegra_output output;
56 	struct device *dev;
57 
58 	void __iomem *regs;
59 
60 	struct reset_control *rst;
61 	struct clk *clk_parent;
62 	struct clk *clk_lp;
63 	struct clk *clk;
64 
65 	struct drm_info_list *debugfs_files;
66 	struct drm_minor *minor;
67 	struct dentry *debugfs;
68 
69 	unsigned long flags;
70 	enum mipi_dsi_pixel_format format;
71 	unsigned int lanes;
72 
73 	struct tegra_mipi_device *mipi;
74 	struct mipi_dsi_host host;
75 
76 	struct regulator *vdd;
77 
78 	unsigned int video_fifo_depth;
79 	unsigned int host_fifo_depth;
80 
81 	/* for ganged-mode support */
82 	struct tegra_dsi *master;
83 	struct tegra_dsi *slave;
84 };
85 
86 static inline struct tegra_dsi *
87 host1x_client_to_dsi(struct host1x_client *client)
88 {
89 	return container_of(client, struct tegra_dsi, client);
90 }
91 
92 static inline struct tegra_dsi *host_to_tegra(struct mipi_dsi_host *host)
93 {
94 	return container_of(host, struct tegra_dsi, host);
95 }
96 
97 static inline struct tegra_dsi *to_dsi(struct tegra_output *output)
98 {
99 	return container_of(output, struct tegra_dsi, output);
100 }
101 
102 static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi)
103 {
104 	return to_dsi_state(dsi->output.connector.state);
105 }
106 
107 static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned long reg)
108 {
109 	return readl(dsi->regs + (reg << 2));
110 }
111 
112 static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value,
113 				    unsigned long reg)
114 {
115 	writel(value, dsi->regs + (reg << 2));
116 }
117 
118 static int tegra_dsi_show_regs(struct seq_file *s, void *data)
119 {
120 	struct drm_info_node *node = s->private;
121 	struct tegra_dsi *dsi = node->info_ent->data;
122 	struct drm_crtc *crtc = dsi->output.encoder.crtc;
123 	struct drm_device *drm = node->minor->dev;
124 	int err = 0;
125 
126 	drm_modeset_lock_all(drm);
127 
128 	if (!crtc || !crtc->state->active) {
129 		err = -EBUSY;
130 		goto unlock;
131 	}
132 
133 #define DUMP_REG(name)						\
134 	seq_printf(s, "%-32s %#05x %08x\n", #name, name,	\
135 		   tegra_dsi_readl(dsi, name))
136 
137 	DUMP_REG(DSI_INCR_SYNCPT);
138 	DUMP_REG(DSI_INCR_SYNCPT_CONTROL);
139 	DUMP_REG(DSI_INCR_SYNCPT_ERROR);
140 	DUMP_REG(DSI_CTXSW);
141 	DUMP_REG(DSI_RD_DATA);
142 	DUMP_REG(DSI_WR_DATA);
143 	DUMP_REG(DSI_POWER_CONTROL);
144 	DUMP_REG(DSI_INT_ENABLE);
145 	DUMP_REG(DSI_INT_STATUS);
146 	DUMP_REG(DSI_INT_MASK);
147 	DUMP_REG(DSI_HOST_CONTROL);
148 	DUMP_REG(DSI_CONTROL);
149 	DUMP_REG(DSI_SOL_DELAY);
150 	DUMP_REG(DSI_MAX_THRESHOLD);
151 	DUMP_REG(DSI_TRIGGER);
152 	DUMP_REG(DSI_TX_CRC);
153 	DUMP_REG(DSI_STATUS);
154 
155 	DUMP_REG(DSI_INIT_SEQ_CONTROL);
156 	DUMP_REG(DSI_INIT_SEQ_DATA_0);
157 	DUMP_REG(DSI_INIT_SEQ_DATA_1);
158 	DUMP_REG(DSI_INIT_SEQ_DATA_2);
159 	DUMP_REG(DSI_INIT_SEQ_DATA_3);
160 	DUMP_REG(DSI_INIT_SEQ_DATA_4);
161 	DUMP_REG(DSI_INIT_SEQ_DATA_5);
162 	DUMP_REG(DSI_INIT_SEQ_DATA_6);
163 	DUMP_REG(DSI_INIT_SEQ_DATA_7);
164 
165 	DUMP_REG(DSI_PKT_SEQ_0_LO);
166 	DUMP_REG(DSI_PKT_SEQ_0_HI);
167 	DUMP_REG(DSI_PKT_SEQ_1_LO);
168 	DUMP_REG(DSI_PKT_SEQ_1_HI);
169 	DUMP_REG(DSI_PKT_SEQ_2_LO);
170 	DUMP_REG(DSI_PKT_SEQ_2_HI);
171 	DUMP_REG(DSI_PKT_SEQ_3_LO);
172 	DUMP_REG(DSI_PKT_SEQ_3_HI);
173 	DUMP_REG(DSI_PKT_SEQ_4_LO);
174 	DUMP_REG(DSI_PKT_SEQ_4_HI);
175 	DUMP_REG(DSI_PKT_SEQ_5_LO);
176 	DUMP_REG(DSI_PKT_SEQ_5_HI);
177 
178 	DUMP_REG(DSI_DCS_CMDS);
179 
180 	DUMP_REG(DSI_PKT_LEN_0_1);
181 	DUMP_REG(DSI_PKT_LEN_2_3);
182 	DUMP_REG(DSI_PKT_LEN_4_5);
183 	DUMP_REG(DSI_PKT_LEN_6_7);
184 
185 	DUMP_REG(DSI_PHY_TIMING_0);
186 	DUMP_REG(DSI_PHY_TIMING_1);
187 	DUMP_REG(DSI_PHY_TIMING_2);
188 	DUMP_REG(DSI_BTA_TIMING);
189 
190 	DUMP_REG(DSI_TIMEOUT_0);
191 	DUMP_REG(DSI_TIMEOUT_1);
192 	DUMP_REG(DSI_TO_TALLY);
193 
194 	DUMP_REG(DSI_PAD_CONTROL_0);
195 	DUMP_REG(DSI_PAD_CONTROL_CD);
196 	DUMP_REG(DSI_PAD_CD_STATUS);
197 	DUMP_REG(DSI_VIDEO_MODE_CONTROL);
198 	DUMP_REG(DSI_PAD_CONTROL_1);
199 	DUMP_REG(DSI_PAD_CONTROL_2);
200 	DUMP_REG(DSI_PAD_CONTROL_3);
201 	DUMP_REG(DSI_PAD_CONTROL_4);
202 
203 	DUMP_REG(DSI_GANGED_MODE_CONTROL);
204 	DUMP_REG(DSI_GANGED_MODE_START);
205 	DUMP_REG(DSI_GANGED_MODE_SIZE);
206 
207 	DUMP_REG(DSI_RAW_DATA_BYTE_COUNT);
208 	DUMP_REG(DSI_ULTRA_LOW_POWER_CONTROL);
209 
210 	DUMP_REG(DSI_INIT_SEQ_DATA_8);
211 	DUMP_REG(DSI_INIT_SEQ_DATA_9);
212 	DUMP_REG(DSI_INIT_SEQ_DATA_10);
213 	DUMP_REG(DSI_INIT_SEQ_DATA_11);
214 	DUMP_REG(DSI_INIT_SEQ_DATA_12);
215 	DUMP_REG(DSI_INIT_SEQ_DATA_13);
216 	DUMP_REG(DSI_INIT_SEQ_DATA_14);
217 	DUMP_REG(DSI_INIT_SEQ_DATA_15);
218 
219 #undef DUMP_REG
220 
221 unlock:
222 	drm_modeset_unlock_all(drm);
223 	return err;
224 }
225 
226 static struct drm_info_list debugfs_files[] = {
227 	{ "regs", tegra_dsi_show_regs, 0, NULL },
228 };
229 
230 static int tegra_dsi_debugfs_init(struct tegra_dsi *dsi,
231 				  struct drm_minor *minor)
232 {
233 	const char *name = dev_name(dsi->dev);
234 	unsigned int i;
235 	int err;
236 
237 	dsi->debugfs = debugfs_create_dir(name, minor->debugfs_root);
238 	if (!dsi->debugfs)
239 		return -ENOMEM;
240 
241 	dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
242 				     GFP_KERNEL);
243 	if (!dsi->debugfs_files) {
244 		err = -ENOMEM;
245 		goto remove;
246 	}
247 
248 	for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
249 		dsi->debugfs_files[i].data = dsi;
250 
251 	err = drm_debugfs_create_files(dsi->debugfs_files,
252 				       ARRAY_SIZE(debugfs_files),
253 				       dsi->debugfs, minor);
254 	if (err < 0)
255 		goto free;
256 
257 	dsi->minor = minor;
258 
259 	return 0;
260 
261 free:
262 	kfree(dsi->debugfs_files);
263 	dsi->debugfs_files = NULL;
264 remove:
265 	debugfs_remove(dsi->debugfs);
266 	dsi->debugfs = NULL;
267 
268 	return err;
269 }
270 
271 static void tegra_dsi_debugfs_exit(struct tegra_dsi *dsi)
272 {
273 	drm_debugfs_remove_files(dsi->debugfs_files, ARRAY_SIZE(debugfs_files),
274 				 dsi->minor);
275 	dsi->minor = NULL;
276 
277 	kfree(dsi->debugfs_files);
278 	dsi->debugfs_files = NULL;
279 
280 	debugfs_remove(dsi->debugfs);
281 	dsi->debugfs = NULL;
282 }
283 
284 #define PKT_ID0(id)	((((id) & 0x3f) <<  3) | (1 <<  9))
285 #define PKT_LEN0(len)	(((len) & 0x07) <<  0)
286 #define PKT_ID1(id)	((((id) & 0x3f) << 13) | (1 << 19))
287 #define PKT_LEN1(len)	(((len) & 0x07) << 10)
288 #define PKT_ID2(id)	((((id) & 0x3f) << 23) | (1 << 29))
289 #define PKT_LEN2(len)	(((len) & 0x07) << 20)
290 
291 #define PKT_LP		(1 << 30)
292 #define NUM_PKT_SEQ	12
293 
294 /*
295  * non-burst mode with sync pulses
296  */
297 static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = {
298 	[ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
299 	       PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
300 	       PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
301 	       PKT_LP,
302 	[ 1] = 0,
303 	[ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) |
304 	       PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
305 	       PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
306 	       PKT_LP,
307 	[ 3] = 0,
308 	[ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
309 	       PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
310 	       PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
311 	       PKT_LP,
312 	[ 5] = 0,
313 	[ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
314 	       PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
315 	       PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
316 	[ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
317 	       PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
318 	       PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
319 	[ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
320 	       PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
321 	       PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
322 	       PKT_LP,
323 	[ 9] = 0,
324 	[10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
325 	       PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
326 	       PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
327 	[11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
328 	       PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
329 	       PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
330 };
331 
332 /*
333  * non-burst mode with sync events
334  */
335 static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = {
336 	[ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
337 	       PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
338 	       PKT_LP,
339 	[ 1] = 0,
340 	[ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
341 	       PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
342 	       PKT_LP,
343 	[ 3] = 0,
344 	[ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
345 	       PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
346 	       PKT_LP,
347 	[ 5] = 0,
348 	[ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
349 	       PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
350 	       PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
351 	[ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
352 	[ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
353 	       PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
354 	       PKT_LP,
355 	[ 9] = 0,
356 	[10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
357 	       PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
358 	       PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
359 	[11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
360 };
361 
362 static const u32 pkt_seq_command_mode[NUM_PKT_SEQ] = {
363 	[ 0] = 0,
364 	[ 1] = 0,
365 	[ 2] = 0,
366 	[ 3] = 0,
367 	[ 4] = 0,
368 	[ 5] = 0,
369 	[ 6] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(3) | PKT_LP,
370 	[ 7] = 0,
371 	[ 8] = 0,
372 	[ 9] = 0,
373 	[10] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(5) | PKT_LP,
374 	[11] = 0,
375 };
376 
377 static void tegra_dsi_set_phy_timing(struct tegra_dsi *dsi,
378 				     unsigned long period,
379 				     const struct mipi_dphy_timing *timing)
380 {
381 	u32 value;
382 
383 	value = DSI_TIMING_FIELD(timing->hsexit, period, 1) << 24 |
384 		DSI_TIMING_FIELD(timing->hstrail, period, 0) << 16 |
385 		DSI_TIMING_FIELD(timing->hszero, period, 3) << 8 |
386 		DSI_TIMING_FIELD(timing->hsprepare, period, 1);
387 	tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0);
388 
389 	value = DSI_TIMING_FIELD(timing->clktrail, period, 1) << 24 |
390 		DSI_TIMING_FIELD(timing->clkpost, period, 1) << 16 |
391 		DSI_TIMING_FIELD(timing->clkzero, period, 1) << 8 |
392 		DSI_TIMING_FIELD(timing->lpx, period, 1);
393 	tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1);
394 
395 	value = DSI_TIMING_FIELD(timing->clkprepare, period, 1) << 16 |
396 		DSI_TIMING_FIELD(timing->clkpre, period, 1) << 8 |
397 		DSI_TIMING_FIELD(0xff * period, period, 0) << 0;
398 	tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2);
399 
400 	value = DSI_TIMING_FIELD(timing->taget, period, 1) << 16 |
401 		DSI_TIMING_FIELD(timing->tasure, period, 1) << 8 |
402 		DSI_TIMING_FIELD(timing->tago, period, 1);
403 	tegra_dsi_writel(dsi, value, DSI_BTA_TIMING);
404 
405 	if (dsi->slave)
406 		tegra_dsi_set_phy_timing(dsi->slave, period, timing);
407 }
408 
409 static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format,
410 				unsigned int *mulp, unsigned int *divp)
411 {
412 	switch (format) {
413 	case MIPI_DSI_FMT_RGB666_PACKED:
414 	case MIPI_DSI_FMT_RGB888:
415 		*mulp = 3;
416 		*divp = 1;
417 		break;
418 
419 	case MIPI_DSI_FMT_RGB565:
420 		*mulp = 2;
421 		*divp = 1;
422 		break;
423 
424 	case MIPI_DSI_FMT_RGB666:
425 		*mulp = 9;
426 		*divp = 4;
427 		break;
428 
429 	default:
430 		return -EINVAL;
431 	}
432 
433 	return 0;
434 }
435 
436 static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format,
437 				enum tegra_dsi_format *fmt)
438 {
439 	switch (format) {
440 	case MIPI_DSI_FMT_RGB888:
441 		*fmt = TEGRA_DSI_FORMAT_24P;
442 		break;
443 
444 	case MIPI_DSI_FMT_RGB666:
445 		*fmt = TEGRA_DSI_FORMAT_18NP;
446 		break;
447 
448 	case MIPI_DSI_FMT_RGB666_PACKED:
449 		*fmt = TEGRA_DSI_FORMAT_18P;
450 		break;
451 
452 	case MIPI_DSI_FMT_RGB565:
453 		*fmt = TEGRA_DSI_FORMAT_16P;
454 		break;
455 
456 	default:
457 		return -EINVAL;
458 	}
459 
460 	return 0;
461 }
462 
463 static void tegra_dsi_ganged_enable(struct tegra_dsi *dsi, unsigned int start,
464 				    unsigned int size)
465 {
466 	u32 value;
467 
468 	tegra_dsi_writel(dsi, start, DSI_GANGED_MODE_START);
469 	tegra_dsi_writel(dsi, size << 16 | size, DSI_GANGED_MODE_SIZE);
470 
471 	value = DSI_GANGED_MODE_CONTROL_ENABLE;
472 	tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL);
473 }
474 
475 static void tegra_dsi_enable(struct tegra_dsi *dsi)
476 {
477 	u32 value;
478 
479 	value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
480 	value |= DSI_POWER_CONTROL_ENABLE;
481 	tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
482 
483 	if (dsi->slave)
484 		tegra_dsi_enable(dsi->slave);
485 }
486 
487 static unsigned int tegra_dsi_get_lanes(struct tegra_dsi *dsi)
488 {
489 	if (dsi->master)
490 		return dsi->master->lanes + dsi->lanes;
491 
492 	if (dsi->slave)
493 		return dsi->lanes + dsi->slave->lanes;
494 
495 	return dsi->lanes;
496 }
497 
498 static void tegra_dsi_configure(struct tegra_dsi *dsi, unsigned int pipe,
499 				const struct drm_display_mode *mode)
500 {
501 	unsigned int hact, hsw, hbp, hfp, i, mul, div;
502 	struct tegra_dsi_state *state;
503 	const u32 *pkt_seq;
504 	u32 value;
505 
506 	/* XXX: pass in state into this function? */
507 	if (dsi->master)
508 		state = tegra_dsi_get_state(dsi->master);
509 	else
510 		state = tegra_dsi_get_state(dsi);
511 
512 	mul = state->mul;
513 	div = state->div;
514 
515 	if (dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
516 		DRM_DEBUG_KMS("Non-burst video mode with sync pulses\n");
517 		pkt_seq = pkt_seq_video_non_burst_sync_pulses;
518 	} else if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
519 		DRM_DEBUG_KMS("Non-burst video mode with sync events\n");
520 		pkt_seq = pkt_seq_video_non_burst_sync_events;
521 	} else {
522 		DRM_DEBUG_KMS("Command mode\n");
523 		pkt_seq = pkt_seq_command_mode;
524 	}
525 
526 	value = DSI_CONTROL_CHANNEL(0) |
527 		DSI_CONTROL_FORMAT(state->format) |
528 		DSI_CONTROL_LANES(dsi->lanes - 1) |
529 		DSI_CONTROL_SOURCE(pipe);
530 	tegra_dsi_writel(dsi, value, DSI_CONTROL);
531 
532 	tegra_dsi_writel(dsi, dsi->video_fifo_depth, DSI_MAX_THRESHOLD);
533 
534 	value = DSI_HOST_CONTROL_HS;
535 	tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
536 
537 	value = tegra_dsi_readl(dsi, DSI_CONTROL);
538 
539 	if (dsi->flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
540 		value |= DSI_CONTROL_HS_CLK_CTRL;
541 
542 	value &= ~DSI_CONTROL_TX_TRIG(3);
543 
544 	/* enable DCS commands for command mode */
545 	if (dsi->flags & MIPI_DSI_MODE_VIDEO)
546 		value &= ~DSI_CONTROL_DCS_ENABLE;
547 	else
548 		value |= DSI_CONTROL_DCS_ENABLE;
549 
550 	value |= DSI_CONTROL_VIDEO_ENABLE;
551 	value &= ~DSI_CONTROL_HOST_ENABLE;
552 	tegra_dsi_writel(dsi, value, DSI_CONTROL);
553 
554 	for (i = 0; i < NUM_PKT_SEQ; i++)
555 		tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i);
556 
557 	if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
558 		/* horizontal active pixels */
559 		hact = mode->hdisplay * mul / div;
560 
561 		/* horizontal sync width */
562 		hsw = (mode->hsync_end - mode->hsync_start) * mul / div;
563 
564 		/* horizontal back porch */
565 		hbp = (mode->htotal - mode->hsync_end) * mul / div;
566 
567 		if ((dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) == 0)
568 			hbp += hsw;
569 
570 		/* horizontal front porch */
571 		hfp = (mode->hsync_start - mode->hdisplay) * mul / div;
572 
573 		/* subtract packet overhead */
574 		hsw -= 10;
575 		hbp -= 14;
576 		hfp -= 8;
577 
578 		tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1);
579 		tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3);
580 		tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5);
581 		tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7);
582 
583 		/* set SOL delay (for non-burst mode only) */
584 		tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY);
585 
586 		/* TODO: implement ganged mode */
587 	} else {
588 		u16 bytes;
589 
590 		if (dsi->master || dsi->slave) {
591 			/*
592 			 * For ganged mode, assume symmetric left-right mode.
593 			 */
594 			bytes = 1 + (mode->hdisplay / 2) * mul / div;
595 		} else {
596 			/* 1 byte (DCS command) + pixel data */
597 			bytes = 1 + mode->hdisplay * mul / div;
598 		}
599 
600 		tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1);
601 		tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_2_3);
602 		tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_4_5);
603 		tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_6_7);
604 
605 		value = MIPI_DCS_WRITE_MEMORY_START << 8 |
606 			MIPI_DCS_WRITE_MEMORY_CONTINUE;
607 		tegra_dsi_writel(dsi, value, DSI_DCS_CMDS);
608 
609 		/* set SOL delay */
610 		if (dsi->master || dsi->slave) {
611 			unsigned long delay, bclk, bclk_ganged;
612 			unsigned int lanes = state->lanes;
613 
614 			/* SOL to valid, valid to FIFO and FIFO write delay */
615 			delay = 4 + 4 + 2;
616 			delay = DIV_ROUND_UP(delay * mul, div * lanes);
617 			/* FIFO read delay */
618 			delay = delay + 6;
619 
620 			bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes);
621 			bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes);
622 			value = bclk - bclk_ganged + delay + 20;
623 		} else {
624 			/* TODO: revisit for non-ganged mode */
625 			value = 8 * mul / div;
626 		}
627 
628 		tegra_dsi_writel(dsi, value, DSI_SOL_DELAY);
629 	}
630 
631 	if (dsi->slave) {
632 		tegra_dsi_configure(dsi->slave, pipe, mode);
633 
634 		/*
635 		 * TODO: Support modes other than symmetrical left-right
636 		 * split.
637 		 */
638 		tegra_dsi_ganged_enable(dsi, 0, mode->hdisplay / 2);
639 		tegra_dsi_ganged_enable(dsi->slave, mode->hdisplay / 2,
640 					mode->hdisplay / 2);
641 	}
642 }
643 
644 static int tegra_dsi_wait_idle(struct tegra_dsi *dsi, unsigned long timeout)
645 {
646 	u32 value;
647 
648 	timeout = jiffies + msecs_to_jiffies(timeout);
649 
650 	while (time_before(jiffies, timeout)) {
651 		value = tegra_dsi_readl(dsi, DSI_STATUS);
652 		if (value & DSI_STATUS_IDLE)
653 			return 0;
654 
655 		usleep_range(1000, 2000);
656 	}
657 
658 	return -ETIMEDOUT;
659 }
660 
661 static void tegra_dsi_video_disable(struct tegra_dsi *dsi)
662 {
663 	u32 value;
664 
665 	value = tegra_dsi_readl(dsi, DSI_CONTROL);
666 	value &= ~DSI_CONTROL_VIDEO_ENABLE;
667 	tegra_dsi_writel(dsi, value, DSI_CONTROL);
668 
669 	if (dsi->slave)
670 		tegra_dsi_video_disable(dsi->slave);
671 }
672 
673 static void tegra_dsi_ganged_disable(struct tegra_dsi *dsi)
674 {
675 	tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_START);
676 	tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_SIZE);
677 	tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_CONTROL);
678 }
679 
680 static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk,
681 				  unsigned int vrefresh)
682 {
683 	unsigned int timeout;
684 	u32 value;
685 
686 	/* one frame high-speed transmission timeout */
687 	timeout = (bclk / vrefresh) / 512;
688 	value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout);
689 	tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0);
690 
691 	/* 2 ms peripheral timeout for panel */
692 	timeout = 2 * bclk / 512 * 1000;
693 	value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000);
694 	tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1);
695 
696 	value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0);
697 	tegra_dsi_writel(dsi, value, DSI_TO_TALLY);
698 
699 	if (dsi->slave)
700 		tegra_dsi_set_timeout(dsi->slave, bclk, vrefresh);
701 }
702 
703 static void tegra_dsi_disable(struct tegra_dsi *dsi)
704 {
705 	u32 value;
706 
707 	if (dsi->slave) {
708 		tegra_dsi_ganged_disable(dsi->slave);
709 		tegra_dsi_ganged_disable(dsi);
710 	}
711 
712 	value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
713 	value &= ~DSI_POWER_CONTROL_ENABLE;
714 	tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
715 
716 	if (dsi->slave)
717 		tegra_dsi_disable(dsi->slave);
718 
719 	usleep_range(5000, 10000);
720 }
721 
722 static void tegra_dsi_soft_reset(struct tegra_dsi *dsi)
723 {
724 	u32 value;
725 
726 	value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
727 	value &= ~DSI_POWER_CONTROL_ENABLE;
728 	tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
729 
730 	usleep_range(300, 1000);
731 
732 	value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
733 	value |= DSI_POWER_CONTROL_ENABLE;
734 	tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
735 
736 	usleep_range(300, 1000);
737 
738 	value = tegra_dsi_readl(dsi, DSI_TRIGGER);
739 	if (value)
740 		tegra_dsi_writel(dsi, 0, DSI_TRIGGER);
741 
742 	if (dsi->slave)
743 		tegra_dsi_soft_reset(dsi->slave);
744 }
745 
746 static void tegra_dsi_connector_reset(struct drm_connector *connector)
747 {
748 	struct tegra_dsi_state *state =
749 		kzalloc(sizeof(*state), GFP_KERNEL);
750 
751 	if (state) {
752 		kfree(connector->state);
753 		__drm_atomic_helper_connector_reset(connector, &state->base);
754 	}
755 }
756 
757 static struct drm_connector_state *
758 tegra_dsi_connector_duplicate_state(struct drm_connector *connector)
759 {
760 	struct tegra_dsi_state *state = to_dsi_state(connector->state);
761 	struct tegra_dsi_state *copy;
762 
763 	copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
764 	if (!copy)
765 		return NULL;
766 
767 	return &copy->base;
768 }
769 
770 static const struct drm_connector_funcs tegra_dsi_connector_funcs = {
771 	.dpms = drm_atomic_helper_connector_dpms,
772 	.reset = tegra_dsi_connector_reset,
773 	.detect = tegra_output_connector_detect,
774 	.fill_modes = drm_helper_probe_single_connector_modes,
775 	.destroy = tegra_output_connector_destroy,
776 	.atomic_duplicate_state = tegra_dsi_connector_duplicate_state,
777 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
778 };
779 
780 static enum drm_mode_status
781 tegra_dsi_connector_mode_valid(struct drm_connector *connector,
782 			       struct drm_display_mode *mode)
783 {
784 	return MODE_OK;
785 }
786 
787 static const struct drm_connector_helper_funcs tegra_dsi_connector_helper_funcs = {
788 	.get_modes = tegra_output_connector_get_modes,
789 	.mode_valid = tegra_dsi_connector_mode_valid,
790 	.best_encoder = tegra_output_connector_best_encoder,
791 };
792 
793 static const struct drm_encoder_funcs tegra_dsi_encoder_funcs = {
794 	.destroy = tegra_output_encoder_destroy,
795 };
796 
797 static void tegra_dsi_encoder_disable(struct drm_encoder *encoder)
798 {
799 	struct tegra_output *output = encoder_to_output(encoder);
800 	struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
801 	struct tegra_dsi *dsi = to_dsi(output);
802 	u32 value;
803 	int err;
804 
805 	if (output->panel)
806 		drm_panel_disable(output->panel);
807 
808 	tegra_dsi_video_disable(dsi);
809 
810 	/*
811 	 * The following accesses registers of the display controller, so make
812 	 * sure it's only executed when the output is attached to one.
813 	 */
814 	if (dc) {
815 		value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
816 		value &= ~DSI_ENABLE;
817 		tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
818 
819 		tegra_dc_commit(dc);
820 	}
821 
822 	err = tegra_dsi_wait_idle(dsi, 100);
823 	if (err < 0)
824 		dev_dbg(dsi->dev, "failed to idle DSI: %d\n", err);
825 
826 	tegra_dsi_soft_reset(dsi);
827 
828 	if (output->panel)
829 		drm_panel_unprepare(output->panel);
830 
831 	tegra_dsi_disable(dsi);
832 
833 	return;
834 }
835 
836 static void tegra_dsi_encoder_enable(struct drm_encoder *encoder)
837 {
838 	struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
839 	struct tegra_output *output = encoder_to_output(encoder);
840 	struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
841 	struct tegra_dsi *dsi = to_dsi(output);
842 	struct tegra_dsi_state *state;
843 	u32 value;
844 
845 	state = tegra_dsi_get_state(dsi);
846 
847 	tegra_dsi_set_timeout(dsi, state->bclk, state->vrefresh);
848 
849 	/*
850 	 * The D-PHY timing fields are expressed in byte-clock cycles, so
851 	 * multiply the period by 8.
852 	 */
853 	tegra_dsi_set_phy_timing(dsi, state->period * 8, &state->timing);
854 
855 	if (output->panel)
856 		drm_panel_prepare(output->panel);
857 
858 	tegra_dsi_configure(dsi, dc->pipe, mode);
859 
860 	/* enable display controller */
861 	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
862 	value |= DSI_ENABLE;
863 	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
864 
865 	tegra_dc_commit(dc);
866 
867 	/* enable DSI controller */
868 	tegra_dsi_enable(dsi);
869 
870 	if (output->panel)
871 		drm_panel_enable(output->panel);
872 
873 	return;
874 }
875 
876 static int
877 tegra_dsi_encoder_atomic_check(struct drm_encoder *encoder,
878 			       struct drm_crtc_state *crtc_state,
879 			       struct drm_connector_state *conn_state)
880 {
881 	struct tegra_output *output = encoder_to_output(encoder);
882 	struct tegra_dsi_state *state = to_dsi_state(conn_state);
883 	struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
884 	struct tegra_dsi *dsi = to_dsi(output);
885 	unsigned int scdiv;
886 	unsigned long plld;
887 	int err;
888 
889 	state->pclk = crtc_state->mode.clock * 1000;
890 
891 	err = tegra_dsi_get_muldiv(dsi->format, &state->mul, &state->div);
892 	if (err < 0)
893 		return err;
894 
895 	state->lanes = tegra_dsi_get_lanes(dsi);
896 
897 	err = tegra_dsi_get_format(dsi->format, &state->format);
898 	if (err < 0)
899 		return err;
900 
901 	state->vrefresh = drm_mode_vrefresh(&crtc_state->mode);
902 
903 	/* compute byte clock */
904 	state->bclk = (state->pclk * state->mul) / (state->div * state->lanes);
905 
906 	DRM_DEBUG_KMS("mul: %u, div: %u, lanes: %u\n", state->mul, state->div,
907 		      state->lanes);
908 	DRM_DEBUG_KMS("format: %u, vrefresh: %u\n", state->format,
909 		      state->vrefresh);
910 	DRM_DEBUG_KMS("bclk: %lu\n", state->bclk);
911 
912 	/*
913 	 * Compute bit clock and round up to the next MHz.
914 	 */
915 	plld = DIV_ROUND_UP(state->bclk * 8, USEC_PER_SEC) * USEC_PER_SEC;
916 	state->period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, plld);
917 
918 	err = mipi_dphy_timing_get_default(&state->timing, state->period);
919 	if (err < 0)
920 		return err;
921 
922 	err = mipi_dphy_timing_validate(&state->timing, state->period);
923 	if (err < 0) {
924 		dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err);
925 		return err;
926 	}
927 
928 	/*
929 	 * We divide the frequency by two here, but we make up for that by
930 	 * setting the shift clock divider (further below) to half of the
931 	 * correct value.
932 	 */
933 	plld /= 2;
934 
935 	/*
936 	 * Derive pixel clock from bit clock using the shift clock divider.
937 	 * Note that this is only half of what we would expect, but we need
938 	 * that to make up for the fact that we divided the bit clock by a
939 	 * factor of two above.
940 	 *
941 	 * It's not clear exactly why this is necessary, but the display is
942 	 * not working properly otherwise. Perhaps the PLLs cannot generate
943 	 * frequencies sufficiently high.
944 	 */
945 	scdiv = ((8 * state->mul) / (state->div * state->lanes)) - 2;
946 
947 	err = tegra_dc_state_setup_clock(dc, crtc_state, dsi->clk_parent,
948 					 plld, scdiv);
949 	if (err < 0) {
950 		dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
951 		return err;
952 	}
953 
954 	return err;
955 }
956 
957 static const struct drm_encoder_helper_funcs tegra_dsi_encoder_helper_funcs = {
958 	.disable = tegra_dsi_encoder_disable,
959 	.enable = tegra_dsi_encoder_enable,
960 	.atomic_check = tegra_dsi_encoder_atomic_check,
961 };
962 
963 static int tegra_dsi_pad_enable(struct tegra_dsi *dsi)
964 {
965 	u32 value;
966 
967 	value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
968 	tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
969 
970 	return 0;
971 }
972 
973 static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi)
974 {
975 	u32 value;
976 
977 	tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
978 	tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
979 	tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
980 	tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
981 	tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
982 
983 	/* start calibration */
984 	tegra_dsi_pad_enable(dsi);
985 
986 	value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
987 		DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
988 		DSI_PAD_OUT_CLK(0x0);
989 	tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
990 
991 	value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) |
992 		DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3);
993 	tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3);
994 
995 	return tegra_mipi_calibrate(dsi->mipi);
996 }
997 
998 static int tegra_dsi_init(struct host1x_client *client)
999 {
1000 	struct drm_device *drm = dev_get_drvdata(client->parent);
1001 	struct tegra_dsi *dsi = host1x_client_to_dsi(client);
1002 	int err;
1003 
1004 	reset_control_deassert(dsi->rst);
1005 
1006 	err = tegra_dsi_pad_calibrate(dsi);
1007 	if (err < 0) {
1008 		dev_err(dsi->dev, "MIPI calibration failed: %d\n", err);
1009 		goto reset;
1010 	}
1011 
1012 	/* Gangsters must not register their own outputs. */
1013 	if (!dsi->master) {
1014 		dsi->output.dev = client->dev;
1015 
1016 		drm_connector_init(drm, &dsi->output.connector,
1017 				   &tegra_dsi_connector_funcs,
1018 				   DRM_MODE_CONNECTOR_DSI);
1019 		drm_connector_helper_add(&dsi->output.connector,
1020 					 &tegra_dsi_connector_helper_funcs);
1021 		dsi->output.connector.dpms = DRM_MODE_DPMS_OFF;
1022 
1023 		drm_encoder_init(drm, &dsi->output.encoder,
1024 				 &tegra_dsi_encoder_funcs,
1025 				 DRM_MODE_ENCODER_DSI, NULL);
1026 		drm_encoder_helper_add(&dsi->output.encoder,
1027 				       &tegra_dsi_encoder_helper_funcs);
1028 
1029 		drm_mode_connector_attach_encoder(&dsi->output.connector,
1030 						  &dsi->output.encoder);
1031 		drm_connector_register(&dsi->output.connector);
1032 
1033 		err = tegra_output_init(drm, &dsi->output);
1034 		if (err < 0) {
1035 			dev_err(client->dev,
1036 				"failed to initialize output: %d\n",
1037 				err);
1038 			goto reset;
1039 		}
1040 
1041 		dsi->output.encoder.possible_crtcs = 0x3;
1042 	}
1043 
1044 	if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1045 		err = tegra_dsi_debugfs_init(dsi, drm->primary);
1046 		if (err < 0)
1047 			dev_err(dsi->dev, "debugfs setup failed: %d\n", err);
1048 	}
1049 
1050 	return 0;
1051 
1052 reset:
1053 	reset_control_assert(dsi->rst);
1054 	return err;
1055 }
1056 
1057 static int tegra_dsi_exit(struct host1x_client *client)
1058 {
1059 	struct tegra_dsi *dsi = host1x_client_to_dsi(client);
1060 
1061 	tegra_output_exit(&dsi->output);
1062 
1063 	if (IS_ENABLED(CONFIG_DEBUG_FS))
1064 		tegra_dsi_debugfs_exit(dsi);
1065 
1066 	reset_control_assert(dsi->rst);
1067 
1068 	return 0;
1069 }
1070 
1071 static const struct host1x_client_ops dsi_client_ops = {
1072 	.init = tegra_dsi_init,
1073 	.exit = tegra_dsi_exit,
1074 };
1075 
1076 static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi)
1077 {
1078 	struct clk *parent;
1079 	int err;
1080 
1081 	parent = clk_get_parent(dsi->clk);
1082 	if (!parent)
1083 		return -EINVAL;
1084 
1085 	err = clk_set_parent(parent, dsi->clk_parent);
1086 	if (err < 0)
1087 		return err;
1088 
1089 	return 0;
1090 }
1091 
1092 static const char * const error_report[16] = {
1093 	"SoT Error",
1094 	"SoT Sync Error",
1095 	"EoT Sync Error",
1096 	"Escape Mode Entry Command Error",
1097 	"Low-Power Transmit Sync Error",
1098 	"Peripheral Timeout Error",
1099 	"False Control Error",
1100 	"Contention Detected",
1101 	"ECC Error, single-bit",
1102 	"ECC Error, multi-bit",
1103 	"Checksum Error",
1104 	"DSI Data Type Not Recognized",
1105 	"DSI VC ID Invalid",
1106 	"Invalid Transmission Length",
1107 	"Reserved",
1108 	"DSI Protocol Violation",
1109 };
1110 
1111 static ssize_t tegra_dsi_read_response(struct tegra_dsi *dsi,
1112 				       const struct mipi_dsi_msg *msg,
1113 				       size_t count)
1114 {
1115 	u8 *rx = msg->rx_buf;
1116 	unsigned int i, j, k;
1117 	size_t size = 0;
1118 	u16 errors;
1119 	u32 value;
1120 
1121 	/* read and parse packet header */
1122 	value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1123 
1124 	switch (value & 0x3f) {
1125 	case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1126 		errors = (value >> 8) & 0xffff;
1127 		dev_dbg(dsi->dev, "Acknowledge and error report: %04x\n",
1128 			errors);
1129 		for (i = 0; i < ARRAY_SIZE(error_report); i++)
1130 			if (errors & BIT(i))
1131 				dev_dbg(dsi->dev, "  %2u: %s\n", i,
1132 					error_report[i]);
1133 		break;
1134 
1135 	case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1136 		rx[0] = (value >> 8) & 0xff;
1137 		size = 1;
1138 		break;
1139 
1140 	case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
1141 		rx[0] = (value >>  8) & 0xff;
1142 		rx[1] = (value >> 16) & 0xff;
1143 		size = 2;
1144 		break;
1145 
1146 	case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
1147 		size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
1148 		break;
1149 
1150 	case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
1151 		size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
1152 		break;
1153 
1154 	default:
1155 		dev_err(dsi->dev, "unhandled response type: %02x\n",
1156 			value & 0x3f);
1157 		return -EPROTO;
1158 	}
1159 
1160 	size = min(size, msg->rx_len);
1161 
1162 	if (msg->rx_buf && size > 0) {
1163 		for (i = 0, j = 0; i < count - 1; i++, j += 4) {
1164 			u8 *rx = msg->rx_buf + j;
1165 
1166 			value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1167 
1168 			for (k = 0; k < 4 && (j + k) < msg->rx_len; k++)
1169 				rx[j + k] = (value >> (k << 3)) & 0xff;
1170 		}
1171 	}
1172 
1173 	return size;
1174 }
1175 
1176 static int tegra_dsi_transmit(struct tegra_dsi *dsi, unsigned long timeout)
1177 {
1178 	tegra_dsi_writel(dsi, DSI_TRIGGER_HOST, DSI_TRIGGER);
1179 
1180 	timeout = jiffies + msecs_to_jiffies(timeout);
1181 
1182 	while (time_before(jiffies, timeout)) {
1183 		u32 value = tegra_dsi_readl(dsi, DSI_TRIGGER);
1184 		if ((value & DSI_TRIGGER_HOST) == 0)
1185 			return 0;
1186 
1187 		usleep_range(1000, 2000);
1188 	}
1189 
1190 	DRM_DEBUG_KMS("timeout waiting for transmission to complete\n");
1191 	return -ETIMEDOUT;
1192 }
1193 
1194 static int tegra_dsi_wait_for_response(struct tegra_dsi *dsi,
1195 				       unsigned long timeout)
1196 {
1197 	timeout = jiffies + msecs_to_jiffies(250);
1198 
1199 	while (time_before(jiffies, timeout)) {
1200 		u32 value = tegra_dsi_readl(dsi, DSI_STATUS);
1201 		u8 count = value & 0x1f;
1202 
1203 		if (count > 0)
1204 			return count;
1205 
1206 		usleep_range(1000, 2000);
1207 	}
1208 
1209 	DRM_DEBUG_KMS("peripheral returned no data\n");
1210 	return -ETIMEDOUT;
1211 }
1212 
1213 static void tegra_dsi_writesl(struct tegra_dsi *dsi, unsigned long offset,
1214 			      const void *buffer, size_t size)
1215 {
1216 	const u8 *buf = buffer;
1217 	size_t i, j;
1218 	u32 value;
1219 
1220 	for (j = 0; j < size; j += 4) {
1221 		value = 0;
1222 
1223 		for (i = 0; i < 4 && j + i < size; i++)
1224 			value |= buf[j + i] << (i << 3);
1225 
1226 		tegra_dsi_writel(dsi, value, DSI_WR_DATA);
1227 	}
1228 }
1229 
1230 static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host,
1231 				       const struct mipi_dsi_msg *msg)
1232 {
1233 	struct tegra_dsi *dsi = host_to_tegra(host);
1234 	struct mipi_dsi_packet packet;
1235 	const u8 *header;
1236 	size_t count;
1237 	ssize_t err;
1238 	u32 value;
1239 
1240 	err = mipi_dsi_create_packet(&packet, msg);
1241 	if (err < 0)
1242 		return err;
1243 
1244 	header = packet.header;
1245 
1246 	/* maximum FIFO depth is 1920 words */
1247 	if (packet.size > dsi->video_fifo_depth * 4)
1248 		return -ENOSPC;
1249 
1250 	/* reset underflow/overflow flags */
1251 	value = tegra_dsi_readl(dsi, DSI_STATUS);
1252 	if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) {
1253 		value = DSI_HOST_CONTROL_FIFO_RESET;
1254 		tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1255 		usleep_range(10, 20);
1256 	}
1257 
1258 	value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
1259 	value |= DSI_POWER_CONTROL_ENABLE;
1260 	tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
1261 
1262 	usleep_range(5000, 10000);
1263 
1264 	value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST |
1265 		DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC;
1266 
1267 	if ((msg->flags & MIPI_DSI_MSG_USE_LPM) == 0)
1268 		value |= DSI_HOST_CONTROL_HS;
1269 
1270 	/*
1271 	 * The host FIFO has a maximum of 64 words, so larger transmissions
1272 	 * need to use the video FIFO.
1273 	 */
1274 	if (packet.size > dsi->host_fifo_depth * 4)
1275 		value |= DSI_HOST_CONTROL_FIFO_SEL;
1276 
1277 	tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1278 
1279 	/*
1280 	 * For reads and messages with explicitly requested ACK, generate a
1281 	 * BTA sequence after the transmission of the packet.
1282 	 */
1283 	if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
1284 	    (msg->rx_buf && msg->rx_len > 0)) {
1285 		value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL);
1286 		value |= DSI_HOST_CONTROL_PKT_BTA;
1287 		tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1288 	}
1289 
1290 	value = DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE;
1291 	tegra_dsi_writel(dsi, value, DSI_CONTROL);
1292 
1293 	/* write packet header, ECC is generated by hardware */
1294 	value = header[2] << 16 | header[1] << 8 | header[0];
1295 	tegra_dsi_writel(dsi, value, DSI_WR_DATA);
1296 
1297 	/* write payload (if any) */
1298 	if (packet.payload_length > 0)
1299 		tegra_dsi_writesl(dsi, DSI_WR_DATA, packet.payload,
1300 				  packet.payload_length);
1301 
1302 	err = tegra_dsi_transmit(dsi, 250);
1303 	if (err < 0)
1304 		return err;
1305 
1306 	if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
1307 	    (msg->rx_buf && msg->rx_len > 0)) {
1308 		err = tegra_dsi_wait_for_response(dsi, 250);
1309 		if (err < 0)
1310 			return err;
1311 
1312 		count = err;
1313 
1314 		value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1315 		switch (value) {
1316 		case 0x84:
1317 			/*
1318 			dev_dbg(dsi->dev, "ACK\n");
1319 			*/
1320 			break;
1321 
1322 		case 0x87:
1323 			/*
1324 			dev_dbg(dsi->dev, "ESCAPE\n");
1325 			*/
1326 			break;
1327 
1328 		default:
1329 			dev_err(dsi->dev, "unknown status: %08x\n", value);
1330 			break;
1331 		}
1332 
1333 		if (count > 1) {
1334 			err = tegra_dsi_read_response(dsi, msg, count);
1335 			if (err < 0)
1336 				dev_err(dsi->dev,
1337 					"failed to parse response: %zd\n",
1338 					err);
1339 			else {
1340 				/*
1341 				 * For read commands, return the number of
1342 				 * bytes returned by the peripheral.
1343 				 */
1344 				count = err;
1345 			}
1346 		}
1347 	} else {
1348 		/*
1349 		 * For write commands, we have transmitted the 4-byte header
1350 		 * plus the variable-length payload.
1351 		 */
1352 		count = 4 + packet.payload_length;
1353 	}
1354 
1355 	return count;
1356 }
1357 
1358 static int tegra_dsi_ganged_setup(struct tegra_dsi *dsi)
1359 {
1360 	struct clk *parent;
1361 	int err;
1362 
1363 	/* make sure both DSI controllers share the same PLL */
1364 	parent = clk_get_parent(dsi->slave->clk);
1365 	if (!parent)
1366 		return -EINVAL;
1367 
1368 	err = clk_set_parent(parent, dsi->clk_parent);
1369 	if (err < 0)
1370 		return err;
1371 
1372 	return 0;
1373 }
1374 
1375 static int tegra_dsi_host_attach(struct mipi_dsi_host *host,
1376 				 struct mipi_dsi_device *device)
1377 {
1378 	struct tegra_dsi *dsi = host_to_tegra(host);
1379 
1380 	dsi->flags = device->mode_flags;
1381 	dsi->format = device->format;
1382 	dsi->lanes = device->lanes;
1383 
1384 	if (dsi->slave) {
1385 		int err;
1386 
1387 		dev_dbg(dsi->dev, "attaching dual-channel device %s\n",
1388 			dev_name(&device->dev));
1389 
1390 		err = tegra_dsi_ganged_setup(dsi);
1391 		if (err < 0) {
1392 			dev_err(dsi->dev, "failed to set up ganged mode: %d\n",
1393 				err);
1394 			return err;
1395 		}
1396 	}
1397 
1398 	/*
1399 	 * Slaves don't have a panel associated with them, so they provide
1400 	 * merely the second channel.
1401 	 */
1402 	if (!dsi->master) {
1403 		struct tegra_output *output = &dsi->output;
1404 
1405 		output->panel = of_drm_find_panel(device->dev.of_node);
1406 		if (output->panel && output->connector.dev) {
1407 			drm_panel_attach(output->panel, &output->connector);
1408 			drm_helper_hpd_irq_event(output->connector.dev);
1409 		}
1410 	}
1411 
1412 	return 0;
1413 }
1414 
1415 static int tegra_dsi_host_detach(struct mipi_dsi_host *host,
1416 				 struct mipi_dsi_device *device)
1417 {
1418 	struct tegra_dsi *dsi = host_to_tegra(host);
1419 	struct tegra_output *output = &dsi->output;
1420 
1421 	if (output->panel && &device->dev == output->panel->dev) {
1422 		output->panel = NULL;
1423 
1424 		if (output->connector.dev)
1425 			drm_helper_hpd_irq_event(output->connector.dev);
1426 	}
1427 
1428 	return 0;
1429 }
1430 
1431 static const struct mipi_dsi_host_ops tegra_dsi_host_ops = {
1432 	.attach = tegra_dsi_host_attach,
1433 	.detach = tegra_dsi_host_detach,
1434 	.transfer = tegra_dsi_host_transfer,
1435 };
1436 
1437 static int tegra_dsi_ganged_probe(struct tegra_dsi *dsi)
1438 {
1439 	struct device_node *np;
1440 
1441 	np = of_parse_phandle(dsi->dev->of_node, "nvidia,ganged-mode", 0);
1442 	if (np) {
1443 		struct platform_device *gangster = of_find_device_by_node(np);
1444 
1445 		dsi->slave = platform_get_drvdata(gangster);
1446 		of_node_put(np);
1447 
1448 		if (!dsi->slave)
1449 			return -EPROBE_DEFER;
1450 
1451 		dsi->slave->master = dsi;
1452 	}
1453 
1454 	return 0;
1455 }
1456 
1457 static int tegra_dsi_probe(struct platform_device *pdev)
1458 {
1459 	struct tegra_dsi *dsi;
1460 	struct resource *regs;
1461 	int err;
1462 
1463 	dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
1464 	if (!dsi)
1465 		return -ENOMEM;
1466 
1467 	dsi->output.dev = dsi->dev = &pdev->dev;
1468 	dsi->video_fifo_depth = 1920;
1469 	dsi->host_fifo_depth = 64;
1470 
1471 	err = tegra_dsi_ganged_probe(dsi);
1472 	if (err < 0)
1473 		return err;
1474 
1475 	err = tegra_output_probe(&dsi->output);
1476 	if (err < 0)
1477 		return err;
1478 
1479 	dsi->output.connector.polled = DRM_CONNECTOR_POLL_HPD;
1480 
1481 	/*
1482 	 * Assume these values by default. When a DSI peripheral driver
1483 	 * attaches to the DSI host, the parameters will be taken from
1484 	 * the attached device.
1485 	 */
1486 	dsi->flags = MIPI_DSI_MODE_VIDEO;
1487 	dsi->format = MIPI_DSI_FMT_RGB888;
1488 	dsi->lanes = 4;
1489 
1490 	dsi->rst = devm_reset_control_get(&pdev->dev, "dsi");
1491 	if (IS_ERR(dsi->rst))
1492 		return PTR_ERR(dsi->rst);
1493 
1494 	dsi->clk = devm_clk_get(&pdev->dev, NULL);
1495 	if (IS_ERR(dsi->clk)) {
1496 		dev_err(&pdev->dev, "cannot get DSI clock\n");
1497 		err = PTR_ERR(dsi->clk);
1498 		goto reset;
1499 	}
1500 
1501 	err = clk_prepare_enable(dsi->clk);
1502 	if (err < 0) {
1503 		dev_err(&pdev->dev, "cannot enable DSI clock\n");
1504 		goto reset;
1505 	}
1506 
1507 	dsi->clk_lp = devm_clk_get(&pdev->dev, "lp");
1508 	if (IS_ERR(dsi->clk_lp)) {
1509 		dev_err(&pdev->dev, "cannot get low-power clock\n");
1510 		err = PTR_ERR(dsi->clk_lp);
1511 		goto disable_clk;
1512 	}
1513 
1514 	err = clk_prepare_enable(dsi->clk_lp);
1515 	if (err < 0) {
1516 		dev_err(&pdev->dev, "cannot enable low-power clock\n");
1517 		goto disable_clk;
1518 	}
1519 
1520 	dsi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1521 	if (IS_ERR(dsi->clk_parent)) {
1522 		dev_err(&pdev->dev, "cannot get parent clock\n");
1523 		err = PTR_ERR(dsi->clk_parent);
1524 		goto disable_clk_lp;
1525 	}
1526 
1527 	dsi->vdd = devm_regulator_get(&pdev->dev, "avdd-dsi-csi");
1528 	if (IS_ERR(dsi->vdd)) {
1529 		dev_err(&pdev->dev, "cannot get VDD supply\n");
1530 		err = PTR_ERR(dsi->vdd);
1531 		goto disable_clk_lp;
1532 	}
1533 
1534 	err = regulator_enable(dsi->vdd);
1535 	if (err < 0) {
1536 		dev_err(&pdev->dev, "cannot enable VDD supply\n");
1537 		goto disable_clk_lp;
1538 	}
1539 
1540 	err = tegra_dsi_setup_clocks(dsi);
1541 	if (err < 0) {
1542 		dev_err(&pdev->dev, "cannot setup clocks\n");
1543 		goto disable_vdd;
1544 	}
1545 
1546 	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1547 	dsi->regs = devm_ioremap_resource(&pdev->dev, regs);
1548 	if (IS_ERR(dsi->regs)) {
1549 		err = PTR_ERR(dsi->regs);
1550 		goto disable_vdd;
1551 	}
1552 
1553 	dsi->mipi = tegra_mipi_request(&pdev->dev);
1554 	if (IS_ERR(dsi->mipi)) {
1555 		err = PTR_ERR(dsi->mipi);
1556 		goto disable_vdd;
1557 	}
1558 
1559 	dsi->host.ops = &tegra_dsi_host_ops;
1560 	dsi->host.dev = &pdev->dev;
1561 
1562 	err = mipi_dsi_host_register(&dsi->host);
1563 	if (err < 0) {
1564 		dev_err(&pdev->dev, "failed to register DSI host: %d\n", err);
1565 		goto mipi_free;
1566 	}
1567 
1568 	INIT_LIST_HEAD(&dsi->client.list);
1569 	dsi->client.ops = &dsi_client_ops;
1570 	dsi->client.dev = &pdev->dev;
1571 
1572 	err = host1x_client_register(&dsi->client);
1573 	if (err < 0) {
1574 		dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1575 			err);
1576 		goto unregister;
1577 	}
1578 
1579 	platform_set_drvdata(pdev, dsi);
1580 
1581 	return 0;
1582 
1583 unregister:
1584 	mipi_dsi_host_unregister(&dsi->host);
1585 mipi_free:
1586 	tegra_mipi_free(dsi->mipi);
1587 disable_vdd:
1588 	regulator_disable(dsi->vdd);
1589 disable_clk_lp:
1590 	clk_disable_unprepare(dsi->clk_lp);
1591 disable_clk:
1592 	clk_disable_unprepare(dsi->clk);
1593 reset:
1594 	reset_control_assert(dsi->rst);
1595 	return err;
1596 }
1597 
1598 static int tegra_dsi_remove(struct platform_device *pdev)
1599 {
1600 	struct tegra_dsi *dsi = platform_get_drvdata(pdev);
1601 	int err;
1602 
1603 	err = host1x_client_unregister(&dsi->client);
1604 	if (err < 0) {
1605 		dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1606 			err);
1607 		return err;
1608 	}
1609 
1610 	tegra_output_remove(&dsi->output);
1611 
1612 	mipi_dsi_host_unregister(&dsi->host);
1613 	tegra_mipi_free(dsi->mipi);
1614 
1615 	regulator_disable(dsi->vdd);
1616 	clk_disable_unprepare(dsi->clk_lp);
1617 	clk_disable_unprepare(dsi->clk);
1618 	reset_control_assert(dsi->rst);
1619 
1620 	return 0;
1621 }
1622 
1623 static const struct of_device_id tegra_dsi_of_match[] = {
1624 	{ .compatible = "nvidia,tegra210-dsi", },
1625 	{ .compatible = "nvidia,tegra132-dsi", },
1626 	{ .compatible = "nvidia,tegra124-dsi", },
1627 	{ .compatible = "nvidia,tegra114-dsi", },
1628 	{ },
1629 };
1630 MODULE_DEVICE_TABLE(of, tegra_dsi_of_match);
1631 
1632 struct platform_driver tegra_dsi_driver = {
1633 	.driver = {
1634 		.name = "tegra-dsi",
1635 		.of_match_table = tegra_dsi_of_match,
1636 	},
1637 	.probe = tegra_dsi_probe,
1638 	.remove = tegra_dsi_remove,
1639 };
1640