1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 NVIDIA Corporation 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/debugfs.h> 8 #include <linux/delay.h> 9 #include <linux/host1x.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_platform.h> 13 #include <linux/platform_device.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/reset.h> 17 18 #include <video/mipi_display.h> 19 20 #include <drm/drm_atomic_helper.h> 21 #include <drm/drm_debugfs.h> 22 #include <drm/drm_file.h> 23 #include <drm/drm_mipi_dsi.h> 24 #include <drm/drm_panel.h> 25 #include <drm/drm_simple_kms_helper.h> 26 #include <drm/drm_drv.h> 27 28 #include "dc.h" 29 #include "drm.h" 30 #include "dsi.h" 31 #include "mipi-phy.h" 32 #include "trace.h" 33 34 struct tegra_dsi_state { 35 struct drm_connector_state base; 36 37 struct mipi_dphy_timing timing; 38 unsigned long period; 39 40 unsigned int vrefresh; 41 unsigned int lanes; 42 unsigned long pclk; 43 unsigned long bclk; 44 45 enum tegra_dsi_format format; 46 unsigned int mul; 47 unsigned int div; 48 }; 49 50 static inline struct tegra_dsi_state * 51 to_dsi_state(struct drm_connector_state *state) 52 { 53 return container_of(state, struct tegra_dsi_state, base); 54 } 55 56 struct tegra_dsi { 57 struct host1x_client client; 58 struct tegra_output output; 59 struct device *dev; 60 61 void __iomem *regs; 62 63 struct reset_control *rst; 64 struct clk *clk_parent; 65 struct clk *clk_lp; 66 struct clk *clk; 67 68 struct drm_info_list *debugfs_files; 69 70 unsigned long flags; 71 enum mipi_dsi_pixel_format format; 72 unsigned int lanes; 73 74 struct tegra_mipi_device *mipi; 75 struct mipi_dsi_host host; 76 77 struct regulator *vdd; 78 79 unsigned int video_fifo_depth; 80 unsigned int host_fifo_depth; 81 82 /* for ganged-mode support */ 83 struct tegra_dsi *master; 84 struct tegra_dsi *slave; 85 }; 86 87 static inline struct tegra_dsi * 88 host1x_client_to_dsi(struct host1x_client *client) 89 { 90 return container_of(client, struct tegra_dsi, client); 91 } 92 93 static inline struct tegra_dsi *host_to_tegra(struct mipi_dsi_host *host) 94 { 95 return container_of(host, struct tegra_dsi, host); 96 } 97 98 static inline struct tegra_dsi *to_dsi(struct tegra_output *output) 99 { 100 return container_of(output, struct tegra_dsi, output); 101 } 102 103 static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi) 104 { 105 return to_dsi_state(dsi->output.connector.state); 106 } 107 108 static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned int offset) 109 { 110 u32 value = readl(dsi->regs + (offset << 2)); 111 112 trace_dsi_readl(dsi->dev, offset, value); 113 114 return value; 115 } 116 117 static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value, 118 unsigned int offset) 119 { 120 trace_dsi_writel(dsi->dev, offset, value); 121 writel(value, dsi->regs + (offset << 2)); 122 } 123 124 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name } 125 126 static const struct debugfs_reg32 tegra_dsi_regs[] = { 127 DEBUGFS_REG32(DSI_INCR_SYNCPT), 128 DEBUGFS_REG32(DSI_INCR_SYNCPT_CONTROL), 129 DEBUGFS_REG32(DSI_INCR_SYNCPT_ERROR), 130 DEBUGFS_REG32(DSI_CTXSW), 131 DEBUGFS_REG32(DSI_RD_DATA), 132 DEBUGFS_REG32(DSI_WR_DATA), 133 DEBUGFS_REG32(DSI_POWER_CONTROL), 134 DEBUGFS_REG32(DSI_INT_ENABLE), 135 DEBUGFS_REG32(DSI_INT_STATUS), 136 DEBUGFS_REG32(DSI_INT_MASK), 137 DEBUGFS_REG32(DSI_HOST_CONTROL), 138 DEBUGFS_REG32(DSI_CONTROL), 139 DEBUGFS_REG32(DSI_SOL_DELAY), 140 DEBUGFS_REG32(DSI_MAX_THRESHOLD), 141 DEBUGFS_REG32(DSI_TRIGGER), 142 DEBUGFS_REG32(DSI_TX_CRC), 143 DEBUGFS_REG32(DSI_STATUS), 144 DEBUGFS_REG32(DSI_INIT_SEQ_CONTROL), 145 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_0), 146 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_1), 147 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_2), 148 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_3), 149 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_4), 150 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_5), 151 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_6), 152 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_7), 153 DEBUGFS_REG32(DSI_PKT_SEQ_0_LO), 154 DEBUGFS_REG32(DSI_PKT_SEQ_0_HI), 155 DEBUGFS_REG32(DSI_PKT_SEQ_1_LO), 156 DEBUGFS_REG32(DSI_PKT_SEQ_1_HI), 157 DEBUGFS_REG32(DSI_PKT_SEQ_2_LO), 158 DEBUGFS_REG32(DSI_PKT_SEQ_2_HI), 159 DEBUGFS_REG32(DSI_PKT_SEQ_3_LO), 160 DEBUGFS_REG32(DSI_PKT_SEQ_3_HI), 161 DEBUGFS_REG32(DSI_PKT_SEQ_4_LO), 162 DEBUGFS_REG32(DSI_PKT_SEQ_4_HI), 163 DEBUGFS_REG32(DSI_PKT_SEQ_5_LO), 164 DEBUGFS_REG32(DSI_PKT_SEQ_5_HI), 165 DEBUGFS_REG32(DSI_DCS_CMDS), 166 DEBUGFS_REG32(DSI_PKT_LEN_0_1), 167 DEBUGFS_REG32(DSI_PKT_LEN_2_3), 168 DEBUGFS_REG32(DSI_PKT_LEN_4_5), 169 DEBUGFS_REG32(DSI_PKT_LEN_6_7), 170 DEBUGFS_REG32(DSI_PHY_TIMING_0), 171 DEBUGFS_REG32(DSI_PHY_TIMING_1), 172 DEBUGFS_REG32(DSI_PHY_TIMING_2), 173 DEBUGFS_REG32(DSI_BTA_TIMING), 174 DEBUGFS_REG32(DSI_TIMEOUT_0), 175 DEBUGFS_REG32(DSI_TIMEOUT_1), 176 DEBUGFS_REG32(DSI_TO_TALLY), 177 DEBUGFS_REG32(DSI_PAD_CONTROL_0), 178 DEBUGFS_REG32(DSI_PAD_CONTROL_CD), 179 DEBUGFS_REG32(DSI_PAD_CD_STATUS), 180 DEBUGFS_REG32(DSI_VIDEO_MODE_CONTROL), 181 DEBUGFS_REG32(DSI_PAD_CONTROL_1), 182 DEBUGFS_REG32(DSI_PAD_CONTROL_2), 183 DEBUGFS_REG32(DSI_PAD_CONTROL_3), 184 DEBUGFS_REG32(DSI_PAD_CONTROL_4), 185 DEBUGFS_REG32(DSI_GANGED_MODE_CONTROL), 186 DEBUGFS_REG32(DSI_GANGED_MODE_START), 187 DEBUGFS_REG32(DSI_GANGED_MODE_SIZE), 188 DEBUGFS_REG32(DSI_RAW_DATA_BYTE_COUNT), 189 DEBUGFS_REG32(DSI_ULTRA_LOW_POWER_CONTROL), 190 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_8), 191 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_9), 192 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_10), 193 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_11), 194 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_12), 195 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_13), 196 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_14), 197 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_15), 198 }; 199 200 static int tegra_dsi_show_regs(struct seq_file *s, void *data) 201 { 202 struct drm_info_node *node = s->private; 203 struct tegra_dsi *dsi = node->info_ent->data; 204 struct drm_crtc *crtc = dsi->output.encoder.crtc; 205 struct drm_device *drm = node->minor->dev; 206 struct drm_modeset_acquire_ctx ctx; 207 unsigned int i; 208 int err = 0; 209 210 DRM_MODESET_LOCK_ALL_BEGIN(drm, ctx, 0, err); 211 212 if (!crtc || !crtc->state->active) { 213 err = -EBUSY; 214 goto unlock; 215 } 216 217 for (i = 0; i < ARRAY_SIZE(tegra_dsi_regs); i++) { 218 unsigned int offset = tegra_dsi_regs[i].offset; 219 220 seq_printf(s, "%-32s %#05x %08x\n", tegra_dsi_regs[i].name, 221 offset, tegra_dsi_readl(dsi, offset)); 222 } 223 224 unlock: 225 DRM_MODESET_LOCK_ALL_END(drm, ctx, err); 226 return err; 227 } 228 229 static struct drm_info_list debugfs_files[] = { 230 { "regs", tegra_dsi_show_regs, 0, NULL }, 231 }; 232 233 static int tegra_dsi_late_register(struct drm_connector *connector) 234 { 235 struct tegra_output *output = connector_to_output(connector); 236 unsigned int i, count = ARRAY_SIZE(debugfs_files); 237 struct drm_minor *minor = connector->dev->primary; 238 struct dentry *root = connector->debugfs_entry; 239 struct tegra_dsi *dsi = to_dsi(output); 240 241 dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), 242 GFP_KERNEL); 243 if (!dsi->debugfs_files) 244 return -ENOMEM; 245 246 for (i = 0; i < count; i++) 247 dsi->debugfs_files[i].data = dsi; 248 249 drm_debugfs_create_files(dsi->debugfs_files, count, root, minor); 250 251 return 0; 252 } 253 254 static void tegra_dsi_early_unregister(struct drm_connector *connector) 255 { 256 struct tegra_output *output = connector_to_output(connector); 257 unsigned int count = ARRAY_SIZE(debugfs_files); 258 struct tegra_dsi *dsi = to_dsi(output); 259 260 drm_debugfs_remove_files(dsi->debugfs_files, count, 261 connector->dev->primary); 262 kfree(dsi->debugfs_files); 263 dsi->debugfs_files = NULL; 264 } 265 266 #define PKT_ID0(id) ((((id) & 0x3f) << 3) | (1 << 9)) 267 #define PKT_LEN0(len) (((len) & 0x07) << 0) 268 #define PKT_ID1(id) ((((id) & 0x3f) << 13) | (1 << 19)) 269 #define PKT_LEN1(len) (((len) & 0x07) << 10) 270 #define PKT_ID2(id) ((((id) & 0x3f) << 23) | (1 << 29)) 271 #define PKT_LEN2(len) (((len) & 0x07) << 20) 272 273 #define PKT_LP (1 << 30) 274 #define NUM_PKT_SEQ 12 275 276 /* 277 * non-burst mode with sync pulses 278 */ 279 static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = { 280 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) | 281 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 282 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | 283 PKT_LP, 284 [ 1] = 0, 285 [ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) | 286 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 287 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | 288 PKT_LP, 289 [ 3] = 0, 290 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 291 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 292 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | 293 PKT_LP, 294 [ 5] = 0, 295 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 296 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 297 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0), 298 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) | 299 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) | 300 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4), 301 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 302 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 303 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | 304 PKT_LP, 305 [ 9] = 0, 306 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 307 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 308 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0), 309 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) | 310 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) | 311 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4), 312 }; 313 314 /* 315 * non-burst mode with sync events 316 */ 317 static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = { 318 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) | 319 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | 320 PKT_LP, 321 [ 1] = 0, 322 [ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 323 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | 324 PKT_LP, 325 [ 3] = 0, 326 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 327 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | 328 PKT_LP, 329 [ 5] = 0, 330 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 331 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) | 332 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3), 333 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4), 334 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 335 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | 336 PKT_LP, 337 [ 9] = 0, 338 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 339 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) | 340 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3), 341 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4), 342 }; 343 344 static const u32 pkt_seq_command_mode[NUM_PKT_SEQ] = { 345 [ 0] = 0, 346 [ 1] = 0, 347 [ 2] = 0, 348 [ 3] = 0, 349 [ 4] = 0, 350 [ 5] = 0, 351 [ 6] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(3) | PKT_LP, 352 [ 7] = 0, 353 [ 8] = 0, 354 [ 9] = 0, 355 [10] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(5) | PKT_LP, 356 [11] = 0, 357 }; 358 359 static void tegra_dsi_set_phy_timing(struct tegra_dsi *dsi, 360 unsigned long period, 361 const struct mipi_dphy_timing *timing) 362 { 363 u32 value; 364 365 value = DSI_TIMING_FIELD(timing->hsexit, period, 1) << 24 | 366 DSI_TIMING_FIELD(timing->hstrail, period, 0) << 16 | 367 DSI_TIMING_FIELD(timing->hszero, period, 3) << 8 | 368 DSI_TIMING_FIELD(timing->hsprepare, period, 1); 369 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0); 370 371 value = DSI_TIMING_FIELD(timing->clktrail, period, 1) << 24 | 372 DSI_TIMING_FIELD(timing->clkpost, period, 1) << 16 | 373 DSI_TIMING_FIELD(timing->clkzero, period, 1) << 8 | 374 DSI_TIMING_FIELD(timing->lpx, period, 1); 375 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1); 376 377 value = DSI_TIMING_FIELD(timing->clkprepare, period, 1) << 16 | 378 DSI_TIMING_FIELD(timing->clkpre, period, 1) << 8 | 379 DSI_TIMING_FIELD(0xff * period, period, 0) << 0; 380 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2); 381 382 value = DSI_TIMING_FIELD(timing->taget, period, 1) << 16 | 383 DSI_TIMING_FIELD(timing->tasure, period, 1) << 8 | 384 DSI_TIMING_FIELD(timing->tago, period, 1); 385 tegra_dsi_writel(dsi, value, DSI_BTA_TIMING); 386 387 if (dsi->slave) 388 tegra_dsi_set_phy_timing(dsi->slave, period, timing); 389 } 390 391 static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format, 392 unsigned int *mulp, unsigned int *divp) 393 { 394 switch (format) { 395 case MIPI_DSI_FMT_RGB666_PACKED: 396 case MIPI_DSI_FMT_RGB888: 397 *mulp = 3; 398 *divp = 1; 399 break; 400 401 case MIPI_DSI_FMT_RGB565: 402 *mulp = 2; 403 *divp = 1; 404 break; 405 406 case MIPI_DSI_FMT_RGB666: 407 *mulp = 9; 408 *divp = 4; 409 break; 410 411 default: 412 return -EINVAL; 413 } 414 415 return 0; 416 } 417 418 static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format, 419 enum tegra_dsi_format *fmt) 420 { 421 switch (format) { 422 case MIPI_DSI_FMT_RGB888: 423 *fmt = TEGRA_DSI_FORMAT_24P; 424 break; 425 426 case MIPI_DSI_FMT_RGB666: 427 *fmt = TEGRA_DSI_FORMAT_18NP; 428 break; 429 430 case MIPI_DSI_FMT_RGB666_PACKED: 431 *fmt = TEGRA_DSI_FORMAT_18P; 432 break; 433 434 case MIPI_DSI_FMT_RGB565: 435 *fmt = TEGRA_DSI_FORMAT_16P; 436 break; 437 438 default: 439 return -EINVAL; 440 } 441 442 return 0; 443 } 444 445 static void tegra_dsi_ganged_enable(struct tegra_dsi *dsi, unsigned int start, 446 unsigned int size) 447 { 448 u32 value; 449 450 tegra_dsi_writel(dsi, start, DSI_GANGED_MODE_START); 451 tegra_dsi_writel(dsi, size << 16 | size, DSI_GANGED_MODE_SIZE); 452 453 value = DSI_GANGED_MODE_CONTROL_ENABLE; 454 tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL); 455 } 456 457 static void tegra_dsi_enable(struct tegra_dsi *dsi) 458 { 459 u32 value; 460 461 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 462 value |= DSI_POWER_CONTROL_ENABLE; 463 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); 464 465 if (dsi->slave) 466 tegra_dsi_enable(dsi->slave); 467 } 468 469 static unsigned int tegra_dsi_get_lanes(struct tegra_dsi *dsi) 470 { 471 if (dsi->master) 472 return dsi->master->lanes + dsi->lanes; 473 474 if (dsi->slave) 475 return dsi->lanes + dsi->slave->lanes; 476 477 return dsi->lanes; 478 } 479 480 static void tegra_dsi_configure(struct tegra_dsi *dsi, unsigned int pipe, 481 const struct drm_display_mode *mode) 482 { 483 unsigned int hact, hsw, hbp, hfp, i, mul, div; 484 struct tegra_dsi_state *state; 485 const u32 *pkt_seq; 486 u32 value; 487 488 /* XXX: pass in state into this function? */ 489 if (dsi->master) 490 state = tegra_dsi_get_state(dsi->master); 491 else 492 state = tegra_dsi_get_state(dsi); 493 494 mul = state->mul; 495 div = state->div; 496 497 if (dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { 498 DRM_DEBUG_KMS("Non-burst video mode with sync pulses\n"); 499 pkt_seq = pkt_seq_video_non_burst_sync_pulses; 500 } else if (dsi->flags & MIPI_DSI_MODE_VIDEO) { 501 DRM_DEBUG_KMS("Non-burst video mode with sync events\n"); 502 pkt_seq = pkt_seq_video_non_burst_sync_events; 503 } else { 504 DRM_DEBUG_KMS("Command mode\n"); 505 pkt_seq = pkt_seq_command_mode; 506 } 507 508 value = DSI_CONTROL_CHANNEL(0) | 509 DSI_CONTROL_FORMAT(state->format) | 510 DSI_CONTROL_LANES(dsi->lanes - 1) | 511 DSI_CONTROL_SOURCE(pipe); 512 tegra_dsi_writel(dsi, value, DSI_CONTROL); 513 514 tegra_dsi_writel(dsi, dsi->video_fifo_depth, DSI_MAX_THRESHOLD); 515 516 value = DSI_HOST_CONTROL_HS; 517 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); 518 519 value = tegra_dsi_readl(dsi, DSI_CONTROL); 520 521 if (dsi->flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) 522 value |= DSI_CONTROL_HS_CLK_CTRL; 523 524 value &= ~DSI_CONTROL_TX_TRIG(3); 525 526 /* enable DCS commands for command mode */ 527 if (dsi->flags & MIPI_DSI_MODE_VIDEO) 528 value &= ~DSI_CONTROL_DCS_ENABLE; 529 else 530 value |= DSI_CONTROL_DCS_ENABLE; 531 532 value |= DSI_CONTROL_VIDEO_ENABLE; 533 value &= ~DSI_CONTROL_HOST_ENABLE; 534 tegra_dsi_writel(dsi, value, DSI_CONTROL); 535 536 for (i = 0; i < NUM_PKT_SEQ; i++) 537 tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i); 538 539 if (dsi->flags & MIPI_DSI_MODE_VIDEO) { 540 /* horizontal active pixels */ 541 hact = mode->hdisplay * mul / div; 542 543 /* horizontal sync width */ 544 hsw = (mode->hsync_end - mode->hsync_start) * mul / div; 545 546 /* horizontal back porch */ 547 hbp = (mode->htotal - mode->hsync_end) * mul / div; 548 549 if ((dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) == 0) 550 hbp += hsw; 551 552 /* horizontal front porch */ 553 hfp = (mode->hsync_start - mode->hdisplay) * mul / div; 554 555 /* subtract packet overhead */ 556 hsw -= 10; 557 hbp -= 14; 558 hfp -= 8; 559 560 tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1); 561 tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3); 562 tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5); 563 tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7); 564 565 /* set SOL delay (for non-burst mode only) */ 566 tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY); 567 568 /* TODO: implement ganged mode */ 569 } else { 570 u16 bytes; 571 572 if (dsi->master || dsi->slave) { 573 /* 574 * For ganged mode, assume symmetric left-right mode. 575 */ 576 bytes = 1 + (mode->hdisplay / 2) * mul / div; 577 } else { 578 /* 1 byte (DCS command) + pixel data */ 579 bytes = 1 + mode->hdisplay * mul / div; 580 } 581 582 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1); 583 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_2_3); 584 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_4_5); 585 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_6_7); 586 587 value = MIPI_DCS_WRITE_MEMORY_START << 8 | 588 MIPI_DCS_WRITE_MEMORY_CONTINUE; 589 tegra_dsi_writel(dsi, value, DSI_DCS_CMDS); 590 591 /* set SOL delay */ 592 if (dsi->master || dsi->slave) { 593 unsigned long delay, bclk, bclk_ganged; 594 unsigned int lanes = state->lanes; 595 596 /* SOL to valid, valid to FIFO and FIFO write delay */ 597 delay = 4 + 4 + 2; 598 delay = DIV_ROUND_UP(delay * mul, div * lanes); 599 /* FIFO read delay */ 600 delay = delay + 6; 601 602 bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes); 603 bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes); 604 value = bclk - bclk_ganged + delay + 20; 605 } else { 606 /* TODO: revisit for non-ganged mode */ 607 value = 8 * mul / div; 608 } 609 610 tegra_dsi_writel(dsi, value, DSI_SOL_DELAY); 611 } 612 613 if (dsi->slave) { 614 tegra_dsi_configure(dsi->slave, pipe, mode); 615 616 /* 617 * TODO: Support modes other than symmetrical left-right 618 * split. 619 */ 620 tegra_dsi_ganged_enable(dsi, 0, mode->hdisplay / 2); 621 tegra_dsi_ganged_enable(dsi->slave, mode->hdisplay / 2, 622 mode->hdisplay / 2); 623 } 624 } 625 626 static int tegra_dsi_wait_idle(struct tegra_dsi *dsi, unsigned long timeout) 627 { 628 u32 value; 629 630 timeout = jiffies + msecs_to_jiffies(timeout); 631 632 while (time_before(jiffies, timeout)) { 633 value = tegra_dsi_readl(dsi, DSI_STATUS); 634 if (value & DSI_STATUS_IDLE) 635 return 0; 636 637 usleep_range(1000, 2000); 638 } 639 640 return -ETIMEDOUT; 641 } 642 643 static void tegra_dsi_video_disable(struct tegra_dsi *dsi) 644 { 645 u32 value; 646 647 value = tegra_dsi_readl(dsi, DSI_CONTROL); 648 value &= ~DSI_CONTROL_VIDEO_ENABLE; 649 tegra_dsi_writel(dsi, value, DSI_CONTROL); 650 651 if (dsi->slave) 652 tegra_dsi_video_disable(dsi->slave); 653 } 654 655 static void tegra_dsi_ganged_disable(struct tegra_dsi *dsi) 656 { 657 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_START); 658 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_SIZE); 659 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_CONTROL); 660 } 661 662 static int tegra_dsi_pad_enable(struct tegra_dsi *dsi) 663 { 664 u32 value; 665 666 value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0); 667 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0); 668 669 return 0; 670 } 671 672 static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi) 673 { 674 u32 value; 675 int err; 676 677 /* 678 * XXX Is this still needed? The module reset is deasserted right 679 * before this function is called. 680 */ 681 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0); 682 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1); 683 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2); 684 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3); 685 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4); 686 687 /* start calibration */ 688 tegra_dsi_pad_enable(dsi); 689 690 value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) | 691 DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) | 692 DSI_PAD_OUT_CLK(0x0); 693 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2); 694 695 value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | 696 DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3); 697 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3); 698 699 err = tegra_mipi_start_calibration(dsi->mipi); 700 if (err < 0) 701 return err; 702 703 return tegra_mipi_finish_calibration(dsi->mipi); 704 } 705 706 static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk, 707 unsigned int vrefresh) 708 { 709 unsigned int timeout; 710 u32 value; 711 712 /* one frame high-speed transmission timeout */ 713 timeout = (bclk / vrefresh) / 512; 714 value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout); 715 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0); 716 717 /* 2 ms peripheral timeout for panel */ 718 timeout = 2 * bclk / 512 * 1000; 719 value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000); 720 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1); 721 722 value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0); 723 tegra_dsi_writel(dsi, value, DSI_TO_TALLY); 724 725 if (dsi->slave) 726 tegra_dsi_set_timeout(dsi->slave, bclk, vrefresh); 727 } 728 729 static void tegra_dsi_disable(struct tegra_dsi *dsi) 730 { 731 u32 value; 732 733 if (dsi->slave) { 734 tegra_dsi_ganged_disable(dsi->slave); 735 tegra_dsi_ganged_disable(dsi); 736 } 737 738 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 739 value &= ~DSI_POWER_CONTROL_ENABLE; 740 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); 741 742 if (dsi->slave) 743 tegra_dsi_disable(dsi->slave); 744 745 usleep_range(5000, 10000); 746 } 747 748 static void tegra_dsi_soft_reset(struct tegra_dsi *dsi) 749 { 750 u32 value; 751 752 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 753 value &= ~DSI_POWER_CONTROL_ENABLE; 754 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); 755 756 usleep_range(300, 1000); 757 758 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 759 value |= DSI_POWER_CONTROL_ENABLE; 760 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); 761 762 usleep_range(300, 1000); 763 764 value = tegra_dsi_readl(dsi, DSI_TRIGGER); 765 if (value) 766 tegra_dsi_writel(dsi, 0, DSI_TRIGGER); 767 768 if (dsi->slave) 769 tegra_dsi_soft_reset(dsi->slave); 770 } 771 772 static void tegra_dsi_connector_reset(struct drm_connector *connector) 773 { 774 struct tegra_dsi_state *state = kzalloc(sizeof(*state), GFP_KERNEL); 775 776 if (!state) 777 return; 778 779 if (connector->state) { 780 __drm_atomic_helper_connector_destroy_state(connector->state); 781 kfree(connector->state); 782 } 783 784 __drm_atomic_helper_connector_reset(connector, &state->base); 785 } 786 787 static struct drm_connector_state * 788 tegra_dsi_connector_duplicate_state(struct drm_connector *connector) 789 { 790 struct tegra_dsi_state *state = to_dsi_state(connector->state); 791 struct tegra_dsi_state *copy; 792 793 copy = kmemdup(state, sizeof(*state), GFP_KERNEL); 794 if (!copy) 795 return NULL; 796 797 __drm_atomic_helper_connector_duplicate_state(connector, 798 ©->base); 799 800 return ©->base; 801 } 802 803 static const struct drm_connector_funcs tegra_dsi_connector_funcs = { 804 .reset = tegra_dsi_connector_reset, 805 .detect = tegra_output_connector_detect, 806 .fill_modes = drm_helper_probe_single_connector_modes, 807 .destroy = tegra_output_connector_destroy, 808 .atomic_duplicate_state = tegra_dsi_connector_duplicate_state, 809 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 810 .late_register = tegra_dsi_late_register, 811 .early_unregister = tegra_dsi_early_unregister, 812 }; 813 814 static enum drm_mode_status 815 tegra_dsi_connector_mode_valid(struct drm_connector *connector, 816 struct drm_display_mode *mode) 817 { 818 return MODE_OK; 819 } 820 821 static const struct drm_connector_helper_funcs tegra_dsi_connector_helper_funcs = { 822 .get_modes = tegra_output_connector_get_modes, 823 .mode_valid = tegra_dsi_connector_mode_valid, 824 }; 825 826 static void tegra_dsi_unprepare(struct tegra_dsi *dsi) 827 { 828 int err; 829 830 if (dsi->slave) 831 tegra_dsi_unprepare(dsi->slave); 832 833 err = tegra_mipi_disable(dsi->mipi); 834 if (err < 0) 835 dev_err(dsi->dev, "failed to disable MIPI calibration: %d\n", 836 err); 837 838 err = host1x_client_suspend(&dsi->client); 839 if (err < 0) 840 dev_err(dsi->dev, "failed to suspend: %d\n", err); 841 } 842 843 static void tegra_dsi_encoder_disable(struct drm_encoder *encoder) 844 { 845 struct tegra_output *output = encoder_to_output(encoder); 846 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 847 struct tegra_dsi *dsi = to_dsi(output); 848 u32 value; 849 int err; 850 851 if (output->panel) 852 drm_panel_disable(output->panel); 853 854 tegra_dsi_video_disable(dsi); 855 856 /* 857 * The following accesses registers of the display controller, so make 858 * sure it's only executed when the output is attached to one. 859 */ 860 if (dc) { 861 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 862 value &= ~DSI_ENABLE; 863 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 864 865 tegra_dc_commit(dc); 866 } 867 868 err = tegra_dsi_wait_idle(dsi, 100); 869 if (err < 0) 870 dev_dbg(dsi->dev, "failed to idle DSI: %d\n", err); 871 872 tegra_dsi_soft_reset(dsi); 873 874 if (output->panel) 875 drm_panel_unprepare(output->panel); 876 877 tegra_dsi_disable(dsi); 878 879 tegra_dsi_unprepare(dsi); 880 } 881 882 static int tegra_dsi_prepare(struct tegra_dsi *dsi) 883 { 884 int err; 885 886 err = host1x_client_resume(&dsi->client); 887 if (err < 0) { 888 dev_err(dsi->dev, "failed to resume: %d\n", err); 889 return err; 890 } 891 892 err = tegra_mipi_enable(dsi->mipi); 893 if (err < 0) 894 dev_err(dsi->dev, "failed to enable MIPI calibration: %d\n", 895 err); 896 897 err = tegra_dsi_pad_calibrate(dsi); 898 if (err < 0) 899 dev_err(dsi->dev, "MIPI calibration failed: %d\n", err); 900 901 if (dsi->slave) 902 tegra_dsi_prepare(dsi->slave); 903 904 return 0; 905 } 906 907 static void tegra_dsi_encoder_enable(struct drm_encoder *encoder) 908 { 909 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 910 struct tegra_output *output = encoder_to_output(encoder); 911 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 912 struct tegra_dsi *dsi = to_dsi(output); 913 struct tegra_dsi_state *state; 914 u32 value; 915 int err; 916 917 err = tegra_dsi_prepare(dsi); 918 if (err < 0) { 919 dev_err(dsi->dev, "failed to prepare: %d\n", err); 920 return; 921 } 922 923 state = tegra_dsi_get_state(dsi); 924 925 tegra_dsi_set_timeout(dsi, state->bclk, state->vrefresh); 926 927 /* 928 * The D-PHY timing fields are expressed in byte-clock cycles, so 929 * multiply the period by 8. 930 */ 931 tegra_dsi_set_phy_timing(dsi, state->period * 8, &state->timing); 932 933 if (output->panel) 934 drm_panel_prepare(output->panel); 935 936 tegra_dsi_configure(dsi, dc->pipe, mode); 937 938 /* enable display controller */ 939 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 940 value |= DSI_ENABLE; 941 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 942 943 tegra_dc_commit(dc); 944 945 /* enable DSI controller */ 946 tegra_dsi_enable(dsi); 947 948 if (output->panel) 949 drm_panel_enable(output->panel); 950 } 951 952 static int 953 tegra_dsi_encoder_atomic_check(struct drm_encoder *encoder, 954 struct drm_crtc_state *crtc_state, 955 struct drm_connector_state *conn_state) 956 { 957 struct tegra_output *output = encoder_to_output(encoder); 958 struct tegra_dsi_state *state = to_dsi_state(conn_state); 959 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc); 960 struct tegra_dsi *dsi = to_dsi(output); 961 unsigned int scdiv; 962 unsigned long plld; 963 int err; 964 965 state->pclk = crtc_state->mode.clock * 1000; 966 967 err = tegra_dsi_get_muldiv(dsi->format, &state->mul, &state->div); 968 if (err < 0) 969 return err; 970 971 state->lanes = tegra_dsi_get_lanes(dsi); 972 973 err = tegra_dsi_get_format(dsi->format, &state->format); 974 if (err < 0) 975 return err; 976 977 state->vrefresh = drm_mode_vrefresh(&crtc_state->mode); 978 979 /* compute byte clock */ 980 state->bclk = (state->pclk * state->mul) / (state->div * state->lanes); 981 982 DRM_DEBUG_KMS("mul: %u, div: %u, lanes: %u\n", state->mul, state->div, 983 state->lanes); 984 DRM_DEBUG_KMS("format: %u, vrefresh: %u\n", state->format, 985 state->vrefresh); 986 DRM_DEBUG_KMS("bclk: %lu\n", state->bclk); 987 988 /* 989 * Compute bit clock and round up to the next MHz. 990 */ 991 plld = DIV_ROUND_UP(state->bclk * 8, USEC_PER_SEC) * USEC_PER_SEC; 992 state->period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, plld); 993 994 err = mipi_dphy_timing_get_default(&state->timing, state->period); 995 if (err < 0) 996 return err; 997 998 err = mipi_dphy_timing_validate(&state->timing, state->period); 999 if (err < 0) { 1000 dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err); 1001 return err; 1002 } 1003 1004 /* 1005 * We divide the frequency by two here, but we make up for that by 1006 * setting the shift clock divider (further below) to half of the 1007 * correct value. 1008 */ 1009 plld /= 2; 1010 1011 /* 1012 * Derive pixel clock from bit clock using the shift clock divider. 1013 * Note that this is only half of what we would expect, but we need 1014 * that to make up for the fact that we divided the bit clock by a 1015 * factor of two above. 1016 * 1017 * It's not clear exactly why this is necessary, but the display is 1018 * not working properly otherwise. Perhaps the PLLs cannot generate 1019 * frequencies sufficiently high. 1020 */ 1021 scdiv = ((8 * state->mul) / (state->div * state->lanes)) - 2; 1022 1023 err = tegra_dc_state_setup_clock(dc, crtc_state, dsi->clk_parent, 1024 plld, scdiv); 1025 if (err < 0) { 1026 dev_err(output->dev, "failed to setup CRTC state: %d\n", err); 1027 return err; 1028 } 1029 1030 return err; 1031 } 1032 1033 static const struct drm_encoder_helper_funcs tegra_dsi_encoder_helper_funcs = { 1034 .disable = tegra_dsi_encoder_disable, 1035 .enable = tegra_dsi_encoder_enable, 1036 .atomic_check = tegra_dsi_encoder_atomic_check, 1037 }; 1038 1039 static int tegra_dsi_init(struct host1x_client *client) 1040 { 1041 struct drm_device *drm = dev_get_drvdata(client->host); 1042 struct tegra_dsi *dsi = host1x_client_to_dsi(client); 1043 int err; 1044 1045 /* Gangsters must not register their own outputs. */ 1046 if (!dsi->master) { 1047 dsi->output.dev = client->dev; 1048 1049 drm_connector_init(drm, &dsi->output.connector, 1050 &tegra_dsi_connector_funcs, 1051 DRM_MODE_CONNECTOR_DSI); 1052 drm_connector_helper_add(&dsi->output.connector, 1053 &tegra_dsi_connector_helper_funcs); 1054 dsi->output.connector.dpms = DRM_MODE_DPMS_OFF; 1055 1056 drm_simple_encoder_init(drm, &dsi->output.encoder, 1057 DRM_MODE_ENCODER_DSI); 1058 drm_encoder_helper_add(&dsi->output.encoder, 1059 &tegra_dsi_encoder_helper_funcs); 1060 1061 drm_connector_attach_encoder(&dsi->output.connector, 1062 &dsi->output.encoder); 1063 drm_connector_register(&dsi->output.connector); 1064 1065 err = tegra_output_init(drm, &dsi->output); 1066 if (err < 0) 1067 dev_err(dsi->dev, "failed to initialize output: %d\n", 1068 err); 1069 1070 dsi->output.encoder.possible_crtcs = 0x3; 1071 } 1072 1073 return 0; 1074 } 1075 1076 static int tegra_dsi_exit(struct host1x_client *client) 1077 { 1078 struct tegra_dsi *dsi = host1x_client_to_dsi(client); 1079 1080 tegra_output_exit(&dsi->output); 1081 1082 return 0; 1083 } 1084 1085 static int tegra_dsi_runtime_suspend(struct host1x_client *client) 1086 { 1087 struct tegra_dsi *dsi = host1x_client_to_dsi(client); 1088 struct device *dev = client->dev; 1089 int err; 1090 1091 if (dsi->rst) { 1092 err = reset_control_assert(dsi->rst); 1093 if (err < 0) { 1094 dev_err(dev, "failed to assert reset: %d\n", err); 1095 return err; 1096 } 1097 } 1098 1099 usleep_range(1000, 2000); 1100 1101 clk_disable_unprepare(dsi->clk_lp); 1102 clk_disable_unprepare(dsi->clk); 1103 1104 regulator_disable(dsi->vdd); 1105 pm_runtime_put_sync(dev); 1106 1107 return 0; 1108 } 1109 1110 static int tegra_dsi_runtime_resume(struct host1x_client *client) 1111 { 1112 struct tegra_dsi *dsi = host1x_client_to_dsi(client); 1113 struct device *dev = client->dev; 1114 int err; 1115 1116 err = pm_runtime_resume_and_get(dev); 1117 if (err < 0) { 1118 dev_err(dev, "failed to get runtime PM: %d\n", err); 1119 return err; 1120 } 1121 1122 err = regulator_enable(dsi->vdd); 1123 if (err < 0) { 1124 dev_err(dev, "failed to enable VDD supply: %d\n", err); 1125 goto put_rpm; 1126 } 1127 1128 err = clk_prepare_enable(dsi->clk); 1129 if (err < 0) { 1130 dev_err(dev, "cannot enable DSI clock: %d\n", err); 1131 goto disable_vdd; 1132 } 1133 1134 err = clk_prepare_enable(dsi->clk_lp); 1135 if (err < 0) { 1136 dev_err(dev, "cannot enable low-power clock: %d\n", err); 1137 goto disable_clk; 1138 } 1139 1140 usleep_range(1000, 2000); 1141 1142 if (dsi->rst) { 1143 err = reset_control_deassert(dsi->rst); 1144 if (err < 0) { 1145 dev_err(dev, "cannot assert reset: %d\n", err); 1146 goto disable_clk_lp; 1147 } 1148 } 1149 1150 return 0; 1151 1152 disable_clk_lp: 1153 clk_disable_unprepare(dsi->clk_lp); 1154 disable_clk: 1155 clk_disable_unprepare(dsi->clk); 1156 disable_vdd: 1157 regulator_disable(dsi->vdd); 1158 put_rpm: 1159 pm_runtime_put_sync(dev); 1160 return err; 1161 } 1162 1163 static const struct host1x_client_ops dsi_client_ops = { 1164 .init = tegra_dsi_init, 1165 .exit = tegra_dsi_exit, 1166 .suspend = tegra_dsi_runtime_suspend, 1167 .resume = tegra_dsi_runtime_resume, 1168 }; 1169 1170 static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi) 1171 { 1172 struct clk *parent; 1173 int err; 1174 1175 parent = clk_get_parent(dsi->clk); 1176 if (!parent) 1177 return -EINVAL; 1178 1179 err = clk_set_parent(parent, dsi->clk_parent); 1180 if (err < 0) 1181 return err; 1182 1183 return 0; 1184 } 1185 1186 static const char * const error_report[16] = { 1187 "SoT Error", 1188 "SoT Sync Error", 1189 "EoT Sync Error", 1190 "Escape Mode Entry Command Error", 1191 "Low-Power Transmit Sync Error", 1192 "Peripheral Timeout Error", 1193 "False Control Error", 1194 "Contention Detected", 1195 "ECC Error, single-bit", 1196 "ECC Error, multi-bit", 1197 "Checksum Error", 1198 "DSI Data Type Not Recognized", 1199 "DSI VC ID Invalid", 1200 "Invalid Transmission Length", 1201 "Reserved", 1202 "DSI Protocol Violation", 1203 }; 1204 1205 static ssize_t tegra_dsi_read_response(struct tegra_dsi *dsi, 1206 const struct mipi_dsi_msg *msg, 1207 size_t count) 1208 { 1209 u8 *rx = msg->rx_buf; 1210 unsigned int i, j, k; 1211 size_t size = 0; 1212 u16 errors; 1213 u32 value; 1214 1215 /* read and parse packet header */ 1216 value = tegra_dsi_readl(dsi, DSI_RD_DATA); 1217 1218 switch (value & 0x3f) { 1219 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 1220 errors = (value >> 8) & 0xffff; 1221 dev_dbg(dsi->dev, "Acknowledge and error report: %04x\n", 1222 errors); 1223 for (i = 0; i < ARRAY_SIZE(error_report); i++) 1224 if (errors & BIT(i)) 1225 dev_dbg(dsi->dev, " %2u: %s\n", i, 1226 error_report[i]); 1227 break; 1228 1229 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 1230 rx[0] = (value >> 8) & 0xff; 1231 size = 1; 1232 break; 1233 1234 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 1235 rx[0] = (value >> 8) & 0xff; 1236 rx[1] = (value >> 16) & 0xff; 1237 size = 2; 1238 break; 1239 1240 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE: 1241 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff); 1242 break; 1243 1244 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE: 1245 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff); 1246 break; 1247 1248 default: 1249 dev_err(dsi->dev, "unhandled response type: %02x\n", 1250 value & 0x3f); 1251 return -EPROTO; 1252 } 1253 1254 size = min(size, msg->rx_len); 1255 1256 if (msg->rx_buf && size > 0) { 1257 for (i = 0, j = 0; i < count - 1; i++, j += 4) { 1258 u8 *rx = msg->rx_buf + j; 1259 1260 value = tegra_dsi_readl(dsi, DSI_RD_DATA); 1261 1262 for (k = 0; k < 4 && (j + k) < msg->rx_len; k++) 1263 rx[j + k] = (value >> (k << 3)) & 0xff; 1264 } 1265 } 1266 1267 return size; 1268 } 1269 1270 static int tegra_dsi_transmit(struct tegra_dsi *dsi, unsigned long timeout) 1271 { 1272 tegra_dsi_writel(dsi, DSI_TRIGGER_HOST, DSI_TRIGGER); 1273 1274 timeout = jiffies + msecs_to_jiffies(timeout); 1275 1276 while (time_before(jiffies, timeout)) { 1277 u32 value = tegra_dsi_readl(dsi, DSI_TRIGGER); 1278 if ((value & DSI_TRIGGER_HOST) == 0) 1279 return 0; 1280 1281 usleep_range(1000, 2000); 1282 } 1283 1284 DRM_DEBUG_KMS("timeout waiting for transmission to complete\n"); 1285 return -ETIMEDOUT; 1286 } 1287 1288 static int tegra_dsi_wait_for_response(struct tegra_dsi *dsi, 1289 unsigned long timeout) 1290 { 1291 timeout = jiffies + msecs_to_jiffies(250); 1292 1293 while (time_before(jiffies, timeout)) { 1294 u32 value = tegra_dsi_readl(dsi, DSI_STATUS); 1295 u8 count = value & 0x1f; 1296 1297 if (count > 0) 1298 return count; 1299 1300 usleep_range(1000, 2000); 1301 } 1302 1303 DRM_DEBUG_KMS("peripheral returned no data\n"); 1304 return -ETIMEDOUT; 1305 } 1306 1307 static void tegra_dsi_writesl(struct tegra_dsi *dsi, unsigned long offset, 1308 const void *buffer, size_t size) 1309 { 1310 const u8 *buf = buffer; 1311 size_t i, j; 1312 u32 value; 1313 1314 for (j = 0; j < size; j += 4) { 1315 value = 0; 1316 1317 for (i = 0; i < 4 && j + i < size; i++) 1318 value |= buf[j + i] << (i << 3); 1319 1320 tegra_dsi_writel(dsi, value, DSI_WR_DATA); 1321 } 1322 } 1323 1324 static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host, 1325 const struct mipi_dsi_msg *msg) 1326 { 1327 struct tegra_dsi *dsi = host_to_tegra(host); 1328 struct mipi_dsi_packet packet; 1329 const u8 *header; 1330 size_t count; 1331 ssize_t err; 1332 u32 value; 1333 1334 err = mipi_dsi_create_packet(&packet, msg); 1335 if (err < 0) 1336 return err; 1337 1338 header = packet.header; 1339 1340 /* maximum FIFO depth is 1920 words */ 1341 if (packet.size > dsi->video_fifo_depth * 4) 1342 return -ENOSPC; 1343 1344 /* reset underflow/overflow flags */ 1345 value = tegra_dsi_readl(dsi, DSI_STATUS); 1346 if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) { 1347 value = DSI_HOST_CONTROL_FIFO_RESET; 1348 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); 1349 usleep_range(10, 20); 1350 } 1351 1352 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 1353 value |= DSI_POWER_CONTROL_ENABLE; 1354 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); 1355 1356 usleep_range(5000, 10000); 1357 1358 value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | 1359 DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC; 1360 1361 if ((msg->flags & MIPI_DSI_MSG_USE_LPM) == 0) 1362 value |= DSI_HOST_CONTROL_HS; 1363 1364 /* 1365 * The host FIFO has a maximum of 64 words, so larger transmissions 1366 * need to use the video FIFO. 1367 */ 1368 if (packet.size > dsi->host_fifo_depth * 4) 1369 value |= DSI_HOST_CONTROL_FIFO_SEL; 1370 1371 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); 1372 1373 /* 1374 * For reads and messages with explicitly requested ACK, generate a 1375 * BTA sequence after the transmission of the packet. 1376 */ 1377 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) || 1378 (msg->rx_buf && msg->rx_len > 0)) { 1379 value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL); 1380 value |= DSI_HOST_CONTROL_PKT_BTA; 1381 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); 1382 } 1383 1384 value = DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE; 1385 tegra_dsi_writel(dsi, value, DSI_CONTROL); 1386 1387 /* write packet header, ECC is generated by hardware */ 1388 value = header[2] << 16 | header[1] << 8 | header[0]; 1389 tegra_dsi_writel(dsi, value, DSI_WR_DATA); 1390 1391 /* write payload (if any) */ 1392 if (packet.payload_length > 0) 1393 tegra_dsi_writesl(dsi, DSI_WR_DATA, packet.payload, 1394 packet.payload_length); 1395 1396 err = tegra_dsi_transmit(dsi, 250); 1397 if (err < 0) 1398 return err; 1399 1400 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) || 1401 (msg->rx_buf && msg->rx_len > 0)) { 1402 err = tegra_dsi_wait_for_response(dsi, 250); 1403 if (err < 0) 1404 return err; 1405 1406 count = err; 1407 1408 value = tegra_dsi_readl(dsi, DSI_RD_DATA); 1409 switch (value) { 1410 case 0x84: 1411 /* 1412 dev_dbg(dsi->dev, "ACK\n"); 1413 */ 1414 break; 1415 1416 case 0x87: 1417 /* 1418 dev_dbg(dsi->dev, "ESCAPE\n"); 1419 */ 1420 break; 1421 1422 default: 1423 dev_err(dsi->dev, "unknown status: %08x\n", value); 1424 break; 1425 } 1426 1427 if (count > 1) { 1428 err = tegra_dsi_read_response(dsi, msg, count); 1429 if (err < 0) 1430 dev_err(dsi->dev, 1431 "failed to parse response: %zd\n", 1432 err); 1433 else { 1434 /* 1435 * For read commands, return the number of 1436 * bytes returned by the peripheral. 1437 */ 1438 count = err; 1439 } 1440 } 1441 } else { 1442 /* 1443 * For write commands, we have transmitted the 4-byte header 1444 * plus the variable-length payload. 1445 */ 1446 count = 4 + packet.payload_length; 1447 } 1448 1449 return count; 1450 } 1451 1452 static int tegra_dsi_ganged_setup(struct tegra_dsi *dsi) 1453 { 1454 struct clk *parent; 1455 int err; 1456 1457 /* make sure both DSI controllers share the same PLL */ 1458 parent = clk_get_parent(dsi->slave->clk); 1459 if (!parent) 1460 return -EINVAL; 1461 1462 err = clk_set_parent(parent, dsi->clk_parent); 1463 if (err < 0) 1464 return err; 1465 1466 return 0; 1467 } 1468 1469 static int tegra_dsi_host_attach(struct mipi_dsi_host *host, 1470 struct mipi_dsi_device *device) 1471 { 1472 struct tegra_dsi *dsi = host_to_tegra(host); 1473 1474 dsi->flags = device->mode_flags; 1475 dsi->format = device->format; 1476 dsi->lanes = device->lanes; 1477 1478 if (dsi->slave) { 1479 int err; 1480 1481 dev_dbg(dsi->dev, "attaching dual-channel device %s\n", 1482 dev_name(&device->dev)); 1483 1484 err = tegra_dsi_ganged_setup(dsi); 1485 if (err < 0) { 1486 dev_err(dsi->dev, "failed to set up ganged mode: %d\n", 1487 err); 1488 return err; 1489 } 1490 } 1491 1492 /* 1493 * Slaves don't have a panel associated with them, so they provide 1494 * merely the second channel. 1495 */ 1496 if (!dsi->master) { 1497 struct tegra_output *output = &dsi->output; 1498 1499 output->panel = of_drm_find_panel(device->dev.of_node); 1500 if (IS_ERR(output->panel)) 1501 output->panel = NULL; 1502 1503 if (output->panel && output->connector.dev) 1504 drm_helper_hpd_irq_event(output->connector.dev); 1505 } 1506 1507 return 0; 1508 } 1509 1510 static int tegra_dsi_host_detach(struct mipi_dsi_host *host, 1511 struct mipi_dsi_device *device) 1512 { 1513 struct tegra_dsi *dsi = host_to_tegra(host); 1514 struct tegra_output *output = &dsi->output; 1515 1516 if (output->panel && &device->dev == output->panel->dev) { 1517 output->panel = NULL; 1518 1519 if (output->connector.dev) 1520 drm_helper_hpd_irq_event(output->connector.dev); 1521 } 1522 1523 return 0; 1524 } 1525 1526 static const struct mipi_dsi_host_ops tegra_dsi_host_ops = { 1527 .attach = tegra_dsi_host_attach, 1528 .detach = tegra_dsi_host_detach, 1529 .transfer = tegra_dsi_host_transfer, 1530 }; 1531 1532 static int tegra_dsi_ganged_probe(struct tegra_dsi *dsi) 1533 { 1534 struct device_node *np; 1535 1536 np = of_parse_phandle(dsi->dev->of_node, "nvidia,ganged-mode", 0); 1537 if (np) { 1538 struct platform_device *gangster = of_find_device_by_node(np); 1539 1540 dsi->slave = platform_get_drvdata(gangster); 1541 of_node_put(np); 1542 1543 if (!dsi->slave) 1544 return -EPROBE_DEFER; 1545 1546 dsi->slave->master = dsi; 1547 } 1548 1549 return 0; 1550 } 1551 1552 static int tegra_dsi_probe(struct platform_device *pdev) 1553 { 1554 struct tegra_dsi *dsi; 1555 struct resource *regs; 1556 int err; 1557 1558 dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL); 1559 if (!dsi) 1560 return -ENOMEM; 1561 1562 dsi->output.dev = dsi->dev = &pdev->dev; 1563 dsi->video_fifo_depth = 1920; 1564 dsi->host_fifo_depth = 64; 1565 1566 err = tegra_dsi_ganged_probe(dsi); 1567 if (err < 0) 1568 return err; 1569 1570 err = tegra_output_probe(&dsi->output); 1571 if (err < 0) 1572 return err; 1573 1574 dsi->output.connector.polled = DRM_CONNECTOR_POLL_HPD; 1575 1576 /* 1577 * Assume these values by default. When a DSI peripheral driver 1578 * attaches to the DSI host, the parameters will be taken from 1579 * the attached device. 1580 */ 1581 dsi->flags = MIPI_DSI_MODE_VIDEO; 1582 dsi->format = MIPI_DSI_FMT_RGB888; 1583 dsi->lanes = 4; 1584 1585 if (!pdev->dev.pm_domain) { 1586 dsi->rst = devm_reset_control_get(&pdev->dev, "dsi"); 1587 if (IS_ERR(dsi->rst)) 1588 return PTR_ERR(dsi->rst); 1589 } 1590 1591 dsi->clk = devm_clk_get(&pdev->dev, NULL); 1592 if (IS_ERR(dsi->clk)) { 1593 dev_err(&pdev->dev, "cannot get DSI clock\n"); 1594 return PTR_ERR(dsi->clk); 1595 } 1596 1597 dsi->clk_lp = devm_clk_get(&pdev->dev, "lp"); 1598 if (IS_ERR(dsi->clk_lp)) { 1599 dev_err(&pdev->dev, "cannot get low-power clock\n"); 1600 return PTR_ERR(dsi->clk_lp); 1601 } 1602 1603 dsi->clk_parent = devm_clk_get(&pdev->dev, "parent"); 1604 if (IS_ERR(dsi->clk_parent)) { 1605 dev_err(&pdev->dev, "cannot get parent clock\n"); 1606 return PTR_ERR(dsi->clk_parent); 1607 } 1608 1609 dsi->vdd = devm_regulator_get(&pdev->dev, "avdd-dsi-csi"); 1610 if (IS_ERR(dsi->vdd)) { 1611 dev_err(&pdev->dev, "cannot get VDD supply\n"); 1612 return PTR_ERR(dsi->vdd); 1613 } 1614 1615 err = tegra_dsi_setup_clocks(dsi); 1616 if (err < 0) { 1617 dev_err(&pdev->dev, "cannot setup clocks\n"); 1618 return err; 1619 } 1620 1621 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1622 dsi->regs = devm_ioremap_resource(&pdev->dev, regs); 1623 if (IS_ERR(dsi->regs)) 1624 return PTR_ERR(dsi->regs); 1625 1626 dsi->mipi = tegra_mipi_request(&pdev->dev, pdev->dev.of_node); 1627 if (IS_ERR(dsi->mipi)) 1628 return PTR_ERR(dsi->mipi); 1629 1630 dsi->host.ops = &tegra_dsi_host_ops; 1631 dsi->host.dev = &pdev->dev; 1632 1633 err = mipi_dsi_host_register(&dsi->host); 1634 if (err < 0) { 1635 dev_err(&pdev->dev, "failed to register DSI host: %d\n", err); 1636 goto mipi_free; 1637 } 1638 1639 platform_set_drvdata(pdev, dsi); 1640 pm_runtime_enable(&pdev->dev); 1641 1642 INIT_LIST_HEAD(&dsi->client.list); 1643 dsi->client.ops = &dsi_client_ops; 1644 dsi->client.dev = &pdev->dev; 1645 1646 err = host1x_client_register(&dsi->client); 1647 if (err < 0) { 1648 dev_err(&pdev->dev, "failed to register host1x client: %d\n", 1649 err); 1650 goto unregister; 1651 } 1652 1653 return 0; 1654 1655 unregister: 1656 mipi_dsi_host_unregister(&dsi->host); 1657 mipi_free: 1658 tegra_mipi_free(dsi->mipi); 1659 return err; 1660 } 1661 1662 static int tegra_dsi_remove(struct platform_device *pdev) 1663 { 1664 struct tegra_dsi *dsi = platform_get_drvdata(pdev); 1665 int err; 1666 1667 pm_runtime_disable(&pdev->dev); 1668 1669 err = host1x_client_unregister(&dsi->client); 1670 if (err < 0) { 1671 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", 1672 err); 1673 return err; 1674 } 1675 1676 tegra_output_remove(&dsi->output); 1677 1678 mipi_dsi_host_unregister(&dsi->host); 1679 tegra_mipi_free(dsi->mipi); 1680 1681 return 0; 1682 } 1683 1684 static const struct of_device_id tegra_dsi_of_match[] = { 1685 { .compatible = "nvidia,tegra210-dsi", }, 1686 { .compatible = "nvidia,tegra132-dsi", }, 1687 { .compatible = "nvidia,tegra124-dsi", }, 1688 { .compatible = "nvidia,tegra114-dsi", }, 1689 { }, 1690 }; 1691 MODULE_DEVICE_TABLE(of, tegra_dsi_of_match); 1692 1693 struct platform_driver tegra_dsi_driver = { 1694 .driver = { 1695 .name = "tegra-dsi", 1696 .of_match_table = tegra_dsi_of_match, 1697 }, 1698 .probe = tegra_dsi_probe, 1699 .remove = tegra_dsi_remove, 1700 }; 1701