1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 NVIDIA Corporation 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/debugfs.h> 8 #include <linux/delay.h> 9 #include <linux/host1x.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_platform.h> 13 #include <linux/platform_device.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/reset.h> 17 18 #include <video/mipi_display.h> 19 20 #include <drm/drm_atomic_helper.h> 21 #include <drm/drm_debugfs.h> 22 #include <drm/drm_file.h> 23 #include <drm/drm_mipi_dsi.h> 24 #include <drm/drm_panel.h> 25 #include <drm/drm_print.h> 26 #include <drm/drm_simple_kms_helper.h> 27 28 #include "dc.h" 29 #include "drm.h" 30 #include "dsi.h" 31 #include "mipi-phy.h" 32 #include "trace.h" 33 34 struct tegra_dsi_state { 35 struct drm_connector_state base; 36 37 struct mipi_dphy_timing timing; 38 unsigned long period; 39 40 unsigned int vrefresh; 41 unsigned int lanes; 42 unsigned long pclk; 43 unsigned long bclk; 44 45 enum tegra_dsi_format format; 46 unsigned int mul; 47 unsigned int div; 48 }; 49 50 static inline struct tegra_dsi_state * 51 to_dsi_state(struct drm_connector_state *state) 52 { 53 return container_of(state, struct tegra_dsi_state, base); 54 } 55 56 struct tegra_dsi { 57 struct host1x_client client; 58 struct tegra_output output; 59 struct device *dev; 60 61 void __iomem *regs; 62 63 struct reset_control *rst; 64 struct clk *clk_parent; 65 struct clk *clk_lp; 66 struct clk *clk; 67 68 struct drm_info_list *debugfs_files; 69 70 unsigned long flags; 71 enum mipi_dsi_pixel_format format; 72 unsigned int lanes; 73 74 struct tegra_mipi_device *mipi; 75 struct mipi_dsi_host host; 76 77 struct regulator *vdd; 78 79 unsigned int video_fifo_depth; 80 unsigned int host_fifo_depth; 81 82 /* for ganged-mode support */ 83 struct tegra_dsi *master; 84 struct tegra_dsi *slave; 85 }; 86 87 static inline struct tegra_dsi * 88 host1x_client_to_dsi(struct host1x_client *client) 89 { 90 return container_of(client, struct tegra_dsi, client); 91 } 92 93 static inline struct tegra_dsi *host_to_tegra(struct mipi_dsi_host *host) 94 { 95 return container_of(host, struct tegra_dsi, host); 96 } 97 98 static inline struct tegra_dsi *to_dsi(struct tegra_output *output) 99 { 100 return container_of(output, struct tegra_dsi, output); 101 } 102 103 static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi) 104 { 105 return to_dsi_state(dsi->output.connector.state); 106 } 107 108 static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned int offset) 109 { 110 u32 value = readl(dsi->regs + (offset << 2)); 111 112 trace_dsi_readl(dsi->dev, offset, value); 113 114 return value; 115 } 116 117 static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value, 118 unsigned int offset) 119 { 120 trace_dsi_writel(dsi->dev, offset, value); 121 writel(value, dsi->regs + (offset << 2)); 122 } 123 124 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name } 125 126 static const struct debugfs_reg32 tegra_dsi_regs[] = { 127 DEBUGFS_REG32(DSI_INCR_SYNCPT), 128 DEBUGFS_REG32(DSI_INCR_SYNCPT_CONTROL), 129 DEBUGFS_REG32(DSI_INCR_SYNCPT_ERROR), 130 DEBUGFS_REG32(DSI_CTXSW), 131 DEBUGFS_REG32(DSI_RD_DATA), 132 DEBUGFS_REG32(DSI_WR_DATA), 133 DEBUGFS_REG32(DSI_POWER_CONTROL), 134 DEBUGFS_REG32(DSI_INT_ENABLE), 135 DEBUGFS_REG32(DSI_INT_STATUS), 136 DEBUGFS_REG32(DSI_INT_MASK), 137 DEBUGFS_REG32(DSI_HOST_CONTROL), 138 DEBUGFS_REG32(DSI_CONTROL), 139 DEBUGFS_REG32(DSI_SOL_DELAY), 140 DEBUGFS_REG32(DSI_MAX_THRESHOLD), 141 DEBUGFS_REG32(DSI_TRIGGER), 142 DEBUGFS_REG32(DSI_TX_CRC), 143 DEBUGFS_REG32(DSI_STATUS), 144 DEBUGFS_REG32(DSI_INIT_SEQ_CONTROL), 145 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_0), 146 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_1), 147 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_2), 148 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_3), 149 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_4), 150 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_5), 151 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_6), 152 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_7), 153 DEBUGFS_REG32(DSI_PKT_SEQ_0_LO), 154 DEBUGFS_REG32(DSI_PKT_SEQ_0_HI), 155 DEBUGFS_REG32(DSI_PKT_SEQ_1_LO), 156 DEBUGFS_REG32(DSI_PKT_SEQ_1_HI), 157 DEBUGFS_REG32(DSI_PKT_SEQ_2_LO), 158 DEBUGFS_REG32(DSI_PKT_SEQ_2_HI), 159 DEBUGFS_REG32(DSI_PKT_SEQ_3_LO), 160 DEBUGFS_REG32(DSI_PKT_SEQ_3_HI), 161 DEBUGFS_REG32(DSI_PKT_SEQ_4_LO), 162 DEBUGFS_REG32(DSI_PKT_SEQ_4_HI), 163 DEBUGFS_REG32(DSI_PKT_SEQ_5_LO), 164 DEBUGFS_REG32(DSI_PKT_SEQ_5_HI), 165 DEBUGFS_REG32(DSI_DCS_CMDS), 166 DEBUGFS_REG32(DSI_PKT_LEN_0_1), 167 DEBUGFS_REG32(DSI_PKT_LEN_2_3), 168 DEBUGFS_REG32(DSI_PKT_LEN_4_5), 169 DEBUGFS_REG32(DSI_PKT_LEN_6_7), 170 DEBUGFS_REG32(DSI_PHY_TIMING_0), 171 DEBUGFS_REG32(DSI_PHY_TIMING_1), 172 DEBUGFS_REG32(DSI_PHY_TIMING_2), 173 DEBUGFS_REG32(DSI_BTA_TIMING), 174 DEBUGFS_REG32(DSI_TIMEOUT_0), 175 DEBUGFS_REG32(DSI_TIMEOUT_1), 176 DEBUGFS_REG32(DSI_TO_TALLY), 177 DEBUGFS_REG32(DSI_PAD_CONTROL_0), 178 DEBUGFS_REG32(DSI_PAD_CONTROL_CD), 179 DEBUGFS_REG32(DSI_PAD_CD_STATUS), 180 DEBUGFS_REG32(DSI_VIDEO_MODE_CONTROL), 181 DEBUGFS_REG32(DSI_PAD_CONTROL_1), 182 DEBUGFS_REG32(DSI_PAD_CONTROL_2), 183 DEBUGFS_REG32(DSI_PAD_CONTROL_3), 184 DEBUGFS_REG32(DSI_PAD_CONTROL_4), 185 DEBUGFS_REG32(DSI_GANGED_MODE_CONTROL), 186 DEBUGFS_REG32(DSI_GANGED_MODE_START), 187 DEBUGFS_REG32(DSI_GANGED_MODE_SIZE), 188 DEBUGFS_REG32(DSI_RAW_DATA_BYTE_COUNT), 189 DEBUGFS_REG32(DSI_ULTRA_LOW_POWER_CONTROL), 190 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_8), 191 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_9), 192 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_10), 193 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_11), 194 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_12), 195 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_13), 196 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_14), 197 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_15), 198 }; 199 200 static int tegra_dsi_show_regs(struct seq_file *s, void *data) 201 { 202 struct drm_info_node *node = s->private; 203 struct tegra_dsi *dsi = node->info_ent->data; 204 struct drm_crtc *crtc = dsi->output.encoder.crtc; 205 struct drm_device *drm = node->minor->dev; 206 unsigned int i; 207 int err = 0; 208 209 drm_modeset_lock_all(drm); 210 211 if (!crtc || !crtc->state->active) { 212 err = -EBUSY; 213 goto unlock; 214 } 215 216 for (i = 0; i < ARRAY_SIZE(tegra_dsi_regs); i++) { 217 unsigned int offset = tegra_dsi_regs[i].offset; 218 219 seq_printf(s, "%-32s %#05x %08x\n", tegra_dsi_regs[i].name, 220 offset, tegra_dsi_readl(dsi, offset)); 221 } 222 223 unlock: 224 drm_modeset_unlock_all(drm); 225 return err; 226 } 227 228 static struct drm_info_list debugfs_files[] = { 229 { "regs", tegra_dsi_show_regs, 0, NULL }, 230 }; 231 232 static int tegra_dsi_late_register(struct drm_connector *connector) 233 { 234 struct tegra_output *output = connector_to_output(connector); 235 unsigned int i, count = ARRAY_SIZE(debugfs_files); 236 struct drm_minor *minor = connector->dev->primary; 237 struct dentry *root = connector->debugfs_entry; 238 struct tegra_dsi *dsi = to_dsi(output); 239 240 dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), 241 GFP_KERNEL); 242 if (!dsi->debugfs_files) 243 return -ENOMEM; 244 245 for (i = 0; i < count; i++) 246 dsi->debugfs_files[i].data = dsi; 247 248 drm_debugfs_create_files(dsi->debugfs_files, count, root, minor); 249 250 return 0; 251 } 252 253 static void tegra_dsi_early_unregister(struct drm_connector *connector) 254 { 255 struct tegra_output *output = connector_to_output(connector); 256 unsigned int count = ARRAY_SIZE(debugfs_files); 257 struct tegra_dsi *dsi = to_dsi(output); 258 259 drm_debugfs_remove_files(dsi->debugfs_files, count, 260 connector->debugfs_entry, 261 connector->dev->primary); 262 kfree(dsi->debugfs_files); 263 dsi->debugfs_files = NULL; 264 } 265 266 #define PKT_ID0(id) ((((id) & 0x3f) << 3) | (1 << 9)) 267 #define PKT_LEN0(len) (((len) & 0x07) << 0) 268 #define PKT_ID1(id) ((((id) & 0x3f) << 13) | (1 << 19)) 269 #define PKT_LEN1(len) (((len) & 0x07) << 10) 270 #define PKT_ID2(id) ((((id) & 0x3f) << 23) | (1 << 29)) 271 #define PKT_LEN2(len) (((len) & 0x07) << 20) 272 273 #define PKT_LP (1 << 30) 274 #define NUM_PKT_SEQ 12 275 276 /* 277 * non-burst mode with sync pulses 278 */ 279 static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = { 280 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) | 281 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 282 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | 283 PKT_LP, 284 [ 1] = 0, 285 [ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) | 286 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 287 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | 288 PKT_LP, 289 [ 3] = 0, 290 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 291 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 292 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | 293 PKT_LP, 294 [ 5] = 0, 295 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 296 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 297 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0), 298 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) | 299 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) | 300 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4), 301 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 302 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 303 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | 304 PKT_LP, 305 [ 9] = 0, 306 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 307 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 308 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0), 309 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) | 310 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) | 311 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4), 312 }; 313 314 /* 315 * non-burst mode with sync events 316 */ 317 static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = { 318 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) | 319 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | 320 PKT_LP, 321 [ 1] = 0, 322 [ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 323 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | 324 PKT_LP, 325 [ 3] = 0, 326 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 327 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | 328 PKT_LP, 329 [ 5] = 0, 330 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 331 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) | 332 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3), 333 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4), 334 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 335 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | 336 PKT_LP, 337 [ 9] = 0, 338 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 339 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) | 340 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3), 341 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4), 342 }; 343 344 static const u32 pkt_seq_command_mode[NUM_PKT_SEQ] = { 345 [ 0] = 0, 346 [ 1] = 0, 347 [ 2] = 0, 348 [ 3] = 0, 349 [ 4] = 0, 350 [ 5] = 0, 351 [ 6] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(3) | PKT_LP, 352 [ 7] = 0, 353 [ 8] = 0, 354 [ 9] = 0, 355 [10] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(5) | PKT_LP, 356 [11] = 0, 357 }; 358 359 static void tegra_dsi_set_phy_timing(struct tegra_dsi *dsi, 360 unsigned long period, 361 const struct mipi_dphy_timing *timing) 362 { 363 u32 value; 364 365 value = DSI_TIMING_FIELD(timing->hsexit, period, 1) << 24 | 366 DSI_TIMING_FIELD(timing->hstrail, period, 0) << 16 | 367 DSI_TIMING_FIELD(timing->hszero, period, 3) << 8 | 368 DSI_TIMING_FIELD(timing->hsprepare, period, 1); 369 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0); 370 371 value = DSI_TIMING_FIELD(timing->clktrail, period, 1) << 24 | 372 DSI_TIMING_FIELD(timing->clkpost, period, 1) << 16 | 373 DSI_TIMING_FIELD(timing->clkzero, period, 1) << 8 | 374 DSI_TIMING_FIELD(timing->lpx, period, 1); 375 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1); 376 377 value = DSI_TIMING_FIELD(timing->clkprepare, period, 1) << 16 | 378 DSI_TIMING_FIELD(timing->clkpre, period, 1) << 8 | 379 DSI_TIMING_FIELD(0xff * period, period, 0) << 0; 380 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2); 381 382 value = DSI_TIMING_FIELD(timing->taget, period, 1) << 16 | 383 DSI_TIMING_FIELD(timing->tasure, period, 1) << 8 | 384 DSI_TIMING_FIELD(timing->tago, period, 1); 385 tegra_dsi_writel(dsi, value, DSI_BTA_TIMING); 386 387 if (dsi->slave) 388 tegra_dsi_set_phy_timing(dsi->slave, period, timing); 389 } 390 391 static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format, 392 unsigned int *mulp, unsigned int *divp) 393 { 394 switch (format) { 395 case MIPI_DSI_FMT_RGB666_PACKED: 396 case MIPI_DSI_FMT_RGB888: 397 *mulp = 3; 398 *divp = 1; 399 break; 400 401 case MIPI_DSI_FMT_RGB565: 402 *mulp = 2; 403 *divp = 1; 404 break; 405 406 case MIPI_DSI_FMT_RGB666: 407 *mulp = 9; 408 *divp = 4; 409 break; 410 411 default: 412 return -EINVAL; 413 } 414 415 return 0; 416 } 417 418 static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format, 419 enum tegra_dsi_format *fmt) 420 { 421 switch (format) { 422 case MIPI_DSI_FMT_RGB888: 423 *fmt = TEGRA_DSI_FORMAT_24P; 424 break; 425 426 case MIPI_DSI_FMT_RGB666: 427 *fmt = TEGRA_DSI_FORMAT_18NP; 428 break; 429 430 case MIPI_DSI_FMT_RGB666_PACKED: 431 *fmt = TEGRA_DSI_FORMAT_18P; 432 break; 433 434 case MIPI_DSI_FMT_RGB565: 435 *fmt = TEGRA_DSI_FORMAT_16P; 436 break; 437 438 default: 439 return -EINVAL; 440 } 441 442 return 0; 443 } 444 445 static void tegra_dsi_ganged_enable(struct tegra_dsi *dsi, unsigned int start, 446 unsigned int size) 447 { 448 u32 value; 449 450 tegra_dsi_writel(dsi, start, DSI_GANGED_MODE_START); 451 tegra_dsi_writel(dsi, size << 16 | size, DSI_GANGED_MODE_SIZE); 452 453 value = DSI_GANGED_MODE_CONTROL_ENABLE; 454 tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL); 455 } 456 457 static void tegra_dsi_enable(struct tegra_dsi *dsi) 458 { 459 u32 value; 460 461 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 462 value |= DSI_POWER_CONTROL_ENABLE; 463 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); 464 465 if (dsi->slave) 466 tegra_dsi_enable(dsi->slave); 467 } 468 469 static unsigned int tegra_dsi_get_lanes(struct tegra_dsi *dsi) 470 { 471 if (dsi->master) 472 return dsi->master->lanes + dsi->lanes; 473 474 if (dsi->slave) 475 return dsi->lanes + dsi->slave->lanes; 476 477 return dsi->lanes; 478 } 479 480 static void tegra_dsi_configure(struct tegra_dsi *dsi, unsigned int pipe, 481 const struct drm_display_mode *mode) 482 { 483 unsigned int hact, hsw, hbp, hfp, i, mul, div; 484 struct tegra_dsi_state *state; 485 const u32 *pkt_seq; 486 u32 value; 487 488 /* XXX: pass in state into this function? */ 489 if (dsi->master) 490 state = tegra_dsi_get_state(dsi->master); 491 else 492 state = tegra_dsi_get_state(dsi); 493 494 mul = state->mul; 495 div = state->div; 496 497 if (dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { 498 DRM_DEBUG_KMS("Non-burst video mode with sync pulses\n"); 499 pkt_seq = pkt_seq_video_non_burst_sync_pulses; 500 } else if (dsi->flags & MIPI_DSI_MODE_VIDEO) { 501 DRM_DEBUG_KMS("Non-burst video mode with sync events\n"); 502 pkt_seq = pkt_seq_video_non_burst_sync_events; 503 } else { 504 DRM_DEBUG_KMS("Command mode\n"); 505 pkt_seq = pkt_seq_command_mode; 506 } 507 508 value = DSI_CONTROL_CHANNEL(0) | 509 DSI_CONTROL_FORMAT(state->format) | 510 DSI_CONTROL_LANES(dsi->lanes - 1) | 511 DSI_CONTROL_SOURCE(pipe); 512 tegra_dsi_writel(dsi, value, DSI_CONTROL); 513 514 tegra_dsi_writel(dsi, dsi->video_fifo_depth, DSI_MAX_THRESHOLD); 515 516 value = DSI_HOST_CONTROL_HS; 517 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); 518 519 value = tegra_dsi_readl(dsi, DSI_CONTROL); 520 521 if (dsi->flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) 522 value |= DSI_CONTROL_HS_CLK_CTRL; 523 524 value &= ~DSI_CONTROL_TX_TRIG(3); 525 526 /* enable DCS commands for command mode */ 527 if (dsi->flags & MIPI_DSI_MODE_VIDEO) 528 value &= ~DSI_CONTROL_DCS_ENABLE; 529 else 530 value |= DSI_CONTROL_DCS_ENABLE; 531 532 value |= DSI_CONTROL_VIDEO_ENABLE; 533 value &= ~DSI_CONTROL_HOST_ENABLE; 534 tegra_dsi_writel(dsi, value, DSI_CONTROL); 535 536 for (i = 0; i < NUM_PKT_SEQ; i++) 537 tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i); 538 539 if (dsi->flags & MIPI_DSI_MODE_VIDEO) { 540 /* horizontal active pixels */ 541 hact = mode->hdisplay * mul / div; 542 543 /* horizontal sync width */ 544 hsw = (mode->hsync_end - mode->hsync_start) * mul / div; 545 546 /* horizontal back porch */ 547 hbp = (mode->htotal - mode->hsync_end) * mul / div; 548 549 if ((dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) == 0) 550 hbp += hsw; 551 552 /* horizontal front porch */ 553 hfp = (mode->hsync_start - mode->hdisplay) * mul / div; 554 555 /* subtract packet overhead */ 556 hsw -= 10; 557 hbp -= 14; 558 hfp -= 8; 559 560 tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1); 561 tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3); 562 tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5); 563 tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7); 564 565 /* set SOL delay (for non-burst mode only) */ 566 tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY); 567 568 /* TODO: implement ganged mode */ 569 } else { 570 u16 bytes; 571 572 if (dsi->master || dsi->slave) { 573 /* 574 * For ganged mode, assume symmetric left-right mode. 575 */ 576 bytes = 1 + (mode->hdisplay / 2) * mul / div; 577 } else { 578 /* 1 byte (DCS command) + pixel data */ 579 bytes = 1 + mode->hdisplay * mul / div; 580 } 581 582 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1); 583 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_2_3); 584 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_4_5); 585 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_6_7); 586 587 value = MIPI_DCS_WRITE_MEMORY_START << 8 | 588 MIPI_DCS_WRITE_MEMORY_CONTINUE; 589 tegra_dsi_writel(dsi, value, DSI_DCS_CMDS); 590 591 /* set SOL delay */ 592 if (dsi->master || dsi->slave) { 593 unsigned long delay, bclk, bclk_ganged; 594 unsigned int lanes = state->lanes; 595 596 /* SOL to valid, valid to FIFO and FIFO write delay */ 597 delay = 4 + 4 + 2; 598 delay = DIV_ROUND_UP(delay * mul, div * lanes); 599 /* FIFO read delay */ 600 delay = delay + 6; 601 602 bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes); 603 bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes); 604 value = bclk - bclk_ganged + delay + 20; 605 } else { 606 /* TODO: revisit for non-ganged mode */ 607 value = 8 * mul / div; 608 } 609 610 tegra_dsi_writel(dsi, value, DSI_SOL_DELAY); 611 } 612 613 if (dsi->slave) { 614 tegra_dsi_configure(dsi->slave, pipe, mode); 615 616 /* 617 * TODO: Support modes other than symmetrical left-right 618 * split. 619 */ 620 tegra_dsi_ganged_enable(dsi, 0, mode->hdisplay / 2); 621 tegra_dsi_ganged_enable(dsi->slave, mode->hdisplay / 2, 622 mode->hdisplay / 2); 623 } 624 } 625 626 static int tegra_dsi_wait_idle(struct tegra_dsi *dsi, unsigned long timeout) 627 { 628 u32 value; 629 630 timeout = jiffies + msecs_to_jiffies(timeout); 631 632 while (time_before(jiffies, timeout)) { 633 value = tegra_dsi_readl(dsi, DSI_STATUS); 634 if (value & DSI_STATUS_IDLE) 635 return 0; 636 637 usleep_range(1000, 2000); 638 } 639 640 return -ETIMEDOUT; 641 } 642 643 static void tegra_dsi_video_disable(struct tegra_dsi *dsi) 644 { 645 u32 value; 646 647 value = tegra_dsi_readl(dsi, DSI_CONTROL); 648 value &= ~DSI_CONTROL_VIDEO_ENABLE; 649 tegra_dsi_writel(dsi, value, DSI_CONTROL); 650 651 if (dsi->slave) 652 tegra_dsi_video_disable(dsi->slave); 653 } 654 655 static void tegra_dsi_ganged_disable(struct tegra_dsi *dsi) 656 { 657 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_START); 658 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_SIZE); 659 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_CONTROL); 660 } 661 662 static int tegra_dsi_pad_enable(struct tegra_dsi *dsi) 663 { 664 u32 value; 665 666 value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0); 667 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0); 668 669 return 0; 670 } 671 672 static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi) 673 { 674 u32 value; 675 int err; 676 677 /* 678 * XXX Is this still needed? The module reset is deasserted right 679 * before this function is called. 680 */ 681 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0); 682 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1); 683 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2); 684 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3); 685 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4); 686 687 /* start calibration */ 688 tegra_dsi_pad_enable(dsi); 689 690 value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) | 691 DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) | 692 DSI_PAD_OUT_CLK(0x0); 693 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2); 694 695 value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | 696 DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3); 697 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3); 698 699 err = tegra_mipi_start_calibration(dsi->mipi); 700 if (err < 0) 701 return err; 702 703 return tegra_mipi_finish_calibration(dsi->mipi); 704 } 705 706 static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk, 707 unsigned int vrefresh) 708 { 709 unsigned int timeout; 710 u32 value; 711 712 /* one frame high-speed transmission timeout */ 713 timeout = (bclk / vrefresh) / 512; 714 value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout); 715 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0); 716 717 /* 2 ms peripheral timeout for panel */ 718 timeout = 2 * bclk / 512 * 1000; 719 value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000); 720 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1); 721 722 value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0); 723 tegra_dsi_writel(dsi, value, DSI_TO_TALLY); 724 725 if (dsi->slave) 726 tegra_dsi_set_timeout(dsi->slave, bclk, vrefresh); 727 } 728 729 static void tegra_dsi_disable(struct tegra_dsi *dsi) 730 { 731 u32 value; 732 733 if (dsi->slave) { 734 tegra_dsi_ganged_disable(dsi->slave); 735 tegra_dsi_ganged_disable(dsi); 736 } 737 738 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 739 value &= ~DSI_POWER_CONTROL_ENABLE; 740 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); 741 742 if (dsi->slave) 743 tegra_dsi_disable(dsi->slave); 744 745 usleep_range(5000, 10000); 746 } 747 748 static void tegra_dsi_soft_reset(struct tegra_dsi *dsi) 749 { 750 u32 value; 751 752 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 753 value &= ~DSI_POWER_CONTROL_ENABLE; 754 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); 755 756 usleep_range(300, 1000); 757 758 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 759 value |= DSI_POWER_CONTROL_ENABLE; 760 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); 761 762 usleep_range(300, 1000); 763 764 value = tegra_dsi_readl(dsi, DSI_TRIGGER); 765 if (value) 766 tegra_dsi_writel(dsi, 0, DSI_TRIGGER); 767 768 if (dsi->slave) 769 tegra_dsi_soft_reset(dsi->slave); 770 } 771 772 static void tegra_dsi_connector_reset(struct drm_connector *connector) 773 { 774 struct tegra_dsi_state *state = kzalloc(sizeof(*state), GFP_KERNEL); 775 776 if (!state) 777 return; 778 779 if (connector->state) { 780 __drm_atomic_helper_connector_destroy_state(connector->state); 781 kfree(connector->state); 782 } 783 784 __drm_atomic_helper_connector_reset(connector, &state->base); 785 } 786 787 static struct drm_connector_state * 788 tegra_dsi_connector_duplicate_state(struct drm_connector *connector) 789 { 790 struct tegra_dsi_state *state = to_dsi_state(connector->state); 791 struct tegra_dsi_state *copy; 792 793 copy = kmemdup(state, sizeof(*state), GFP_KERNEL); 794 if (!copy) 795 return NULL; 796 797 __drm_atomic_helper_connector_duplicate_state(connector, 798 ©->base); 799 800 return ©->base; 801 } 802 803 static const struct drm_connector_funcs tegra_dsi_connector_funcs = { 804 .reset = tegra_dsi_connector_reset, 805 .detect = tegra_output_connector_detect, 806 .fill_modes = drm_helper_probe_single_connector_modes, 807 .destroy = tegra_output_connector_destroy, 808 .atomic_duplicate_state = tegra_dsi_connector_duplicate_state, 809 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 810 .late_register = tegra_dsi_late_register, 811 .early_unregister = tegra_dsi_early_unregister, 812 }; 813 814 static enum drm_mode_status 815 tegra_dsi_connector_mode_valid(struct drm_connector *connector, 816 const struct drm_display_mode *mode) 817 { 818 return MODE_OK; 819 } 820 821 static const struct drm_connector_helper_funcs tegra_dsi_connector_helper_funcs = { 822 .get_modes = tegra_output_connector_get_modes, 823 .mode_valid = tegra_dsi_connector_mode_valid, 824 }; 825 826 static void tegra_dsi_unprepare(struct tegra_dsi *dsi) 827 { 828 int err; 829 830 if (dsi->slave) 831 tegra_dsi_unprepare(dsi->slave); 832 833 err = tegra_mipi_disable(dsi->mipi); 834 if (err < 0) 835 dev_err(dsi->dev, "failed to disable MIPI calibration: %d\n", 836 err); 837 838 err = host1x_client_suspend(&dsi->client); 839 if (err < 0) 840 dev_err(dsi->dev, "failed to suspend: %d\n", err); 841 } 842 843 static void tegra_dsi_encoder_disable(struct drm_encoder *encoder) 844 { 845 struct tegra_output *output = encoder_to_output(encoder); 846 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 847 struct tegra_dsi *dsi = to_dsi(output); 848 u32 value; 849 int err; 850 851 if (output->panel) 852 drm_panel_disable(output->panel); 853 854 tegra_dsi_video_disable(dsi); 855 856 /* 857 * The following accesses registers of the display controller, so make 858 * sure it's only executed when the output is attached to one. 859 */ 860 if (dc) { 861 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 862 value &= ~DSI_ENABLE; 863 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 864 865 tegra_dc_commit(dc); 866 } 867 868 err = tegra_dsi_wait_idle(dsi, 100); 869 if (err < 0) 870 dev_dbg(dsi->dev, "failed to idle DSI: %d\n", err); 871 872 tegra_dsi_soft_reset(dsi); 873 874 if (output->panel) 875 drm_panel_unprepare(output->panel); 876 877 tegra_dsi_disable(dsi); 878 879 tegra_dsi_unprepare(dsi); 880 } 881 882 static int tegra_dsi_prepare(struct tegra_dsi *dsi) 883 { 884 int err; 885 886 err = host1x_client_resume(&dsi->client); 887 if (err < 0) { 888 dev_err(dsi->dev, "failed to resume: %d\n", err); 889 return err; 890 } 891 892 err = tegra_mipi_enable(dsi->mipi); 893 if (err < 0) 894 dev_err(dsi->dev, "failed to enable MIPI calibration: %d\n", 895 err); 896 897 err = tegra_dsi_pad_calibrate(dsi); 898 if (err < 0) 899 dev_err(dsi->dev, "MIPI calibration failed: %d\n", err); 900 901 if (dsi->slave) 902 tegra_dsi_prepare(dsi->slave); 903 904 return 0; 905 } 906 907 static void tegra_dsi_encoder_enable(struct drm_encoder *encoder) 908 { 909 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 910 struct tegra_output *output = encoder_to_output(encoder); 911 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 912 struct tegra_dsi *dsi = to_dsi(output); 913 struct tegra_dsi_state *state; 914 u32 value; 915 int err; 916 917 /* If the bootloader enabled DSI it needs to be disabled 918 * in order for the panel initialization commands to be 919 * properly sent. 920 */ 921 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 922 923 if (value & DSI_POWER_CONTROL_ENABLE) 924 tegra_dsi_disable(dsi); 925 926 err = tegra_dsi_prepare(dsi); 927 if (err < 0) { 928 dev_err(dsi->dev, "failed to prepare: %d\n", err); 929 return; 930 } 931 932 state = tegra_dsi_get_state(dsi); 933 934 tegra_dsi_set_timeout(dsi, state->bclk, state->vrefresh); 935 936 /* 937 * The D-PHY timing fields are expressed in byte-clock cycles, so 938 * multiply the period by 8. 939 */ 940 tegra_dsi_set_phy_timing(dsi, state->period * 8, &state->timing); 941 942 if (output->panel) 943 drm_panel_prepare(output->panel); 944 945 tegra_dsi_configure(dsi, dc->pipe, mode); 946 947 /* enable display controller */ 948 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 949 value |= DSI_ENABLE; 950 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 951 952 tegra_dc_commit(dc); 953 954 /* enable DSI controller */ 955 tegra_dsi_enable(dsi); 956 957 if (output->panel) 958 drm_panel_enable(output->panel); 959 } 960 961 static int 962 tegra_dsi_encoder_atomic_check(struct drm_encoder *encoder, 963 struct drm_crtc_state *crtc_state, 964 struct drm_connector_state *conn_state) 965 { 966 struct tegra_output *output = encoder_to_output(encoder); 967 struct tegra_dsi_state *state = to_dsi_state(conn_state); 968 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc); 969 struct tegra_dsi *dsi = to_dsi(output); 970 unsigned int scdiv; 971 unsigned long plld; 972 int err; 973 974 state->pclk = crtc_state->mode.clock * 1000; 975 976 err = tegra_dsi_get_muldiv(dsi->format, &state->mul, &state->div); 977 if (err < 0) 978 return err; 979 980 state->lanes = tegra_dsi_get_lanes(dsi); 981 982 err = tegra_dsi_get_format(dsi->format, &state->format); 983 if (err < 0) 984 return err; 985 986 state->vrefresh = drm_mode_vrefresh(&crtc_state->mode); 987 988 /* compute byte clock */ 989 state->bclk = (state->pclk * state->mul) / (state->div * state->lanes); 990 991 DRM_DEBUG_KMS("mul: %u, div: %u, lanes: %u\n", state->mul, state->div, 992 state->lanes); 993 DRM_DEBUG_KMS("format: %u, vrefresh: %u\n", state->format, 994 state->vrefresh); 995 DRM_DEBUG_KMS("bclk: %lu\n", state->bclk); 996 997 /* 998 * Compute bit clock and round up to the next MHz. 999 */ 1000 plld = DIV_ROUND_UP(state->bclk * 8, USEC_PER_SEC) * USEC_PER_SEC; 1001 state->period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, plld); 1002 1003 err = mipi_dphy_timing_get_default(&state->timing, state->period); 1004 if (err < 0) 1005 return err; 1006 1007 err = mipi_dphy_timing_validate(&state->timing, state->period); 1008 if (err < 0) { 1009 dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err); 1010 return err; 1011 } 1012 1013 /* 1014 * We divide the frequency by two here, but we make up for that by 1015 * setting the shift clock divider (further below) to half of the 1016 * correct value. 1017 */ 1018 plld /= 2; 1019 1020 /* 1021 * Derive pixel clock from bit clock using the shift clock divider. 1022 * Note that this is only half of what we would expect, but we need 1023 * that to make up for the fact that we divided the bit clock by a 1024 * factor of two above. 1025 * 1026 * It's not clear exactly why this is necessary, but the display is 1027 * not working properly otherwise. Perhaps the PLLs cannot generate 1028 * frequencies sufficiently high. 1029 */ 1030 scdiv = ((8 * state->mul) / (state->div * state->lanes)) - 2; 1031 1032 err = tegra_dc_state_setup_clock(dc, crtc_state, dsi->clk_parent, 1033 plld, scdiv); 1034 if (err < 0) { 1035 dev_err(output->dev, "failed to setup CRTC state: %d\n", err); 1036 return err; 1037 } 1038 1039 return err; 1040 } 1041 1042 static const struct drm_encoder_helper_funcs tegra_dsi_encoder_helper_funcs = { 1043 .disable = tegra_dsi_encoder_disable, 1044 .enable = tegra_dsi_encoder_enable, 1045 .atomic_check = tegra_dsi_encoder_atomic_check, 1046 }; 1047 1048 static int tegra_dsi_init(struct host1x_client *client) 1049 { 1050 struct drm_device *drm = dev_get_drvdata(client->host); 1051 struct tegra_dsi *dsi = host1x_client_to_dsi(client); 1052 int err; 1053 1054 /* Gangsters must not register their own outputs. */ 1055 if (!dsi->master) { 1056 dsi->output.dev = client->dev; 1057 1058 drm_connector_init(drm, &dsi->output.connector, 1059 &tegra_dsi_connector_funcs, 1060 DRM_MODE_CONNECTOR_DSI); 1061 drm_connector_helper_add(&dsi->output.connector, 1062 &tegra_dsi_connector_helper_funcs); 1063 dsi->output.connector.dpms = DRM_MODE_DPMS_OFF; 1064 1065 drm_simple_encoder_init(drm, &dsi->output.encoder, 1066 DRM_MODE_ENCODER_DSI); 1067 drm_encoder_helper_add(&dsi->output.encoder, 1068 &tegra_dsi_encoder_helper_funcs); 1069 1070 drm_connector_attach_encoder(&dsi->output.connector, 1071 &dsi->output.encoder); 1072 drm_connector_register(&dsi->output.connector); 1073 1074 err = tegra_output_init(drm, &dsi->output); 1075 if (err < 0) 1076 dev_err(dsi->dev, "failed to initialize output: %d\n", 1077 err); 1078 1079 dsi->output.encoder.possible_crtcs = 0x3; 1080 } 1081 1082 return 0; 1083 } 1084 1085 static int tegra_dsi_exit(struct host1x_client *client) 1086 { 1087 struct tegra_dsi *dsi = host1x_client_to_dsi(client); 1088 1089 tegra_output_exit(&dsi->output); 1090 1091 return 0; 1092 } 1093 1094 static int tegra_dsi_runtime_suspend(struct host1x_client *client) 1095 { 1096 struct tegra_dsi *dsi = host1x_client_to_dsi(client); 1097 struct device *dev = client->dev; 1098 int err; 1099 1100 if (dsi->rst) { 1101 err = reset_control_assert(dsi->rst); 1102 if (err < 0) { 1103 dev_err(dev, "failed to assert reset: %d\n", err); 1104 return err; 1105 } 1106 } 1107 1108 usleep_range(1000, 2000); 1109 1110 clk_disable_unprepare(dsi->clk_lp); 1111 clk_disable_unprepare(dsi->clk); 1112 1113 regulator_disable(dsi->vdd); 1114 pm_runtime_put_sync(dev); 1115 1116 return 0; 1117 } 1118 1119 static int tegra_dsi_runtime_resume(struct host1x_client *client) 1120 { 1121 struct tegra_dsi *dsi = host1x_client_to_dsi(client); 1122 struct device *dev = client->dev; 1123 int err; 1124 1125 err = pm_runtime_resume_and_get(dev); 1126 if (err < 0) { 1127 dev_err(dev, "failed to get runtime PM: %d\n", err); 1128 return err; 1129 } 1130 1131 err = regulator_enable(dsi->vdd); 1132 if (err < 0) { 1133 dev_err(dev, "failed to enable VDD supply: %d\n", err); 1134 goto put_rpm; 1135 } 1136 1137 err = clk_prepare_enable(dsi->clk); 1138 if (err < 0) { 1139 dev_err(dev, "cannot enable DSI clock: %d\n", err); 1140 goto disable_vdd; 1141 } 1142 1143 err = clk_prepare_enable(dsi->clk_lp); 1144 if (err < 0) { 1145 dev_err(dev, "cannot enable low-power clock: %d\n", err); 1146 goto disable_clk; 1147 } 1148 1149 usleep_range(1000, 2000); 1150 1151 if (dsi->rst) { 1152 err = reset_control_deassert(dsi->rst); 1153 if (err < 0) { 1154 dev_err(dev, "cannot assert reset: %d\n", err); 1155 goto disable_clk_lp; 1156 } 1157 } 1158 1159 return 0; 1160 1161 disable_clk_lp: 1162 clk_disable_unprepare(dsi->clk_lp); 1163 disable_clk: 1164 clk_disable_unprepare(dsi->clk); 1165 disable_vdd: 1166 regulator_disable(dsi->vdd); 1167 put_rpm: 1168 pm_runtime_put_sync(dev); 1169 return err; 1170 } 1171 1172 static const struct host1x_client_ops dsi_client_ops = { 1173 .init = tegra_dsi_init, 1174 .exit = tegra_dsi_exit, 1175 .suspend = tegra_dsi_runtime_suspend, 1176 .resume = tegra_dsi_runtime_resume, 1177 }; 1178 1179 static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi) 1180 { 1181 struct clk *parent; 1182 int err; 1183 1184 parent = clk_get_parent(dsi->clk); 1185 if (!parent) 1186 return -EINVAL; 1187 1188 err = clk_set_parent(parent, dsi->clk_parent); 1189 if (err < 0) 1190 return err; 1191 1192 return 0; 1193 } 1194 1195 static const char * const error_report[16] = { 1196 "SoT Error", 1197 "SoT Sync Error", 1198 "EoT Sync Error", 1199 "Escape Mode Entry Command Error", 1200 "Low-Power Transmit Sync Error", 1201 "Peripheral Timeout Error", 1202 "False Control Error", 1203 "Contention Detected", 1204 "ECC Error, single-bit", 1205 "ECC Error, multi-bit", 1206 "Checksum Error", 1207 "DSI Data Type Not Recognized", 1208 "DSI VC ID Invalid", 1209 "Invalid Transmission Length", 1210 "Reserved", 1211 "DSI Protocol Violation", 1212 }; 1213 1214 static ssize_t tegra_dsi_read_response(struct tegra_dsi *dsi, 1215 const struct mipi_dsi_msg *msg, 1216 size_t count) 1217 { 1218 u8 *rx = msg->rx_buf; 1219 unsigned int i, j, k; 1220 size_t size = 0; 1221 u16 errors; 1222 u32 value; 1223 1224 /* read and parse packet header */ 1225 value = tegra_dsi_readl(dsi, DSI_RD_DATA); 1226 1227 switch (value & 0x3f) { 1228 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 1229 errors = (value >> 8) & 0xffff; 1230 dev_dbg(dsi->dev, "Acknowledge and error report: %04x\n", 1231 errors); 1232 for (i = 0; i < ARRAY_SIZE(error_report); i++) 1233 if (errors & BIT(i)) 1234 dev_dbg(dsi->dev, " %2u: %s\n", i, 1235 error_report[i]); 1236 break; 1237 1238 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 1239 rx[0] = (value >> 8) & 0xff; 1240 size = 1; 1241 break; 1242 1243 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 1244 rx[0] = (value >> 8) & 0xff; 1245 rx[1] = (value >> 16) & 0xff; 1246 size = 2; 1247 break; 1248 1249 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE: 1250 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff); 1251 break; 1252 1253 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE: 1254 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff); 1255 break; 1256 1257 default: 1258 dev_err(dsi->dev, "unhandled response type: %02x\n", 1259 value & 0x3f); 1260 return -EPROTO; 1261 } 1262 1263 size = min(size, msg->rx_len); 1264 1265 if (msg->rx_buf && size > 0) { 1266 for (i = 0, j = 0; i < count - 1; i++, j += 4) { 1267 u8 *rx = msg->rx_buf + j; 1268 1269 value = tegra_dsi_readl(dsi, DSI_RD_DATA); 1270 1271 for (k = 0; k < 4 && (j + k) < msg->rx_len; k++) 1272 rx[j + k] = (value >> (k << 3)) & 0xff; 1273 } 1274 } 1275 1276 return size; 1277 } 1278 1279 static int tegra_dsi_transmit(struct tegra_dsi *dsi, unsigned long timeout) 1280 { 1281 tegra_dsi_writel(dsi, DSI_TRIGGER_HOST, DSI_TRIGGER); 1282 1283 timeout = jiffies + msecs_to_jiffies(timeout); 1284 1285 while (time_before(jiffies, timeout)) { 1286 u32 value = tegra_dsi_readl(dsi, DSI_TRIGGER); 1287 if ((value & DSI_TRIGGER_HOST) == 0) 1288 return 0; 1289 1290 usleep_range(1000, 2000); 1291 } 1292 1293 DRM_DEBUG_KMS("timeout waiting for transmission to complete\n"); 1294 return -ETIMEDOUT; 1295 } 1296 1297 static int tegra_dsi_wait_for_response(struct tegra_dsi *dsi, 1298 unsigned long timeout) 1299 { 1300 timeout = jiffies + msecs_to_jiffies(250); 1301 1302 while (time_before(jiffies, timeout)) { 1303 u32 value = tegra_dsi_readl(dsi, DSI_STATUS); 1304 u8 count = value & 0x1f; 1305 1306 if (count > 0) 1307 return count; 1308 1309 usleep_range(1000, 2000); 1310 } 1311 1312 DRM_DEBUG_KMS("peripheral returned no data\n"); 1313 return -ETIMEDOUT; 1314 } 1315 1316 static void tegra_dsi_writesl(struct tegra_dsi *dsi, unsigned long offset, 1317 const void *buffer, size_t size) 1318 { 1319 const u8 *buf = buffer; 1320 size_t i, j; 1321 u32 value; 1322 1323 for (j = 0; j < size; j += 4) { 1324 value = 0; 1325 1326 for (i = 0; i < 4 && j + i < size; i++) 1327 value |= buf[j + i] << (i << 3); 1328 1329 tegra_dsi_writel(dsi, value, DSI_WR_DATA); 1330 } 1331 } 1332 1333 static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host, 1334 const struct mipi_dsi_msg *msg) 1335 { 1336 struct tegra_dsi *dsi = host_to_tegra(host); 1337 struct mipi_dsi_packet packet; 1338 const u8 *header; 1339 size_t count; 1340 ssize_t err; 1341 u32 value; 1342 1343 err = mipi_dsi_create_packet(&packet, msg); 1344 if (err < 0) 1345 return err; 1346 1347 header = packet.header; 1348 1349 /* maximum FIFO depth is 1920 words */ 1350 if (packet.size > dsi->video_fifo_depth * 4) 1351 return -ENOSPC; 1352 1353 /* reset underflow/overflow flags */ 1354 value = tegra_dsi_readl(dsi, DSI_STATUS); 1355 if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) { 1356 value = DSI_HOST_CONTROL_FIFO_RESET; 1357 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); 1358 usleep_range(10, 20); 1359 } 1360 1361 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 1362 value |= DSI_POWER_CONTROL_ENABLE; 1363 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); 1364 1365 usleep_range(5000, 10000); 1366 1367 value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | 1368 DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC; 1369 1370 if ((msg->flags & MIPI_DSI_MSG_USE_LPM) == 0) 1371 value |= DSI_HOST_CONTROL_HS; 1372 1373 /* 1374 * The host FIFO has a maximum of 64 words, so larger transmissions 1375 * need to use the video FIFO. 1376 */ 1377 if (packet.size > dsi->host_fifo_depth * 4) 1378 value |= DSI_HOST_CONTROL_FIFO_SEL; 1379 1380 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); 1381 1382 /* 1383 * For reads and messages with explicitly requested ACK, generate a 1384 * BTA sequence after the transmission of the packet. 1385 */ 1386 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) || 1387 (msg->rx_buf && msg->rx_len > 0)) { 1388 value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL); 1389 value |= DSI_HOST_CONTROL_PKT_BTA; 1390 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); 1391 } 1392 1393 value = DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE; 1394 tegra_dsi_writel(dsi, value, DSI_CONTROL); 1395 1396 /* write packet header, ECC is generated by hardware */ 1397 value = header[2] << 16 | header[1] << 8 | header[0]; 1398 tegra_dsi_writel(dsi, value, DSI_WR_DATA); 1399 1400 /* write payload (if any) */ 1401 if (packet.payload_length > 0) 1402 tegra_dsi_writesl(dsi, DSI_WR_DATA, packet.payload, 1403 packet.payload_length); 1404 1405 err = tegra_dsi_transmit(dsi, 250); 1406 if (err < 0) 1407 return err; 1408 1409 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) || 1410 (msg->rx_buf && msg->rx_len > 0)) { 1411 err = tegra_dsi_wait_for_response(dsi, 250); 1412 if (err < 0) 1413 return err; 1414 1415 count = err; 1416 1417 value = tegra_dsi_readl(dsi, DSI_RD_DATA); 1418 switch (value) { 1419 case 0x84: 1420 /* 1421 dev_dbg(dsi->dev, "ACK\n"); 1422 */ 1423 break; 1424 1425 case 0x87: 1426 /* 1427 dev_dbg(dsi->dev, "ESCAPE\n"); 1428 */ 1429 break; 1430 1431 default: 1432 dev_err(dsi->dev, "unknown status: %08x\n", value); 1433 break; 1434 } 1435 1436 if (count > 1) { 1437 err = tegra_dsi_read_response(dsi, msg, count); 1438 if (err < 0) 1439 dev_err(dsi->dev, 1440 "failed to parse response: %zd\n", 1441 err); 1442 else { 1443 /* 1444 * For read commands, return the number of 1445 * bytes returned by the peripheral. 1446 */ 1447 count = err; 1448 } 1449 } 1450 } else { 1451 /* 1452 * For write commands, we have transmitted the 4-byte header 1453 * plus the variable-length payload. 1454 */ 1455 count = 4 + packet.payload_length; 1456 } 1457 1458 return count; 1459 } 1460 1461 static int tegra_dsi_ganged_setup(struct tegra_dsi *dsi) 1462 { 1463 struct clk *parent; 1464 int err; 1465 1466 /* make sure both DSI controllers share the same PLL */ 1467 parent = clk_get_parent(dsi->slave->clk); 1468 if (!parent) 1469 return -EINVAL; 1470 1471 err = clk_set_parent(parent, dsi->clk_parent); 1472 if (err < 0) 1473 return err; 1474 1475 return 0; 1476 } 1477 1478 static int tegra_dsi_host_attach(struct mipi_dsi_host *host, 1479 struct mipi_dsi_device *device) 1480 { 1481 struct tegra_dsi *dsi = host_to_tegra(host); 1482 1483 dsi->flags = device->mode_flags; 1484 dsi->format = device->format; 1485 dsi->lanes = device->lanes; 1486 1487 if (dsi->slave) { 1488 int err; 1489 1490 dev_dbg(dsi->dev, "attaching dual-channel device %s\n", 1491 dev_name(&device->dev)); 1492 1493 err = tegra_dsi_ganged_setup(dsi); 1494 if (err < 0) { 1495 dev_err(dsi->dev, "failed to set up ganged mode: %d\n", 1496 err); 1497 return err; 1498 } 1499 } 1500 1501 /* 1502 * Slaves don't have a panel associated with them, so they provide 1503 * merely the second channel. 1504 */ 1505 if (!dsi->master) { 1506 struct tegra_output *output = &dsi->output; 1507 1508 output->panel = of_drm_find_panel(device->dev.of_node); 1509 if (IS_ERR(output->panel)) 1510 output->panel = NULL; 1511 1512 if (output->panel && output->connector.dev) 1513 drm_helper_hpd_irq_event(output->connector.dev); 1514 } 1515 1516 return 0; 1517 } 1518 1519 static int tegra_dsi_host_detach(struct mipi_dsi_host *host, 1520 struct mipi_dsi_device *device) 1521 { 1522 struct tegra_dsi *dsi = host_to_tegra(host); 1523 struct tegra_output *output = &dsi->output; 1524 1525 if (output->panel && &device->dev == output->panel->dev) { 1526 output->panel = NULL; 1527 1528 if (output->connector.dev) 1529 drm_helper_hpd_irq_event(output->connector.dev); 1530 } 1531 1532 return 0; 1533 } 1534 1535 static const struct mipi_dsi_host_ops tegra_dsi_host_ops = { 1536 .attach = tegra_dsi_host_attach, 1537 .detach = tegra_dsi_host_detach, 1538 .transfer = tegra_dsi_host_transfer, 1539 }; 1540 1541 static int tegra_dsi_ganged_probe(struct tegra_dsi *dsi) 1542 { 1543 struct device_node *np; 1544 1545 np = of_parse_phandle(dsi->dev->of_node, "nvidia,ganged-mode", 0); 1546 if (np) { 1547 struct platform_device *gangster = of_find_device_by_node(np); 1548 of_node_put(np); 1549 if (!gangster) 1550 return -EPROBE_DEFER; 1551 1552 dsi->slave = platform_get_drvdata(gangster); 1553 1554 if (!dsi->slave) { 1555 put_device(&gangster->dev); 1556 return -EPROBE_DEFER; 1557 } 1558 1559 dsi->slave->master = dsi; 1560 } 1561 1562 return 0; 1563 } 1564 1565 static int tegra_dsi_probe(struct platform_device *pdev) 1566 { 1567 struct tegra_dsi *dsi; 1568 int err; 1569 1570 dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL); 1571 if (!dsi) 1572 return -ENOMEM; 1573 1574 dsi->output.dev = dsi->dev = &pdev->dev; 1575 dsi->video_fifo_depth = 1920; 1576 dsi->host_fifo_depth = 64; 1577 1578 err = tegra_dsi_ganged_probe(dsi); 1579 if (err < 0) 1580 return err; 1581 1582 err = tegra_output_probe(&dsi->output); 1583 if (err < 0) 1584 return err; 1585 1586 dsi->output.connector.polled = DRM_CONNECTOR_POLL_HPD; 1587 1588 /* 1589 * Assume these values by default. When a DSI peripheral driver 1590 * attaches to the DSI host, the parameters will be taken from 1591 * the attached device. 1592 */ 1593 dsi->flags = MIPI_DSI_MODE_VIDEO; 1594 dsi->format = MIPI_DSI_FMT_RGB888; 1595 dsi->lanes = 4; 1596 1597 if (!pdev->dev.pm_domain) { 1598 dsi->rst = devm_reset_control_get(&pdev->dev, "dsi"); 1599 if (IS_ERR(dsi->rst)) { 1600 err = PTR_ERR(dsi->rst); 1601 goto remove; 1602 } 1603 } 1604 1605 dsi->clk = devm_clk_get(&pdev->dev, NULL); 1606 if (IS_ERR(dsi->clk)) { 1607 err = dev_err_probe(&pdev->dev, PTR_ERR(dsi->clk), 1608 "cannot get DSI clock\n"); 1609 goto remove; 1610 } 1611 1612 dsi->clk_lp = devm_clk_get(&pdev->dev, "lp"); 1613 if (IS_ERR(dsi->clk_lp)) { 1614 err = dev_err_probe(&pdev->dev, PTR_ERR(dsi->clk_lp), 1615 "cannot get low-power clock\n"); 1616 goto remove; 1617 } 1618 1619 dsi->clk_parent = devm_clk_get(&pdev->dev, "parent"); 1620 if (IS_ERR(dsi->clk_parent)) { 1621 err = dev_err_probe(&pdev->dev, PTR_ERR(dsi->clk_parent), 1622 "cannot get parent clock\n"); 1623 goto remove; 1624 } 1625 1626 dsi->vdd = devm_regulator_get(&pdev->dev, "avdd-dsi-csi"); 1627 if (IS_ERR(dsi->vdd)) { 1628 err = dev_err_probe(&pdev->dev, PTR_ERR(dsi->vdd), 1629 "cannot get VDD supply\n"); 1630 goto remove; 1631 } 1632 1633 err = tegra_dsi_setup_clocks(dsi); 1634 if (err < 0) { 1635 dev_err(&pdev->dev, "cannot setup clocks\n"); 1636 goto remove; 1637 } 1638 1639 dsi->regs = devm_platform_ioremap_resource(pdev, 0); 1640 if (IS_ERR(dsi->regs)) { 1641 err = PTR_ERR(dsi->regs); 1642 goto remove; 1643 } 1644 1645 dsi->mipi = tegra_mipi_request(&pdev->dev, pdev->dev.of_node); 1646 if (IS_ERR(dsi->mipi)) { 1647 err = PTR_ERR(dsi->mipi); 1648 goto remove; 1649 } 1650 1651 dsi->host.ops = &tegra_dsi_host_ops; 1652 dsi->host.dev = &pdev->dev; 1653 1654 err = mipi_dsi_host_register(&dsi->host); 1655 if (err < 0) { 1656 dev_err(&pdev->dev, "failed to register DSI host: %d\n", err); 1657 goto mipi_free; 1658 } 1659 1660 platform_set_drvdata(pdev, dsi); 1661 pm_runtime_enable(&pdev->dev); 1662 1663 INIT_LIST_HEAD(&dsi->client.list); 1664 dsi->client.ops = &dsi_client_ops; 1665 dsi->client.dev = &pdev->dev; 1666 1667 err = host1x_client_register(&dsi->client); 1668 if (err < 0) { 1669 dev_err(&pdev->dev, "failed to register host1x client: %d\n", 1670 err); 1671 goto unregister; 1672 } 1673 1674 return 0; 1675 1676 unregister: 1677 pm_runtime_disable(&pdev->dev); 1678 mipi_dsi_host_unregister(&dsi->host); 1679 mipi_free: 1680 tegra_mipi_free(dsi->mipi); 1681 remove: 1682 tegra_output_remove(&dsi->output); 1683 return err; 1684 } 1685 1686 static void tegra_dsi_remove(struct platform_device *pdev) 1687 { 1688 struct tegra_dsi *dsi = platform_get_drvdata(pdev); 1689 1690 pm_runtime_disable(&pdev->dev); 1691 1692 host1x_client_unregister(&dsi->client); 1693 1694 tegra_output_remove(&dsi->output); 1695 1696 mipi_dsi_host_unregister(&dsi->host); 1697 tegra_mipi_free(dsi->mipi); 1698 } 1699 1700 static const struct of_device_id tegra_dsi_of_match[] = { 1701 { .compatible = "nvidia,tegra210-dsi", }, 1702 { .compatible = "nvidia,tegra132-dsi", }, 1703 { .compatible = "nvidia,tegra124-dsi", }, 1704 { .compatible = "nvidia,tegra114-dsi", }, 1705 { }, 1706 }; 1707 MODULE_DEVICE_TABLE(of, tegra_dsi_of_match); 1708 1709 struct platform_driver tegra_dsi_driver = { 1710 .driver = { 1711 .name = "tegra-dsi", 1712 .of_match_table = tegra_dsi_of_match, 1713 }, 1714 .probe = tegra_dsi_probe, 1715 .remove = tegra_dsi_remove, 1716 }; 1717