1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 NVIDIA Corporation 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/debugfs.h> 8 #include <linux/delay.h> 9 #include <linux/host1x.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_platform.h> 13 #include <linux/platform_device.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/reset.h> 17 #include <linux/tegra-mipi-cal.h> 18 19 #include <video/mipi_display.h> 20 21 #include <drm/drm_atomic_helper.h> 22 #include <drm/drm_debugfs.h> 23 #include <drm/drm_encoder.h> 24 #include <drm/drm_file.h> 25 #include <drm/drm_mipi_dsi.h> 26 #include <drm/drm_panel.h> 27 #include <drm/drm_print.h> 28 29 #include "dc.h" 30 #include "drm.h" 31 #include "dsi.h" 32 #include "mipi-phy.h" 33 #include "trace.h" 34 35 struct tegra_dsi_state { 36 struct drm_connector_state base; 37 38 struct mipi_dphy_timing timing; 39 unsigned long period; 40 41 unsigned int vrefresh; 42 unsigned int lanes; 43 unsigned long pclk; 44 unsigned long bclk; 45 46 enum tegra_dsi_format format; 47 unsigned int mul; 48 unsigned int div; 49 }; 50 51 static inline struct tegra_dsi_state * 52 to_dsi_state(struct drm_connector_state *state) 53 { 54 return container_of(state, struct tegra_dsi_state, base); 55 } 56 57 struct tegra_dsi_config { 58 bool has_multiple_pad_controls; 59 bool has_mux_parent_clk; 60 }; 61 62 struct tegra_dsi { 63 struct host1x_client client; 64 struct tegra_output output; 65 struct device *dev; 66 67 void __iomem *regs; 68 69 struct reset_control *rst; 70 struct clk *clk_parent; 71 struct clk *clk_lp; 72 struct clk *clk; 73 74 struct drm_info_list *debugfs_files; 75 76 unsigned long flags; 77 enum mipi_dsi_pixel_format format; 78 unsigned int lanes; 79 80 struct tegra_mipi_device *mipi; 81 struct mipi_dsi_host host; 82 83 struct regulator *vdd; 84 85 unsigned int video_fifo_depth; 86 unsigned int host_fifo_depth; 87 88 /* for ganged-mode support */ 89 struct tegra_dsi *master; 90 struct tegra_dsi *slave; 91 92 const struct tegra_dsi_config *config; 93 }; 94 95 static inline struct tegra_dsi * 96 host1x_client_to_dsi(struct host1x_client *client) 97 { 98 return container_of(client, struct tegra_dsi, client); 99 } 100 101 static inline struct tegra_dsi *host_to_tegra(struct mipi_dsi_host *host) 102 { 103 return container_of(host, struct tegra_dsi, host); 104 } 105 106 static inline struct tegra_dsi *to_dsi(struct tegra_output *output) 107 { 108 return container_of(output, struct tegra_dsi, output); 109 } 110 111 static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi) 112 { 113 return to_dsi_state(dsi->output.connector.state); 114 } 115 116 static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned int offset) 117 { 118 u32 value = readl(dsi->regs + (offset << 2)); 119 120 trace_dsi_readl(dsi->dev, offset, value); 121 122 return value; 123 } 124 125 static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value, 126 unsigned int offset) 127 { 128 trace_dsi_writel(dsi->dev, offset, value); 129 writel(value, dsi->regs + (offset << 2)); 130 } 131 132 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name } 133 134 static const struct debugfs_reg32 tegra_dsi_regs[] = { 135 DEBUGFS_REG32(DSI_INCR_SYNCPT), 136 DEBUGFS_REG32(DSI_INCR_SYNCPT_CONTROL), 137 DEBUGFS_REG32(DSI_INCR_SYNCPT_ERROR), 138 DEBUGFS_REG32(DSI_CTXSW), 139 DEBUGFS_REG32(DSI_RD_DATA), 140 DEBUGFS_REG32(DSI_WR_DATA), 141 DEBUGFS_REG32(DSI_POWER_CONTROL), 142 DEBUGFS_REG32(DSI_INT_ENABLE), 143 DEBUGFS_REG32(DSI_INT_STATUS), 144 DEBUGFS_REG32(DSI_INT_MASK), 145 DEBUGFS_REG32(DSI_HOST_CONTROL), 146 DEBUGFS_REG32(DSI_CONTROL), 147 DEBUGFS_REG32(DSI_SOL_DELAY), 148 DEBUGFS_REG32(DSI_MAX_THRESHOLD), 149 DEBUGFS_REG32(DSI_TRIGGER), 150 DEBUGFS_REG32(DSI_TX_CRC), 151 DEBUGFS_REG32(DSI_STATUS), 152 DEBUGFS_REG32(DSI_INIT_SEQ_CONTROL), 153 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_0), 154 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_1), 155 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_2), 156 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_3), 157 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_4), 158 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_5), 159 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_6), 160 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_7), 161 DEBUGFS_REG32(DSI_PKT_SEQ_0_LO), 162 DEBUGFS_REG32(DSI_PKT_SEQ_0_HI), 163 DEBUGFS_REG32(DSI_PKT_SEQ_1_LO), 164 DEBUGFS_REG32(DSI_PKT_SEQ_1_HI), 165 DEBUGFS_REG32(DSI_PKT_SEQ_2_LO), 166 DEBUGFS_REG32(DSI_PKT_SEQ_2_HI), 167 DEBUGFS_REG32(DSI_PKT_SEQ_3_LO), 168 DEBUGFS_REG32(DSI_PKT_SEQ_3_HI), 169 DEBUGFS_REG32(DSI_PKT_SEQ_4_LO), 170 DEBUGFS_REG32(DSI_PKT_SEQ_4_HI), 171 DEBUGFS_REG32(DSI_PKT_SEQ_5_LO), 172 DEBUGFS_REG32(DSI_PKT_SEQ_5_HI), 173 DEBUGFS_REG32(DSI_DCS_CMDS), 174 DEBUGFS_REG32(DSI_PKT_LEN_0_1), 175 DEBUGFS_REG32(DSI_PKT_LEN_2_3), 176 DEBUGFS_REG32(DSI_PKT_LEN_4_5), 177 DEBUGFS_REG32(DSI_PKT_LEN_6_7), 178 DEBUGFS_REG32(DSI_PHY_TIMING_0), 179 DEBUGFS_REG32(DSI_PHY_TIMING_1), 180 DEBUGFS_REG32(DSI_PHY_TIMING_2), 181 DEBUGFS_REG32(DSI_BTA_TIMING), 182 DEBUGFS_REG32(DSI_TIMEOUT_0), 183 DEBUGFS_REG32(DSI_TIMEOUT_1), 184 DEBUGFS_REG32(DSI_TO_TALLY), 185 DEBUGFS_REG32(DSI_PAD_CONTROL_0), 186 DEBUGFS_REG32(DSI_PAD_CONTROL_CD), 187 DEBUGFS_REG32(DSI_PAD_CD_STATUS), 188 DEBUGFS_REG32(DSI_VIDEO_MODE_CONTROL), 189 DEBUGFS_REG32(DSI_PAD_CONTROL_1), 190 DEBUGFS_REG32(DSI_PAD_CONTROL_2), 191 DEBUGFS_REG32(DSI_PAD_CONTROL_3), 192 DEBUGFS_REG32(DSI_PAD_CONTROL_4), 193 DEBUGFS_REG32(DSI_GANGED_MODE_CONTROL), 194 DEBUGFS_REG32(DSI_GANGED_MODE_START), 195 DEBUGFS_REG32(DSI_GANGED_MODE_SIZE), 196 DEBUGFS_REG32(DSI_RAW_DATA_BYTE_COUNT), 197 DEBUGFS_REG32(DSI_ULTRA_LOW_POWER_CONTROL), 198 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_8), 199 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_9), 200 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_10), 201 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_11), 202 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_12), 203 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_13), 204 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_14), 205 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_15), 206 }; 207 208 static int tegra_dsi_show_regs(struct seq_file *s, void *data) 209 { 210 struct drm_info_node *node = s->private; 211 struct tegra_dsi *dsi = node->info_ent->data; 212 struct drm_crtc *crtc = dsi->output.encoder.crtc; 213 struct drm_device *drm = node->minor->dev; 214 unsigned int i; 215 int err = 0; 216 217 drm_modeset_lock_all(drm); 218 219 if (!crtc || !crtc->state->active) { 220 err = -EBUSY; 221 goto unlock; 222 } 223 224 for (i = 0; i < ARRAY_SIZE(tegra_dsi_regs); i++) { 225 unsigned int offset = tegra_dsi_regs[i].offset; 226 227 seq_printf(s, "%-32s %#05x %08x\n", tegra_dsi_regs[i].name, 228 offset, tegra_dsi_readl(dsi, offset)); 229 } 230 231 unlock: 232 drm_modeset_unlock_all(drm); 233 return err; 234 } 235 236 static struct drm_info_list debugfs_files[] = { 237 { "regs", tegra_dsi_show_regs, 0, NULL }, 238 }; 239 240 static int tegra_dsi_late_register(struct drm_connector *connector) 241 { 242 struct tegra_output *output = connector_to_output(connector); 243 unsigned int i, count = ARRAY_SIZE(debugfs_files); 244 struct drm_minor *minor = connector->dev->primary; 245 struct dentry *root = connector->debugfs_entry; 246 struct tegra_dsi *dsi = to_dsi(output); 247 248 dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), 249 GFP_KERNEL); 250 if (!dsi->debugfs_files) 251 return -ENOMEM; 252 253 for (i = 0; i < count; i++) 254 dsi->debugfs_files[i].data = dsi; 255 256 drm_debugfs_create_files(dsi->debugfs_files, count, root, minor); 257 258 return 0; 259 } 260 261 static void tegra_dsi_early_unregister(struct drm_connector *connector) 262 { 263 struct tegra_output *output = connector_to_output(connector); 264 unsigned int count = ARRAY_SIZE(debugfs_files); 265 struct tegra_dsi *dsi = to_dsi(output); 266 267 drm_debugfs_remove_files(dsi->debugfs_files, count, 268 connector->debugfs_entry, 269 connector->dev->primary); 270 kfree(dsi->debugfs_files); 271 dsi->debugfs_files = NULL; 272 } 273 274 #define PKT_ID0(id) ((((id) & 0x3f) << 3) | (1 << 9)) 275 #define PKT_LEN0(len) (((len) & 0x07) << 0) 276 #define PKT_ID1(id) ((((id) & 0x3f) << 13) | (1 << 19)) 277 #define PKT_LEN1(len) (((len) & 0x07) << 10) 278 #define PKT_ID2(id) ((((id) & 0x3f) << 23) | (1 << 29)) 279 #define PKT_LEN2(len) (((len) & 0x07) << 20) 280 281 #define PKT_LP (1 << 30) 282 #define NUM_PKT_SEQ 12 283 284 /* 285 * non-burst mode with sync pulses 286 */ 287 static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = { 288 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) | 289 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 290 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | 291 PKT_LP, 292 [ 1] = 0, 293 [ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) | 294 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 295 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | 296 PKT_LP, 297 [ 3] = 0, 298 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 299 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 300 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | 301 PKT_LP, 302 [ 5] = 0, 303 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 304 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 305 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0), 306 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) | 307 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) | 308 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4), 309 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 310 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 311 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | 312 PKT_LP, 313 [ 9] = 0, 314 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 315 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 316 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0), 317 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) | 318 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) | 319 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4), 320 }; 321 322 /* 323 * non-burst mode with sync events 324 */ 325 static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = { 326 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) | 327 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | 328 PKT_LP, 329 [ 1] = 0, 330 [ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 331 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | 332 PKT_LP, 333 [ 3] = 0, 334 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 335 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | 336 PKT_LP, 337 [ 5] = 0, 338 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 339 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) | 340 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3), 341 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4), 342 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 343 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | 344 PKT_LP, 345 [ 9] = 0, 346 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 347 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) | 348 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3), 349 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4), 350 }; 351 352 static const u32 pkt_seq_command_mode[NUM_PKT_SEQ] = { 353 [ 0] = 0, 354 [ 1] = 0, 355 [ 2] = 0, 356 [ 3] = 0, 357 [ 4] = 0, 358 [ 5] = 0, 359 [ 6] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(3) | PKT_LP, 360 [ 7] = 0, 361 [ 8] = 0, 362 [ 9] = 0, 363 [10] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(5) | PKT_LP, 364 [11] = 0, 365 }; 366 367 static void tegra_dsi_set_phy_timing(struct tegra_dsi *dsi, 368 unsigned long period, 369 const struct mipi_dphy_timing *timing) 370 { 371 u32 value; 372 373 value = DSI_TIMING_FIELD(timing->hsexit, period, 1) << 24 | 374 DSI_TIMING_FIELD(timing->hstrail, period, 0) << 16 | 375 DSI_TIMING_FIELD(timing->hszero, period, 3) << 8 | 376 DSI_TIMING_FIELD(timing->hsprepare, period, 1); 377 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0); 378 379 value = DSI_TIMING_FIELD(timing->clktrail, period, 1) << 24 | 380 DSI_TIMING_FIELD(timing->clkpost, period, 1) << 16 | 381 DSI_TIMING_FIELD(timing->clkzero, period, 1) << 8 | 382 DSI_TIMING_FIELD(timing->lpx, period, 1); 383 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1); 384 385 value = DSI_TIMING_FIELD(timing->clkprepare, period, 1) << 16 | 386 DSI_TIMING_FIELD(timing->clkpre, period, 1) << 8 | 387 DSI_TIMING_FIELD(0xff * period, period, 0) << 0; 388 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2); 389 390 value = DSI_TIMING_FIELD(timing->taget, period, 1) << 16 | 391 DSI_TIMING_FIELD(timing->tasure, period, 1) << 8 | 392 DSI_TIMING_FIELD(timing->tago, period, 1); 393 tegra_dsi_writel(dsi, value, DSI_BTA_TIMING); 394 395 if (dsi->slave) 396 tegra_dsi_set_phy_timing(dsi->slave, period, timing); 397 } 398 399 static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format, 400 unsigned int *mulp, unsigned int *divp) 401 { 402 switch (format) { 403 case MIPI_DSI_FMT_RGB666_PACKED: 404 case MIPI_DSI_FMT_RGB888: 405 *mulp = 3; 406 *divp = 1; 407 break; 408 409 case MIPI_DSI_FMT_RGB565: 410 *mulp = 2; 411 *divp = 1; 412 break; 413 414 case MIPI_DSI_FMT_RGB666: 415 *mulp = 9; 416 *divp = 4; 417 break; 418 419 default: 420 return -EINVAL; 421 } 422 423 return 0; 424 } 425 426 static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format, 427 enum tegra_dsi_format *fmt) 428 { 429 switch (format) { 430 case MIPI_DSI_FMT_RGB888: 431 *fmt = TEGRA_DSI_FORMAT_24P; 432 break; 433 434 case MIPI_DSI_FMT_RGB666: 435 *fmt = TEGRA_DSI_FORMAT_18NP; 436 break; 437 438 case MIPI_DSI_FMT_RGB666_PACKED: 439 *fmt = TEGRA_DSI_FORMAT_18P; 440 break; 441 442 case MIPI_DSI_FMT_RGB565: 443 *fmt = TEGRA_DSI_FORMAT_16P; 444 break; 445 446 default: 447 return -EINVAL; 448 } 449 450 return 0; 451 } 452 453 static void tegra_dsi_ganged_enable(struct tegra_dsi *dsi, unsigned int start, 454 unsigned int size) 455 { 456 u32 value; 457 458 tegra_dsi_writel(dsi, start, DSI_GANGED_MODE_START); 459 tegra_dsi_writel(dsi, size << 16 | size, DSI_GANGED_MODE_SIZE); 460 461 value = DSI_GANGED_MODE_CONTROL_ENABLE; 462 tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL); 463 } 464 465 static void tegra_dsi_enable(struct tegra_dsi *dsi) 466 { 467 u32 value; 468 469 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 470 value |= DSI_POWER_CONTROL_ENABLE; 471 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); 472 473 if (dsi->slave) 474 tegra_dsi_enable(dsi->slave); 475 } 476 477 static unsigned int tegra_dsi_get_lanes(struct tegra_dsi *dsi) 478 { 479 if (dsi->master) 480 return dsi->master->lanes + dsi->lanes; 481 482 if (dsi->slave) 483 return dsi->lanes + dsi->slave->lanes; 484 485 return dsi->lanes; 486 } 487 488 static void tegra_dsi_configure(struct tegra_dsi *dsi, unsigned int pipe, 489 const struct drm_display_mode *mode) 490 { 491 unsigned int hact, hsw, hbp, hfp, i, mul, div; 492 struct tegra_dsi_state *state; 493 const u32 *pkt_seq; 494 u32 value; 495 496 /* XXX: pass in state into this function? */ 497 if (dsi->master) 498 state = tegra_dsi_get_state(dsi->master); 499 else 500 state = tegra_dsi_get_state(dsi); 501 502 mul = state->mul; 503 div = state->div; 504 505 if (dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { 506 DRM_DEBUG_KMS("Non-burst video mode with sync pulses\n"); 507 pkt_seq = pkt_seq_video_non_burst_sync_pulses; 508 } else if (dsi->flags & MIPI_DSI_MODE_VIDEO) { 509 DRM_DEBUG_KMS("Non-burst video mode with sync events\n"); 510 pkt_seq = pkt_seq_video_non_burst_sync_events; 511 } else { 512 DRM_DEBUG_KMS("Command mode\n"); 513 pkt_seq = pkt_seq_command_mode; 514 } 515 516 value = DSI_CONTROL_CHANNEL(0) | 517 DSI_CONTROL_FORMAT(state->format) | 518 DSI_CONTROL_LANES(dsi->lanes - 1) | 519 DSI_CONTROL_SOURCE(pipe); 520 tegra_dsi_writel(dsi, value, DSI_CONTROL); 521 522 tegra_dsi_writel(dsi, dsi->video_fifo_depth, DSI_MAX_THRESHOLD); 523 524 value = DSI_HOST_CONTROL_HS; 525 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); 526 527 value = tegra_dsi_readl(dsi, DSI_CONTROL); 528 529 if (dsi->flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) 530 value |= DSI_CONTROL_HS_CLK_CTRL; 531 532 value &= ~DSI_CONTROL_TX_TRIG(3); 533 534 /* enable DCS commands for command mode */ 535 if (dsi->flags & MIPI_DSI_MODE_VIDEO) 536 value &= ~DSI_CONTROL_DCS_ENABLE; 537 else 538 value |= DSI_CONTROL_DCS_ENABLE; 539 540 value |= DSI_CONTROL_VIDEO_ENABLE; 541 value &= ~DSI_CONTROL_HOST_ENABLE; 542 tegra_dsi_writel(dsi, value, DSI_CONTROL); 543 544 for (i = 0; i < NUM_PKT_SEQ; i++) 545 tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i); 546 547 if (dsi->flags & MIPI_DSI_MODE_VIDEO) { 548 /* horizontal active pixels */ 549 hact = mode->hdisplay * mul / div; 550 551 /* horizontal sync width */ 552 hsw = (mode->hsync_end - mode->hsync_start) * mul / div; 553 554 /* horizontal back porch */ 555 hbp = (mode->htotal - mode->hsync_end) * mul / div; 556 557 /* horizontal front porch */ 558 hfp = (mode->hsync_start - mode->hdisplay) * mul / div; 559 560 if (dsi->master || dsi->slave) { 561 hact /= 2; 562 hsw /= 2; 563 hbp /= 2; 564 hfp /= 2; 565 } 566 567 if ((dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) == 0) 568 hbp += hsw; 569 570 /* subtract packet overhead */ 571 hsw -= 10; 572 hbp -= 14; 573 hfp -= 8; 574 575 tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1); 576 tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3); 577 tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5); 578 tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7); 579 } else { 580 u16 bytes; 581 582 if (dsi->master || dsi->slave) { 583 /* 584 * For ganged mode, assume symmetric left-right mode. 585 */ 586 bytes = 1 + (mode->hdisplay / 2) * mul / div; 587 } else { 588 /* 1 byte (DCS command) + pixel data */ 589 bytes = 1 + mode->hdisplay * mul / div; 590 } 591 592 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1); 593 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_2_3); 594 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_4_5); 595 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_6_7); 596 597 value = MIPI_DCS_WRITE_MEMORY_START << 8 | 598 MIPI_DCS_WRITE_MEMORY_CONTINUE; 599 tegra_dsi_writel(dsi, value, DSI_DCS_CMDS); 600 } 601 602 /* set SOL delay */ 603 if (dsi->master || dsi->slave) { 604 unsigned long delay, bclk, bclk_ganged; 605 unsigned int lanes = state->lanes; 606 607 /* SOL to valid, valid to FIFO and FIFO write delay */ 608 delay = 4 + 4 + 2; 609 delay = DIV_ROUND_UP(delay * mul, div * lanes); 610 /* FIFO read delay */ 611 delay = delay + 6; 612 613 bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes); 614 bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes); 615 value = bclk - bclk_ganged + delay + 20; 616 } else { 617 value = 8 * mul / div; 618 } 619 620 tegra_dsi_writel(dsi, value, DSI_SOL_DELAY); 621 622 if (dsi->slave) { 623 tegra_dsi_configure(dsi->slave, pipe, mode); 624 625 /* 626 * TODO: Support modes other than symmetrical left-right 627 * split. 628 */ 629 tegra_dsi_ganged_enable(dsi, 0, mode->hdisplay / 2); 630 tegra_dsi_ganged_enable(dsi->slave, mode->hdisplay / 2, 631 mode->hdisplay / 2); 632 } 633 } 634 635 static int tegra_dsi_wait_idle(struct tegra_dsi *dsi, unsigned long timeout) 636 { 637 u32 value; 638 639 timeout = jiffies + msecs_to_jiffies(timeout); 640 641 while (time_before(jiffies, timeout)) { 642 value = tegra_dsi_readl(dsi, DSI_STATUS); 643 if (value & DSI_STATUS_IDLE) 644 return 0; 645 646 usleep_range(1000, 2000); 647 } 648 649 return -ETIMEDOUT; 650 } 651 652 static void tegra_dsi_video_disable(struct tegra_dsi *dsi) 653 { 654 u32 value; 655 656 value = tegra_dsi_readl(dsi, DSI_CONTROL); 657 value &= ~DSI_CONTROL_VIDEO_ENABLE; 658 tegra_dsi_writel(dsi, value, DSI_CONTROL); 659 660 if (dsi->slave) 661 tegra_dsi_video_disable(dsi->slave); 662 } 663 664 static void tegra_dsi_ganged_disable(struct tegra_dsi *dsi) 665 { 666 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_START); 667 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_SIZE); 668 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_CONTROL); 669 } 670 671 static int tegra_dsi_pad_enable(struct tegra_dsi *dsi) 672 { 673 u32 value; 674 675 if (dsi->config->has_multiple_pad_controls) { 676 /* 677 * XXX Is this still needed? The module reset is deasserted right 678 * before this function is called. 679 */ 680 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0); 681 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1); 682 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2); 683 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3); 684 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4); 685 686 value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0); 687 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0); 688 689 value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) | 690 DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) | 691 DSI_PAD_OUT_CLK(0x0); 692 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2); 693 694 value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | 695 DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3); 696 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3); 697 } else { 698 value = DSI_PAD_CONTROL_LPUPADJ(0x1) | DSI_PAD_CONTROL_LPDNADJ(0x1) | 699 DSI_PAD_CONTROL_PREEMP_EN(0x1) | DSI_PAD_CONTROL_SLEWDNADJ(0x6) | 700 DSI_PAD_CONTROL_SLEWUPADJ(0x6) | DSI_PAD_CONTROL_PDIO(0) | 701 DSI_PAD_CONTROL_PDIO_CLK(0) | DSI_PAD_CONTROL_PULLDN_ENAB(0); 702 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0); 703 } 704 705 return 0; 706 } 707 708 static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi) 709 { 710 int err; 711 712 /* start calibration */ 713 tegra_dsi_pad_enable(dsi); 714 715 err = tegra_mipi_start_calibration(dsi->mipi); 716 if (err < 0) 717 return err; 718 719 return tegra_mipi_finish_calibration(dsi->mipi); 720 } 721 722 static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk, 723 unsigned int vrefresh) 724 { 725 unsigned int timeout; 726 u32 value; 727 728 /* one frame high-speed transmission timeout */ 729 timeout = (bclk / vrefresh) / 512; 730 value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout); 731 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0); 732 733 /* 2 ms peripheral timeout for panel */ 734 timeout = 2 * bclk / 512 * 1000; 735 value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000); 736 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1); 737 738 value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0); 739 tegra_dsi_writel(dsi, value, DSI_TO_TALLY); 740 741 if (dsi->slave) 742 tegra_dsi_set_timeout(dsi->slave, bclk, vrefresh); 743 } 744 745 static void tegra_dsi_disable(struct tegra_dsi *dsi) 746 { 747 u32 value; 748 749 if (dsi->slave) { 750 tegra_dsi_ganged_disable(dsi->slave); 751 tegra_dsi_ganged_disable(dsi); 752 } 753 754 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 755 value &= ~DSI_POWER_CONTROL_ENABLE; 756 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); 757 758 if (dsi->slave) 759 tegra_dsi_disable(dsi->slave); 760 761 usleep_range(5000, 10000); 762 } 763 764 static void tegra_dsi_soft_reset(struct tegra_dsi *dsi) 765 { 766 u32 value; 767 768 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 769 value &= ~DSI_POWER_CONTROL_ENABLE; 770 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); 771 772 usleep_range(300, 1000); 773 774 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 775 value |= DSI_POWER_CONTROL_ENABLE; 776 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); 777 778 usleep_range(300, 1000); 779 780 value = tegra_dsi_readl(dsi, DSI_TRIGGER); 781 if (value) 782 tegra_dsi_writel(dsi, 0, DSI_TRIGGER); 783 784 if (dsi->slave) 785 tegra_dsi_soft_reset(dsi->slave); 786 } 787 788 static void tegra_dsi_connector_reset(struct drm_connector *connector) 789 { 790 struct tegra_dsi_state *state = kzalloc_obj(*state); 791 792 if (!state) 793 return; 794 795 if (connector->state) { 796 __drm_atomic_helper_connector_destroy_state(connector->state); 797 kfree(connector->state); 798 } 799 800 __drm_atomic_helper_connector_reset(connector, &state->base); 801 } 802 803 static struct drm_connector_state * 804 tegra_dsi_connector_duplicate_state(struct drm_connector *connector) 805 { 806 struct tegra_dsi_state *state = to_dsi_state(connector->state); 807 struct tegra_dsi_state *copy; 808 809 copy = kmemdup(state, sizeof(*state), GFP_KERNEL); 810 if (!copy) 811 return NULL; 812 813 __drm_atomic_helper_connector_duplicate_state(connector, 814 ©->base); 815 816 return ©->base; 817 } 818 819 static const struct drm_connector_funcs tegra_dsi_connector_funcs = { 820 .reset = tegra_dsi_connector_reset, 821 .detect = tegra_output_connector_detect, 822 .fill_modes = drm_helper_probe_single_connector_modes, 823 .destroy = tegra_output_connector_destroy, 824 .atomic_duplicate_state = tegra_dsi_connector_duplicate_state, 825 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 826 .late_register = tegra_dsi_late_register, 827 .early_unregister = tegra_dsi_early_unregister, 828 }; 829 830 static enum drm_mode_status 831 tegra_dsi_connector_mode_valid(struct drm_connector *connector, 832 const struct drm_display_mode *mode) 833 { 834 return MODE_OK; 835 } 836 837 static const struct drm_connector_helper_funcs tegra_dsi_connector_helper_funcs = { 838 .get_modes = tegra_output_connector_get_modes, 839 .mode_valid = tegra_dsi_connector_mode_valid, 840 }; 841 842 static void tegra_dsi_unprepare(struct tegra_dsi *dsi) 843 { 844 int err; 845 846 if (dsi->slave) 847 tegra_dsi_unprepare(dsi->slave); 848 849 err = tegra_mipi_disable(dsi->mipi); 850 if (err < 0) 851 dev_err(dsi->dev, "failed to disable MIPI calibration: %d\n", 852 err); 853 854 err = host1x_client_suspend(&dsi->client); 855 if (err < 0) 856 dev_err(dsi->dev, "failed to suspend: %d\n", err); 857 } 858 859 static void tegra_dsi_encoder_disable(struct drm_encoder *encoder) 860 { 861 struct tegra_output *output = encoder_to_output(encoder); 862 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 863 struct tegra_dsi *dsi = to_dsi(output); 864 u32 value; 865 int err; 866 867 if (output->panel) 868 drm_panel_disable(output->panel); 869 870 tegra_dsi_video_disable(dsi); 871 872 /* 873 * The following accesses registers of the display controller, so make 874 * sure it's only executed when the output is attached to one. 875 */ 876 if (dc) { 877 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 878 value &= ~DSI_ENABLE; 879 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 880 881 tegra_dc_commit(dc); 882 } 883 884 err = tegra_dsi_wait_idle(dsi, 100); 885 if (err < 0) 886 dev_dbg(dsi->dev, "failed to idle DSI: %d\n", err); 887 888 tegra_dsi_soft_reset(dsi); 889 890 if (output->panel) 891 drm_panel_unprepare(output->panel); 892 893 tegra_dsi_disable(dsi); 894 895 tegra_dsi_unprepare(dsi); 896 } 897 898 static int tegra_dsi_prepare(struct tegra_dsi *dsi) 899 { 900 int err; 901 902 err = host1x_client_resume(&dsi->client); 903 if (err < 0) { 904 dev_err(dsi->dev, "failed to resume: %d\n", err); 905 return err; 906 } 907 908 err = tegra_mipi_enable(dsi->mipi); 909 if (err < 0) 910 dev_err(dsi->dev, "failed to enable MIPI calibration: %d\n", 911 err); 912 913 err = tegra_dsi_pad_calibrate(dsi); 914 if (err < 0) 915 dev_err(dsi->dev, "MIPI calibration failed: %d\n", err); 916 917 if (dsi->slave) 918 tegra_dsi_prepare(dsi->slave); 919 920 return 0; 921 } 922 923 static void tegra_dsi_encoder_enable(struct drm_encoder *encoder) 924 { 925 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 926 struct tegra_output *output = encoder_to_output(encoder); 927 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 928 struct tegra_dsi *dsi = to_dsi(output); 929 struct tegra_dsi_state *state; 930 u32 value; 931 int err; 932 933 err = tegra_dsi_prepare(dsi); 934 if (err < 0) { 935 dev_err(dsi->dev, "failed to prepare: %d\n", err); 936 return; 937 } 938 939 /* If the bootloader enabled DSI it needs to be disabled 940 * in order for the panel initialization commands to be 941 * properly sent. 942 */ 943 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 944 945 if (value & DSI_POWER_CONTROL_ENABLE) 946 tegra_dsi_disable(dsi); 947 948 state = tegra_dsi_get_state(dsi); 949 950 tegra_dsi_set_timeout(dsi, state->bclk, state->vrefresh); 951 952 /* 953 * The D-PHY timing fields are expressed in byte-clock cycles, so 954 * multiply the period by 8. 955 */ 956 tegra_dsi_set_phy_timing(dsi, state->period * 8, &state->timing); 957 958 if (output->panel) 959 drm_panel_prepare(output->panel); 960 961 tegra_dsi_configure(dsi, dc->pipe, mode); 962 963 /* enable display controller */ 964 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 965 value |= DSI_ENABLE; 966 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 967 968 tegra_dc_commit(dc); 969 970 /* enable DSI controller */ 971 tegra_dsi_enable(dsi); 972 973 if (output->panel) 974 drm_panel_enable(output->panel); 975 } 976 977 static int 978 tegra_dsi_encoder_atomic_check(struct drm_encoder *encoder, 979 struct drm_crtc_state *crtc_state, 980 struct drm_connector_state *conn_state) 981 { 982 struct tegra_output *output = encoder_to_output(encoder); 983 struct tegra_dsi_state *state = to_dsi_state(conn_state); 984 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc); 985 struct tegra_dsi *dsi = to_dsi(output); 986 unsigned int scdiv; 987 unsigned long plld; 988 int err; 989 990 state->pclk = crtc_state->mode.clock * 1000; 991 992 err = tegra_dsi_get_muldiv(dsi->format, &state->mul, &state->div); 993 if (err < 0) 994 return err; 995 996 state->lanes = tegra_dsi_get_lanes(dsi); 997 998 err = tegra_dsi_get_format(dsi->format, &state->format); 999 if (err < 0) 1000 return err; 1001 1002 state->vrefresh = drm_mode_vrefresh(&crtc_state->mode); 1003 1004 /* compute byte clock */ 1005 state->bclk = (state->pclk * state->mul) / (state->div * state->lanes); 1006 1007 DRM_DEBUG_KMS("mul: %u, div: %u, lanes: %u\n", state->mul, state->div, 1008 state->lanes); 1009 DRM_DEBUG_KMS("format: %u, vrefresh: %u\n", state->format, 1010 state->vrefresh); 1011 DRM_DEBUG_KMS("bclk: %lu\n", state->bclk); 1012 1013 /* 1014 * Compute bit clock and round up to the next MHz. 1015 */ 1016 plld = DIV_ROUND_UP(state->bclk * 8, USEC_PER_SEC) * USEC_PER_SEC; 1017 state->period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, plld); 1018 1019 err = mipi_dphy_timing_get_default(&state->timing, state->period); 1020 if (err < 0) 1021 return err; 1022 1023 err = mipi_dphy_timing_validate(&state->timing, state->period); 1024 if (err < 0) { 1025 dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err); 1026 return err; 1027 } 1028 1029 /* 1030 * We divide the frequency by two here, but we make up for that by 1031 * setting the shift clock divider (further below) to half of the 1032 * correct value. 1033 */ 1034 plld /= 2; 1035 1036 /* 1037 * Derive pixel clock from bit clock using the shift clock divider. 1038 * Note that this is only half of what we would expect, but we need 1039 * that to make up for the fact that we divided the bit clock by a 1040 * factor of two above. 1041 * 1042 * It's not clear exactly why this is necessary, but the display is 1043 * not working properly otherwise. Perhaps the PLLs cannot generate 1044 * frequencies sufficiently high. 1045 */ 1046 scdiv = ((8 * state->mul) / (state->div * state->lanes)) - 2; 1047 1048 err = tegra_dc_state_setup_clock(dc, crtc_state, dsi->clk_parent, 1049 plld, scdiv); 1050 if (err < 0) { 1051 dev_err(output->dev, "failed to setup CRTC state: %d\n", err); 1052 return err; 1053 } 1054 1055 return err; 1056 } 1057 1058 static const struct drm_encoder_funcs tegra_dsi_encoder_funcs = { 1059 .destroy = drm_encoder_cleanup, 1060 }; 1061 1062 static const struct drm_encoder_helper_funcs tegra_dsi_encoder_helper_funcs = { 1063 .disable = tegra_dsi_encoder_disable, 1064 .enable = tegra_dsi_encoder_enable, 1065 .atomic_check = tegra_dsi_encoder_atomic_check, 1066 }; 1067 1068 static int tegra_dsi_init(struct host1x_client *client) 1069 { 1070 struct drm_device *drm = dev_get_drvdata(client->host); 1071 struct tegra_dsi *dsi = host1x_client_to_dsi(client); 1072 int err; 1073 1074 /* Gangsters must not register their own outputs. */ 1075 if (!dsi->master) { 1076 dsi->output.dev = client->dev; 1077 1078 drm_connector_init(drm, &dsi->output.connector, 1079 &tegra_dsi_connector_funcs, 1080 DRM_MODE_CONNECTOR_DSI); 1081 drm_connector_helper_add(&dsi->output.connector, 1082 &tegra_dsi_connector_helper_funcs); 1083 dsi->output.connector.dpms = DRM_MODE_DPMS_OFF; 1084 1085 err = drm_encoder_init(drm, &dsi->output.encoder, 1086 &tegra_dsi_encoder_funcs, 1087 DRM_MODE_ENCODER_DSI, NULL); 1088 if (err) { 1089 drm_err(drm, "failed to initialize encoder: %d\n", err); 1090 return err; 1091 } 1092 1093 drm_encoder_helper_add(&dsi->output.encoder, 1094 &tegra_dsi_encoder_helper_funcs); 1095 1096 drm_connector_attach_encoder(&dsi->output.connector, 1097 &dsi->output.encoder); 1098 drm_connector_register(&dsi->output.connector); 1099 1100 err = tegra_output_init(drm, &dsi->output); 1101 if (err < 0) 1102 dev_err(dsi->dev, "failed to initialize output: %d\n", 1103 err); 1104 1105 dsi->output.encoder.possible_crtcs = 0x3; 1106 } 1107 1108 return 0; 1109 } 1110 1111 static int tegra_dsi_exit(struct host1x_client *client) 1112 { 1113 struct tegra_dsi *dsi = host1x_client_to_dsi(client); 1114 1115 tegra_output_exit(&dsi->output); 1116 1117 return 0; 1118 } 1119 1120 static int tegra_dsi_runtime_suspend(struct host1x_client *client) 1121 { 1122 struct tegra_dsi *dsi = host1x_client_to_dsi(client); 1123 struct device *dev = client->dev; 1124 int err; 1125 1126 if (dsi->rst) { 1127 err = reset_control_assert(dsi->rst); 1128 if (err < 0) { 1129 dev_err(dev, "failed to assert reset: %d\n", err); 1130 return err; 1131 } 1132 } 1133 1134 usleep_range(1000, 2000); 1135 1136 clk_disable_unprepare(dsi->clk_lp); 1137 clk_disable_unprepare(dsi->clk); 1138 1139 regulator_disable(dsi->vdd); 1140 pm_runtime_put_sync(dev); 1141 1142 return 0; 1143 } 1144 1145 static int tegra_dsi_runtime_resume(struct host1x_client *client) 1146 { 1147 struct tegra_dsi *dsi = host1x_client_to_dsi(client); 1148 struct device *dev = client->dev; 1149 int err; 1150 1151 err = pm_runtime_resume_and_get(dev); 1152 if (err < 0) { 1153 dev_err(dev, "failed to get runtime PM: %d\n", err); 1154 return err; 1155 } 1156 1157 err = regulator_enable(dsi->vdd); 1158 if (err < 0) { 1159 dev_err(dev, "failed to enable VDD supply: %d\n", err); 1160 goto put_rpm; 1161 } 1162 1163 err = clk_prepare_enable(dsi->clk); 1164 if (err < 0) { 1165 dev_err(dev, "cannot enable DSI clock: %d\n", err); 1166 goto disable_vdd; 1167 } 1168 1169 err = clk_prepare_enable(dsi->clk_lp); 1170 if (err < 0) { 1171 dev_err(dev, "cannot enable low-power clock: %d\n", err); 1172 goto disable_clk; 1173 } 1174 1175 usleep_range(1000, 2000); 1176 1177 if (dsi->rst) { 1178 err = reset_control_deassert(dsi->rst); 1179 if (err < 0) { 1180 dev_err(dev, "cannot assert reset: %d\n", err); 1181 goto disable_clk_lp; 1182 } 1183 } 1184 1185 return 0; 1186 1187 disable_clk_lp: 1188 clk_disable_unprepare(dsi->clk_lp); 1189 disable_clk: 1190 clk_disable_unprepare(dsi->clk); 1191 disable_vdd: 1192 regulator_disable(dsi->vdd); 1193 put_rpm: 1194 pm_runtime_put_sync(dev); 1195 return err; 1196 } 1197 1198 static const struct host1x_client_ops dsi_client_ops = { 1199 .init = tegra_dsi_init, 1200 .exit = tegra_dsi_exit, 1201 .suspend = tegra_dsi_runtime_suspend, 1202 .resume = tegra_dsi_runtime_resume, 1203 }; 1204 1205 static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi) 1206 { 1207 struct clk *parent; 1208 int err; 1209 1210 /* 1211 * Tegra124+ uses a clock gate, not a mux, so this step 1212 * should be redundant for configuration; yet, DSI refuses 1213 * to work without it. 1214 */ 1215 1216 parent = clk_get_parent(dsi->clk); 1217 if (!parent) 1218 return -EINVAL; 1219 1220 err = clk_set_parent(parent, dsi->clk_parent); 1221 if (err < 0) 1222 return err; 1223 1224 return 0; 1225 } 1226 1227 static const char * const error_report[16] = { 1228 "SoT Error", 1229 "SoT Sync Error", 1230 "EoT Sync Error", 1231 "Escape Mode Entry Command Error", 1232 "Low-Power Transmit Sync Error", 1233 "Peripheral Timeout Error", 1234 "False Control Error", 1235 "Contention Detected", 1236 "ECC Error, single-bit", 1237 "ECC Error, multi-bit", 1238 "Checksum Error", 1239 "DSI Data Type Not Recognized", 1240 "DSI VC ID Invalid", 1241 "Invalid Transmission Length", 1242 "Reserved", 1243 "DSI Protocol Violation", 1244 }; 1245 1246 static ssize_t tegra_dsi_read_response(struct tegra_dsi *dsi, 1247 const struct mipi_dsi_msg *msg, 1248 size_t count) 1249 { 1250 u8 *rx = msg->rx_buf; 1251 unsigned int i, j, k; 1252 size_t size = 0; 1253 u16 errors; 1254 u32 value; 1255 1256 /* read and parse packet header */ 1257 value = tegra_dsi_readl(dsi, DSI_RD_DATA); 1258 1259 switch (value & 0x3f) { 1260 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 1261 errors = (value >> 8) & 0xffff; 1262 dev_dbg(dsi->dev, "Acknowledge and error report: %04x\n", 1263 errors); 1264 for (i = 0; i < ARRAY_SIZE(error_report); i++) 1265 if (errors & BIT(i)) 1266 dev_dbg(dsi->dev, " %2u: %s\n", i, 1267 error_report[i]); 1268 break; 1269 1270 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 1271 rx[0] = (value >> 8) & 0xff; 1272 size = 1; 1273 break; 1274 1275 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 1276 rx[0] = (value >> 8) & 0xff; 1277 rx[1] = (value >> 16) & 0xff; 1278 size = 2; 1279 break; 1280 1281 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE: 1282 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff); 1283 break; 1284 1285 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE: 1286 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff); 1287 break; 1288 1289 default: 1290 dev_err(dsi->dev, "unhandled response type: %02x\n", 1291 value & 0x3f); 1292 return -EPROTO; 1293 } 1294 1295 size = min(size, msg->rx_len); 1296 1297 if (msg->rx_buf && size > 0) { 1298 for (i = 0, j = 0; i < count - 1; i++, j += 4) { 1299 u8 *rx = msg->rx_buf + j; 1300 1301 value = tegra_dsi_readl(dsi, DSI_RD_DATA); 1302 1303 for (k = 0; k < 4 && (j + k) < msg->rx_len; k++) 1304 rx[j + k] = (value >> (k << 3)) & 0xff; 1305 } 1306 } 1307 1308 return size; 1309 } 1310 1311 static int tegra_dsi_transmit(struct tegra_dsi *dsi, unsigned long timeout) 1312 { 1313 tegra_dsi_writel(dsi, DSI_TRIGGER_HOST, DSI_TRIGGER); 1314 1315 timeout = jiffies + msecs_to_jiffies(timeout); 1316 1317 while (time_before(jiffies, timeout)) { 1318 u32 value = tegra_dsi_readl(dsi, DSI_TRIGGER); 1319 if ((value & DSI_TRIGGER_HOST) == 0) 1320 return 0; 1321 1322 usleep_range(1000, 2000); 1323 } 1324 1325 DRM_DEBUG_KMS("timeout waiting for transmission to complete\n"); 1326 return -ETIMEDOUT; 1327 } 1328 1329 static int tegra_dsi_wait_for_response(struct tegra_dsi *dsi, 1330 unsigned long timeout) 1331 { 1332 timeout = jiffies + msecs_to_jiffies(250); 1333 1334 while (time_before(jiffies, timeout)) { 1335 u32 value = tegra_dsi_readl(dsi, DSI_STATUS); 1336 u8 count = value & 0x1f; 1337 1338 if (count > 0) 1339 return count; 1340 1341 usleep_range(1000, 2000); 1342 } 1343 1344 DRM_DEBUG_KMS("peripheral returned no data\n"); 1345 return -ETIMEDOUT; 1346 } 1347 1348 static void tegra_dsi_writesl(struct tegra_dsi *dsi, unsigned long offset, 1349 const void *buffer, size_t size) 1350 { 1351 const u8 *buf = buffer; 1352 size_t i, j; 1353 u32 value; 1354 1355 for (j = 0; j < size; j += 4) { 1356 value = 0; 1357 1358 for (i = 0; i < 4 && j + i < size; i++) 1359 value |= buf[j + i] << (i << 3); 1360 1361 tegra_dsi_writel(dsi, value, DSI_WR_DATA); 1362 } 1363 } 1364 1365 static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host, 1366 const struct mipi_dsi_msg *msg) 1367 { 1368 struct tegra_dsi *dsi = host_to_tegra(host); 1369 struct mipi_dsi_packet packet; 1370 const u8 *header; 1371 size_t count; 1372 ssize_t err; 1373 u32 value; 1374 1375 err = mipi_dsi_create_packet(&packet, msg); 1376 if (err < 0) 1377 return err; 1378 1379 header = packet.header; 1380 1381 /* maximum FIFO depth is 1920 words */ 1382 if (packet.size > dsi->video_fifo_depth * 4) 1383 return -ENOSPC; 1384 1385 /* reset underflow/overflow flags */ 1386 value = tegra_dsi_readl(dsi, DSI_STATUS); 1387 if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) { 1388 value = DSI_HOST_CONTROL_FIFO_RESET; 1389 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); 1390 usleep_range(10, 20); 1391 } 1392 1393 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 1394 value |= DSI_POWER_CONTROL_ENABLE; 1395 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); 1396 1397 usleep_range(5000, 10000); 1398 1399 value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | 1400 DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC; 1401 1402 if ((msg->flags & MIPI_DSI_MSG_USE_LPM) == 0) 1403 value |= DSI_HOST_CONTROL_HS; 1404 1405 /* 1406 * The host FIFO has a maximum of 64 words, so larger transmissions 1407 * need to use the video FIFO. 1408 */ 1409 if (packet.size > dsi->host_fifo_depth * 4) 1410 value |= DSI_HOST_CONTROL_FIFO_SEL; 1411 1412 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); 1413 1414 /* 1415 * For reads and messages with explicitly requested ACK, generate a 1416 * BTA sequence after the transmission of the packet. 1417 */ 1418 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) || 1419 (msg->rx_buf && msg->rx_len > 0)) { 1420 value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL); 1421 value |= DSI_HOST_CONTROL_PKT_BTA; 1422 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); 1423 } 1424 1425 value = DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE; 1426 tegra_dsi_writel(dsi, value, DSI_CONTROL); 1427 1428 /* write packet header, ECC is generated by hardware */ 1429 value = header[2] << 16 | header[1] << 8 | header[0]; 1430 tegra_dsi_writel(dsi, value, DSI_WR_DATA); 1431 1432 /* write payload (if any) */ 1433 if (packet.payload_length > 0) 1434 tegra_dsi_writesl(dsi, DSI_WR_DATA, packet.payload, 1435 packet.payload_length); 1436 1437 err = tegra_dsi_transmit(dsi, 250); 1438 if (err < 0) 1439 return err; 1440 1441 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) || 1442 (msg->rx_buf && msg->rx_len > 0)) { 1443 err = tegra_dsi_wait_for_response(dsi, 250); 1444 if (err < 0) 1445 return err; 1446 1447 count = err; 1448 1449 value = tegra_dsi_readl(dsi, DSI_RD_DATA); 1450 switch (value) { 1451 case 0x84: 1452 /* 1453 dev_dbg(dsi->dev, "ACK\n"); 1454 */ 1455 break; 1456 1457 case 0x87: 1458 /* 1459 dev_dbg(dsi->dev, "ESCAPE\n"); 1460 */ 1461 break; 1462 1463 default: 1464 dev_err(dsi->dev, "unknown status: %08x\n", value); 1465 break; 1466 } 1467 1468 if (count > 1) { 1469 err = tegra_dsi_read_response(dsi, msg, count); 1470 if (err < 0) 1471 dev_err(dsi->dev, 1472 "failed to parse response: %zd\n", 1473 err); 1474 else { 1475 /* 1476 * For read commands, return the number of 1477 * bytes returned by the peripheral. 1478 */ 1479 count = err; 1480 } 1481 } 1482 } else { 1483 /* 1484 * For write commands, we have transmitted the 4-byte header 1485 * plus the variable-length payload. 1486 */ 1487 count = 4 + packet.payload_length; 1488 } 1489 1490 return count; 1491 } 1492 1493 static int tegra_dsi_ganged_setup(struct tegra_dsi *dsi) 1494 { 1495 struct clk *parent; 1496 int err; 1497 1498 /* make sure both DSI controllers share the same PLL */ 1499 parent = clk_get_parent(dsi->slave->clk); 1500 if (!parent) 1501 return -EINVAL; 1502 1503 err = clk_set_parent(parent, dsi->clk_parent); 1504 if (err < 0) 1505 return err; 1506 1507 return 0; 1508 } 1509 1510 static int tegra_dsi_host_attach(struct mipi_dsi_host *host, 1511 struct mipi_dsi_device *device) 1512 { 1513 struct tegra_dsi *dsi = host_to_tegra(host); 1514 1515 dsi->flags = device->mode_flags; 1516 dsi->format = device->format; 1517 dsi->lanes = device->lanes; 1518 1519 if (dsi->slave) { 1520 int err; 1521 1522 dev_dbg(dsi->dev, "attaching dual-channel device %s\n", 1523 dev_name(&device->dev)); 1524 1525 err = tegra_dsi_ganged_setup(dsi); 1526 if (err < 0) { 1527 dev_err(dsi->dev, "failed to set up ganged mode: %d\n", 1528 err); 1529 return err; 1530 } 1531 } 1532 1533 /* 1534 * Slaves don't have a panel associated with them, so they provide 1535 * merely the second channel. 1536 */ 1537 if (!dsi->master) { 1538 struct tegra_output *output = &dsi->output; 1539 1540 /* 1541 * tegra_output_probe() never populates a panel for DSI 1542 * outputs, so output->panel is always NULL here. 1543 */ 1544 output->panel = of_drm_find_panel(device->dev.of_node); 1545 if (IS_ERR(output->panel)) 1546 output->panel = NULL; 1547 1548 if (output->panel && output->connector.dev) 1549 drm_helper_hpd_irq_event(output->connector.dev); 1550 } 1551 1552 return 0; 1553 } 1554 1555 static int tegra_dsi_host_detach(struct mipi_dsi_host *host, 1556 struct mipi_dsi_device *device) 1557 { 1558 struct tegra_dsi *dsi = host_to_tegra(host); 1559 struct tegra_output *output = &dsi->output; 1560 1561 if (output->panel && &device->dev == output->panel->dev) { 1562 drm_panel_put(output->panel); 1563 output->panel = NULL; 1564 1565 if (output->connector.dev) 1566 drm_helper_hpd_irq_event(output->connector.dev); 1567 } 1568 1569 return 0; 1570 } 1571 1572 static const struct mipi_dsi_host_ops tegra_dsi_host_ops = { 1573 .attach = tegra_dsi_host_attach, 1574 .detach = tegra_dsi_host_detach, 1575 .transfer = tegra_dsi_host_transfer, 1576 }; 1577 1578 static int tegra_dsi_ganged_probe(struct tegra_dsi *dsi) 1579 { 1580 struct device_node *np; 1581 1582 np = of_parse_phandle(dsi->dev->of_node, "nvidia,ganged-mode", 0); 1583 if (np) { 1584 struct platform_device *gangster = of_find_device_by_node(np); 1585 of_node_put(np); 1586 if (!gangster) 1587 return -EPROBE_DEFER; 1588 1589 dsi->slave = platform_get_drvdata(gangster); 1590 put_device(&gangster->dev); 1591 if (!dsi->slave) 1592 return -EPROBE_DEFER; 1593 1594 dsi->slave->master = dsi; 1595 } 1596 1597 return 0; 1598 } 1599 1600 static int tegra_dsi_probe(struct platform_device *pdev) 1601 { 1602 struct tegra_dsi *dsi; 1603 int err; 1604 1605 dsi = devm_kzalloc_obj(&pdev->dev, *dsi); 1606 if (!dsi) 1607 return -ENOMEM; 1608 1609 dsi->config = device_get_match_data(&pdev->dev); 1610 if (!dsi->config) 1611 return -ENODEV; 1612 1613 dsi->output.dev = dsi->dev = &pdev->dev; 1614 dsi->video_fifo_depth = 1920; 1615 dsi->host_fifo_depth = 64; 1616 1617 err = tegra_dsi_ganged_probe(dsi); 1618 if (err < 0) 1619 return err; 1620 1621 err = tegra_output_probe(&dsi->output); 1622 if (err < 0) 1623 return err; 1624 1625 dsi->output.connector.polled = DRM_CONNECTOR_POLL_HPD; 1626 1627 /* 1628 * Assume these values by default. When a DSI peripheral driver 1629 * attaches to the DSI host, the parameters will be taken from 1630 * the attached device. 1631 */ 1632 dsi->flags = MIPI_DSI_MODE_VIDEO; 1633 dsi->format = MIPI_DSI_FMT_RGB888; 1634 dsi->lanes = 4; 1635 1636 if (!pdev->dev.pm_domain) { 1637 dsi->rst = devm_reset_control_get(&pdev->dev, "dsi"); 1638 if (IS_ERR(dsi->rst)) { 1639 err = PTR_ERR(dsi->rst); 1640 goto remove; 1641 } 1642 } 1643 1644 dsi->clk = devm_clk_get(&pdev->dev, NULL); 1645 if (IS_ERR(dsi->clk)) { 1646 err = dev_err_probe(&pdev->dev, PTR_ERR(dsi->clk), 1647 "cannot get DSI clock\n"); 1648 goto remove; 1649 } 1650 1651 dsi->clk_lp = devm_clk_get_optional(&pdev->dev, "lp"); 1652 if (IS_ERR(dsi->clk_lp)) { 1653 err = dev_err_probe(&pdev->dev, PTR_ERR(dsi->clk_lp), 1654 "cannot get low-power clock\n"); 1655 goto remove; 1656 } 1657 1658 dsi->clk_parent = devm_clk_get(&pdev->dev, "parent"); 1659 if (IS_ERR(dsi->clk_parent)) { 1660 err = dev_err_probe(&pdev->dev, PTR_ERR(dsi->clk_parent), 1661 "cannot get parent clock\n"); 1662 goto remove; 1663 } 1664 1665 dsi->vdd = devm_regulator_get(&pdev->dev, "avdd-dsi-csi"); 1666 if (IS_ERR(dsi->vdd)) { 1667 err = dev_err_probe(&pdev->dev, PTR_ERR(dsi->vdd), 1668 "cannot get VDD supply\n"); 1669 goto remove; 1670 } 1671 1672 if (dsi->config->has_mux_parent_clk) { 1673 err = tegra_dsi_setup_clocks(dsi); 1674 if (err < 0) { 1675 dev_err(&pdev->dev, "cannot setup clocks\n"); 1676 goto remove; 1677 } 1678 } 1679 1680 dsi->regs = devm_platform_ioremap_resource(pdev, 0); 1681 if (IS_ERR(dsi->regs)) { 1682 err = PTR_ERR(dsi->regs); 1683 goto remove; 1684 } 1685 1686 dsi->mipi = tegra_mipi_request(&pdev->dev, pdev->dev.of_node); 1687 if (IS_ERR(dsi->mipi)) { 1688 err = PTR_ERR(dsi->mipi); 1689 goto remove; 1690 } 1691 1692 dsi->host.ops = &tegra_dsi_host_ops; 1693 dsi->host.dev = &pdev->dev; 1694 1695 err = mipi_dsi_host_register(&dsi->host); 1696 if (err < 0) { 1697 dev_err(&pdev->dev, "failed to register DSI host: %d\n", err); 1698 goto mipi_free; 1699 } 1700 1701 platform_set_drvdata(pdev, dsi); 1702 pm_runtime_enable(&pdev->dev); 1703 1704 INIT_LIST_HEAD(&dsi->client.list); 1705 dsi->client.ops = &dsi_client_ops; 1706 dsi->client.dev = &pdev->dev; 1707 1708 err = host1x_client_register(&dsi->client); 1709 if (err < 0) { 1710 dev_err(&pdev->dev, "failed to register host1x client: %d\n", 1711 err); 1712 goto unregister; 1713 } 1714 1715 return 0; 1716 1717 unregister: 1718 pm_runtime_disable(&pdev->dev); 1719 mipi_dsi_host_unregister(&dsi->host); 1720 mipi_free: 1721 tegra_mipi_free(dsi->mipi); 1722 remove: 1723 tegra_output_remove(&dsi->output); 1724 return err; 1725 } 1726 1727 static void tegra_dsi_remove(struct platform_device *pdev) 1728 { 1729 struct tegra_dsi *dsi = platform_get_drvdata(pdev); 1730 1731 pm_runtime_disable(&pdev->dev); 1732 1733 host1x_client_unregister(&dsi->client); 1734 1735 tegra_output_remove(&dsi->output); 1736 1737 mipi_dsi_host_unregister(&dsi->host); 1738 tegra_mipi_free(dsi->mipi); 1739 } 1740 1741 static const struct tegra_dsi_config tegra20_dsi_config = { 1742 .has_multiple_pad_controls = false, 1743 .has_mux_parent_clk = false, 1744 }; 1745 1746 /* 1747 * Tegra30 allows DSIA/DSIB to be muxed to either PLL_D or PLL_D2; this is 1748 * simply not modeled in the clock driver yet. If this functionality is 1749 * required, the has_mux_parent_clk flag can be set to true once the clock 1750 * driver is patched. 1751 */ 1752 static const struct tegra_dsi_config tegra30_dsi_config = { 1753 .has_multiple_pad_controls = false, 1754 .has_mux_parent_clk = false, 1755 }; 1756 1757 static const struct tegra_dsi_config tegra114_dsi_config = { 1758 .has_multiple_pad_controls = true, 1759 .has_mux_parent_clk = true, 1760 }; 1761 1762 /* TODO: figure out why has_mux_parent_clk = true is necessary on Tegra124+ */ 1763 static const struct tegra_dsi_config tegra124_dsi_config = { 1764 .has_multiple_pad_controls = true, 1765 .has_mux_parent_clk = true, 1766 }; 1767 1768 static const struct of_device_id tegra_dsi_of_match[] = { 1769 { .compatible = "nvidia,tegra210-dsi", .data = &tegra124_dsi_config }, 1770 { .compatible = "nvidia,tegra132-dsi", .data = &tegra124_dsi_config }, 1771 { .compatible = "nvidia,tegra124-dsi", .data = &tegra124_dsi_config }, 1772 { .compatible = "nvidia,tegra114-dsi", .data = &tegra114_dsi_config }, 1773 { .compatible = "nvidia,tegra30-dsi", .data = &tegra30_dsi_config }, 1774 { .compatible = "nvidia,tegra20-dsi", .data = &tegra20_dsi_config }, 1775 { }, 1776 }; 1777 MODULE_DEVICE_TABLE(of, tegra_dsi_of_match); 1778 1779 struct platform_driver tegra_dsi_driver = { 1780 .driver = { 1781 .name = "tegra-dsi", 1782 .of_match_table = tegra_dsi_of_match, 1783 }, 1784 .probe = tegra_dsi_probe, 1785 .remove = tegra_dsi_remove, 1786 }; 1787