xref: /linux/drivers/gpu/drm/tegra/dpaux.c (revision 17cfcb68af3bc7d5e8ae08779b1853310a2949f3) 
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2013 NVIDIA Corporation
4  */
5 
6 #include <linux/clk.h>
7 #include <linux/delay.h>
8 #include <linux/gpio.h>
9 #include <linux/interrupt.h>
10 #include <linux/io.h>
11 #include <linux/module.h>
12 #include <linux/of_gpio.h>
13 #include <linux/pinctrl/pinconf-generic.h>
14 #include <linux/pinctrl/pinctrl.h>
15 #include <linux/pinctrl/pinmux.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/reset.h>
20 #include <linux/workqueue.h>
21 
22 #include <drm/drm_dp_helper.h>
23 #include <drm/drm_panel.h>
24 
25 #include "dp.h"
26 #include "dpaux.h"
27 #include "drm.h"
28 #include "trace.h"
29 
30 static DEFINE_MUTEX(dpaux_lock);
31 static LIST_HEAD(dpaux_list);
32 
33 struct tegra_dpaux {
34 	struct drm_dp_aux aux;
35 	struct device *dev;
36 
37 	void __iomem *regs;
38 	int irq;
39 
40 	struct tegra_output *output;
41 
42 	struct reset_control *rst;
43 	struct clk *clk_parent;
44 	struct clk *clk;
45 
46 	struct regulator *vdd;
47 
48 	struct completion complete;
49 	struct work_struct work;
50 	struct list_head list;
51 
52 #ifdef CONFIG_GENERIC_PINCONF
53 	struct pinctrl_dev *pinctrl;
54 	struct pinctrl_desc desc;
55 #endif
56 };
57 
58 static inline struct tegra_dpaux *to_dpaux(struct drm_dp_aux *aux)
59 {
60 	return container_of(aux, struct tegra_dpaux, aux);
61 }
62 
63 static inline struct tegra_dpaux *work_to_dpaux(struct work_struct *work)
64 {
65 	return container_of(work, struct tegra_dpaux, work);
66 }
67 
68 static inline u32 tegra_dpaux_readl(struct tegra_dpaux *dpaux,
69 				    unsigned int offset)
70 {
71 	u32 value = readl(dpaux->regs + (offset << 2));
72 
73 	trace_dpaux_readl(dpaux->dev, offset, value);
74 
75 	return value;
76 }
77 
78 static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux,
79 				      u32 value, unsigned int offset)
80 {
81 	trace_dpaux_writel(dpaux->dev, offset, value);
82 	writel(value, dpaux->regs + (offset << 2));
83 }
84 
85 static void tegra_dpaux_write_fifo(struct tegra_dpaux *dpaux, const u8 *buffer,
86 				   size_t size)
87 {
88 	size_t i, j;
89 
90 	for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
91 		size_t num = min_t(size_t, size - i * 4, 4);
92 		u32 value = 0;
93 
94 		for (j = 0; j < num; j++)
95 			value |= buffer[i * 4 + j] << (j * 8);
96 
97 		tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXDATA_WRITE(i));
98 	}
99 }
100 
101 static void tegra_dpaux_read_fifo(struct tegra_dpaux *dpaux, u8 *buffer,
102 				  size_t size)
103 {
104 	size_t i, j;
105 
106 	for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
107 		size_t num = min_t(size_t, size - i * 4, 4);
108 		u32 value;
109 
110 		value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXDATA_READ(i));
111 
112 		for (j = 0; j < num; j++)
113 			buffer[i * 4 + j] = value >> (j * 8);
114 	}
115 }
116 
117 static ssize_t tegra_dpaux_transfer(struct drm_dp_aux *aux,
118 				    struct drm_dp_aux_msg *msg)
119 {
120 	unsigned long timeout = msecs_to_jiffies(250);
121 	struct tegra_dpaux *dpaux = to_dpaux(aux);
122 	unsigned long status;
123 	ssize_t ret = 0;
124 	u32 value;
125 
126 	/* Tegra has 4x4 byte DP AUX transmit and receive FIFOs. */
127 	if (msg->size > 16)
128 		return -EINVAL;
129 
130 	/*
131 	 * Allow zero-sized messages only for I2C, in which case they specify
132 	 * address-only transactions.
133 	 */
134 	if (msg->size < 1) {
135 		switch (msg->request & ~DP_AUX_I2C_MOT) {
136 		case DP_AUX_I2C_WRITE_STATUS_UPDATE:
137 		case DP_AUX_I2C_WRITE:
138 		case DP_AUX_I2C_READ:
139 			value = DPAUX_DP_AUXCTL_CMD_ADDRESS_ONLY;
140 			break;
141 
142 		default:
143 			return -EINVAL;
144 		}
145 	} else {
146 		/* For non-zero-sized messages, set the CMDLEN field. */
147 		value = DPAUX_DP_AUXCTL_CMDLEN(msg->size - 1);
148 	}
149 
150 	switch (msg->request & ~DP_AUX_I2C_MOT) {
151 	case DP_AUX_I2C_WRITE:
152 		if (msg->request & DP_AUX_I2C_MOT)
153 			value |= DPAUX_DP_AUXCTL_CMD_MOT_WR;
154 		else
155 			value |= DPAUX_DP_AUXCTL_CMD_I2C_WR;
156 
157 		break;
158 
159 	case DP_AUX_I2C_READ:
160 		if (msg->request & DP_AUX_I2C_MOT)
161 			value |= DPAUX_DP_AUXCTL_CMD_MOT_RD;
162 		else
163 			value |= DPAUX_DP_AUXCTL_CMD_I2C_RD;
164 
165 		break;
166 
167 	case DP_AUX_I2C_WRITE_STATUS_UPDATE:
168 		if (msg->request & DP_AUX_I2C_MOT)
169 			value |= DPAUX_DP_AUXCTL_CMD_MOT_RQ;
170 		else
171 			value |= DPAUX_DP_AUXCTL_CMD_I2C_RQ;
172 
173 		break;
174 
175 	case DP_AUX_NATIVE_WRITE:
176 		value |= DPAUX_DP_AUXCTL_CMD_AUX_WR;
177 		break;
178 
179 	case DP_AUX_NATIVE_READ:
180 		value |= DPAUX_DP_AUXCTL_CMD_AUX_RD;
181 		break;
182 
183 	default:
184 		return -EINVAL;
185 	}
186 
187 	tegra_dpaux_writel(dpaux, msg->address, DPAUX_DP_AUXADDR);
188 	tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
189 
190 	if ((msg->request & DP_AUX_I2C_READ) == 0) {
191 		tegra_dpaux_write_fifo(dpaux, msg->buffer, msg->size);
192 		ret = msg->size;
193 	}
194 
195 	/* start transaction */
196 	value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXCTL);
197 	value |= DPAUX_DP_AUXCTL_TRANSACTREQ;
198 	tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
199 
200 	status = wait_for_completion_timeout(&dpaux->complete, timeout);
201 	if (!status)
202 		return -ETIMEDOUT;
203 
204 	/* read status and clear errors */
205 	value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
206 	tegra_dpaux_writel(dpaux, 0xf00, DPAUX_DP_AUXSTAT);
207 
208 	if (value & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR)
209 		return -ETIMEDOUT;
210 
211 	if ((value & DPAUX_DP_AUXSTAT_RX_ERROR) ||
212 	    (value & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR) ||
213 	    (value & DPAUX_DP_AUXSTAT_NO_STOP_ERROR))
214 		return -EIO;
215 
216 	switch ((value & DPAUX_DP_AUXSTAT_REPLY_TYPE_MASK) >> 16) {
217 	case 0x00:
218 		msg->reply = DP_AUX_NATIVE_REPLY_ACK;
219 		break;
220 
221 	case 0x01:
222 		msg->reply = DP_AUX_NATIVE_REPLY_NACK;
223 		break;
224 
225 	case 0x02:
226 		msg->reply = DP_AUX_NATIVE_REPLY_DEFER;
227 		break;
228 
229 	case 0x04:
230 		msg->reply = DP_AUX_I2C_REPLY_NACK;
231 		break;
232 
233 	case 0x08:
234 		msg->reply = DP_AUX_I2C_REPLY_DEFER;
235 		break;
236 	}
237 
238 	if ((msg->size > 0) && (msg->reply == DP_AUX_NATIVE_REPLY_ACK)) {
239 		if (msg->request & DP_AUX_I2C_READ) {
240 			size_t count = value & DPAUX_DP_AUXSTAT_REPLY_MASK;
241 
242 			if (WARN_ON(count != msg->size))
243 				count = min_t(size_t, count, msg->size);
244 
245 			tegra_dpaux_read_fifo(dpaux, msg->buffer, count);
246 			ret = count;
247 		}
248 	}
249 
250 	return ret;
251 }
252 
253 static void tegra_dpaux_hotplug(struct work_struct *work)
254 {
255 	struct tegra_dpaux *dpaux = work_to_dpaux(work);
256 
257 	if (dpaux->output)
258 		drm_helper_hpd_irq_event(dpaux->output->connector.dev);
259 }
260 
261 static irqreturn_t tegra_dpaux_irq(int irq, void *data)
262 {
263 	struct tegra_dpaux *dpaux = data;
264 	irqreturn_t ret = IRQ_HANDLED;
265 	u32 value;
266 
267 	/* clear interrupts */
268 	value = tegra_dpaux_readl(dpaux, DPAUX_INTR_AUX);
269 	tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
270 
271 	if (value & (DPAUX_INTR_PLUG_EVENT | DPAUX_INTR_UNPLUG_EVENT))
272 		schedule_work(&dpaux->work);
273 
274 	if (value & DPAUX_INTR_IRQ_EVENT) {
275 		/* TODO: handle this */
276 	}
277 
278 	if (value & DPAUX_INTR_AUX_DONE)
279 		complete(&dpaux->complete);
280 
281 	return ret;
282 }
283 
284 enum tegra_dpaux_functions {
285 	DPAUX_PADCTL_FUNC_AUX,
286 	DPAUX_PADCTL_FUNC_I2C,
287 	DPAUX_PADCTL_FUNC_OFF,
288 };
289 
290 static void tegra_dpaux_pad_power_down(struct tegra_dpaux *dpaux)
291 {
292 	u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
293 
294 	value |= DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
295 
296 	tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
297 }
298 
299 static void tegra_dpaux_pad_power_up(struct tegra_dpaux *dpaux)
300 {
301 	u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
302 
303 	value &= ~DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
304 
305 	tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
306 }
307 
308 static int tegra_dpaux_pad_config(struct tegra_dpaux *dpaux, unsigned function)
309 {
310 	u32 value;
311 
312 	switch (function) {
313 	case DPAUX_PADCTL_FUNC_AUX:
314 		value = DPAUX_HYBRID_PADCTL_AUX_CMH(2) |
315 			DPAUX_HYBRID_PADCTL_AUX_DRVZ(4) |
316 			DPAUX_HYBRID_PADCTL_AUX_DRVI(0x18) |
317 			DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV |
318 			DPAUX_HYBRID_PADCTL_MODE_AUX;
319 		break;
320 
321 	case DPAUX_PADCTL_FUNC_I2C:
322 		value = DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV |
323 			DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV |
324 			DPAUX_HYBRID_PADCTL_AUX_CMH(2) |
325 			DPAUX_HYBRID_PADCTL_AUX_DRVZ(4) |
326 			DPAUX_HYBRID_PADCTL_AUX_DRVI(0x18) |
327 			DPAUX_HYBRID_PADCTL_MODE_I2C;
328 		break;
329 
330 	case DPAUX_PADCTL_FUNC_OFF:
331 		tegra_dpaux_pad_power_down(dpaux);
332 		return 0;
333 
334 	default:
335 		return -ENOTSUPP;
336 	}
337 
338 	tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL);
339 	tegra_dpaux_pad_power_up(dpaux);
340 
341 	return 0;
342 }
343 
344 #ifdef CONFIG_GENERIC_PINCONF
345 static const struct pinctrl_pin_desc tegra_dpaux_pins[] = {
346 	PINCTRL_PIN(0, "DP_AUX_CHx_P"),
347 	PINCTRL_PIN(1, "DP_AUX_CHx_N"),
348 };
349 
350 static const unsigned tegra_dpaux_pin_numbers[] = { 0, 1 };
351 
352 static const char * const tegra_dpaux_groups[] = {
353 	"dpaux-io",
354 };
355 
356 static const char * const tegra_dpaux_functions[] = {
357 	"aux",
358 	"i2c",
359 	"off",
360 };
361 
362 static int tegra_dpaux_get_groups_count(struct pinctrl_dev *pinctrl)
363 {
364 	return ARRAY_SIZE(tegra_dpaux_groups);
365 }
366 
367 static const char *tegra_dpaux_get_group_name(struct pinctrl_dev *pinctrl,
368 					      unsigned int group)
369 {
370 	return tegra_dpaux_groups[group];
371 }
372 
373 static int tegra_dpaux_get_group_pins(struct pinctrl_dev *pinctrl,
374 				      unsigned group, const unsigned **pins,
375 				      unsigned *num_pins)
376 {
377 	*pins = tegra_dpaux_pin_numbers;
378 	*num_pins = ARRAY_SIZE(tegra_dpaux_pin_numbers);
379 
380 	return 0;
381 }
382 
383 static const struct pinctrl_ops tegra_dpaux_pinctrl_ops = {
384 	.get_groups_count = tegra_dpaux_get_groups_count,
385 	.get_group_name = tegra_dpaux_get_group_name,
386 	.get_group_pins = tegra_dpaux_get_group_pins,
387 	.dt_node_to_map = pinconf_generic_dt_node_to_map_group,
388 	.dt_free_map = pinconf_generic_dt_free_map,
389 };
390 
391 static int tegra_dpaux_get_functions_count(struct pinctrl_dev *pinctrl)
392 {
393 	return ARRAY_SIZE(tegra_dpaux_functions);
394 }
395 
396 static const char *tegra_dpaux_get_function_name(struct pinctrl_dev *pinctrl,
397 						 unsigned int function)
398 {
399 	return tegra_dpaux_functions[function];
400 }
401 
402 static int tegra_dpaux_get_function_groups(struct pinctrl_dev *pinctrl,
403 					   unsigned int function,
404 					   const char * const **groups,
405 					   unsigned * const num_groups)
406 {
407 	*num_groups = ARRAY_SIZE(tegra_dpaux_groups);
408 	*groups = tegra_dpaux_groups;
409 
410 	return 0;
411 }
412 
413 static int tegra_dpaux_set_mux(struct pinctrl_dev *pinctrl,
414 			       unsigned int function, unsigned int group)
415 {
416 	struct tegra_dpaux *dpaux = pinctrl_dev_get_drvdata(pinctrl);
417 
418 	return tegra_dpaux_pad_config(dpaux, function);
419 }
420 
421 static const struct pinmux_ops tegra_dpaux_pinmux_ops = {
422 	.get_functions_count = tegra_dpaux_get_functions_count,
423 	.get_function_name = tegra_dpaux_get_function_name,
424 	.get_function_groups = tegra_dpaux_get_function_groups,
425 	.set_mux = tegra_dpaux_set_mux,
426 };
427 #endif
428 
429 static int tegra_dpaux_probe(struct platform_device *pdev)
430 {
431 	struct tegra_dpaux *dpaux;
432 	struct resource *regs;
433 	u32 value;
434 	int err;
435 
436 	dpaux = devm_kzalloc(&pdev->dev, sizeof(*dpaux), GFP_KERNEL);
437 	if (!dpaux)
438 		return -ENOMEM;
439 
440 	INIT_WORK(&dpaux->work, tegra_dpaux_hotplug);
441 	init_completion(&dpaux->complete);
442 	INIT_LIST_HEAD(&dpaux->list);
443 	dpaux->dev = &pdev->dev;
444 
445 	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
446 	dpaux->regs = devm_ioremap_resource(&pdev->dev, regs);
447 	if (IS_ERR(dpaux->regs))
448 		return PTR_ERR(dpaux->regs);
449 
450 	dpaux->irq = platform_get_irq(pdev, 0);
451 	if (dpaux->irq < 0) {
452 		dev_err(&pdev->dev, "failed to get IRQ\n");
453 		return -ENXIO;
454 	}
455 
456 	if (!pdev->dev.pm_domain) {
457 		dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux");
458 		if (IS_ERR(dpaux->rst)) {
459 			dev_err(&pdev->dev,
460 				"failed to get reset control: %ld\n",
461 				PTR_ERR(dpaux->rst));
462 			return PTR_ERR(dpaux->rst);
463 		}
464 	}
465 
466 	dpaux->clk = devm_clk_get(&pdev->dev, NULL);
467 	if (IS_ERR(dpaux->clk)) {
468 		dev_err(&pdev->dev, "failed to get module clock: %ld\n",
469 			PTR_ERR(dpaux->clk));
470 		return PTR_ERR(dpaux->clk);
471 	}
472 
473 	dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent");
474 	if (IS_ERR(dpaux->clk_parent)) {
475 		dev_err(&pdev->dev, "failed to get parent clock: %ld\n",
476 			PTR_ERR(dpaux->clk_parent));
477 		return PTR_ERR(dpaux->clk_parent);
478 	}
479 
480 	err = clk_set_rate(dpaux->clk_parent, 270000000);
481 	if (err < 0) {
482 		dev_err(&pdev->dev, "failed to set clock to 270 MHz: %d\n",
483 			err);
484 		return err;
485 	}
486 
487 	dpaux->vdd = devm_regulator_get_optional(&pdev->dev, "vdd");
488 	if (IS_ERR(dpaux->vdd)) {
489 		if (PTR_ERR(dpaux->vdd) != -ENODEV) {
490 			if (PTR_ERR(dpaux->vdd) != -EPROBE_DEFER)
491 				dev_err(&pdev->dev,
492 					"failed to get VDD supply: %ld\n",
493 					PTR_ERR(dpaux->vdd));
494 
495 			return PTR_ERR(dpaux->vdd);
496 		}
497 	}
498 
499 	platform_set_drvdata(pdev, dpaux);
500 	pm_runtime_enable(&pdev->dev);
501 	pm_runtime_get_sync(&pdev->dev);
502 
503 	err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0,
504 			       dev_name(dpaux->dev), dpaux);
505 	if (err < 0) {
506 		dev_err(dpaux->dev, "failed to request IRQ#%u: %d\n",
507 			dpaux->irq, err);
508 		return err;
509 	}
510 
511 	disable_irq(dpaux->irq);
512 
513 	dpaux->aux.transfer = tegra_dpaux_transfer;
514 	dpaux->aux.dev = &pdev->dev;
515 
516 	err = drm_dp_aux_register(&dpaux->aux);
517 	if (err < 0)
518 		return err;
519 
520 	/*
521 	 * Assume that by default the DPAUX/I2C pads will be used for HDMI,
522 	 * so power them up and configure them in I2C mode.
523 	 *
524 	 * The DPAUX code paths reconfigure the pads in AUX mode, but there
525 	 * is no possibility to perform the I2C mode configuration in the
526 	 * HDMI path.
527 	 */
528 	err = tegra_dpaux_pad_config(dpaux, DPAUX_PADCTL_FUNC_I2C);
529 	if (err < 0)
530 		return err;
531 
532 #ifdef CONFIG_GENERIC_PINCONF
533 	dpaux->desc.name = dev_name(&pdev->dev);
534 	dpaux->desc.pins = tegra_dpaux_pins;
535 	dpaux->desc.npins = ARRAY_SIZE(tegra_dpaux_pins);
536 	dpaux->desc.pctlops = &tegra_dpaux_pinctrl_ops;
537 	dpaux->desc.pmxops = &tegra_dpaux_pinmux_ops;
538 	dpaux->desc.owner = THIS_MODULE;
539 
540 	dpaux->pinctrl = devm_pinctrl_register(&pdev->dev, &dpaux->desc, dpaux);
541 	if (IS_ERR(dpaux->pinctrl)) {
542 		dev_err(&pdev->dev, "failed to register pincontrol\n");
543 		return PTR_ERR(dpaux->pinctrl);
544 	}
545 #endif
546 	/* enable and clear all interrupts */
547 	value = DPAUX_INTR_AUX_DONE | DPAUX_INTR_IRQ_EVENT |
548 		DPAUX_INTR_UNPLUG_EVENT | DPAUX_INTR_PLUG_EVENT;
549 	tegra_dpaux_writel(dpaux, value, DPAUX_INTR_EN_AUX);
550 	tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
551 
552 	mutex_lock(&dpaux_lock);
553 	list_add_tail(&dpaux->list, &dpaux_list);
554 	mutex_unlock(&dpaux_lock);
555 
556 	return 0;
557 }
558 
559 static int tegra_dpaux_remove(struct platform_device *pdev)
560 {
561 	struct tegra_dpaux *dpaux = platform_get_drvdata(pdev);
562 
563 	cancel_work_sync(&dpaux->work);
564 
565 	/* make sure pads are powered down when not in use */
566 	tegra_dpaux_pad_power_down(dpaux);
567 
568 	pm_runtime_put(&pdev->dev);
569 	pm_runtime_disable(&pdev->dev);
570 
571 	drm_dp_aux_unregister(&dpaux->aux);
572 
573 	mutex_lock(&dpaux_lock);
574 	list_del(&dpaux->list);
575 	mutex_unlock(&dpaux_lock);
576 
577 	return 0;
578 }
579 
580 #ifdef CONFIG_PM
581 static int tegra_dpaux_suspend(struct device *dev)
582 {
583 	struct tegra_dpaux *dpaux = dev_get_drvdata(dev);
584 	int err = 0;
585 
586 	if (dpaux->rst) {
587 		err = reset_control_assert(dpaux->rst);
588 		if (err < 0) {
589 			dev_err(dev, "failed to assert reset: %d\n", err);
590 			return err;
591 		}
592 	}
593 
594 	usleep_range(1000, 2000);
595 
596 	clk_disable_unprepare(dpaux->clk_parent);
597 	clk_disable_unprepare(dpaux->clk);
598 
599 	return err;
600 }
601 
602 static int tegra_dpaux_resume(struct device *dev)
603 {
604 	struct tegra_dpaux *dpaux = dev_get_drvdata(dev);
605 	int err;
606 
607 	err = clk_prepare_enable(dpaux->clk);
608 	if (err < 0) {
609 		dev_err(dev, "failed to enable clock: %d\n", err);
610 		return err;
611 	}
612 
613 	err = clk_prepare_enable(dpaux->clk_parent);
614 	if (err < 0) {
615 		dev_err(dev, "failed to enable parent clock: %d\n", err);
616 		goto disable_clk;
617 	}
618 
619 	usleep_range(1000, 2000);
620 
621 	if (dpaux->rst) {
622 		err = reset_control_deassert(dpaux->rst);
623 		if (err < 0) {
624 			dev_err(dev, "failed to deassert reset: %d\n", err);
625 			goto disable_parent;
626 		}
627 
628 		usleep_range(1000, 2000);
629 	}
630 
631 	return 0;
632 
633 disable_parent:
634 	clk_disable_unprepare(dpaux->clk_parent);
635 disable_clk:
636 	clk_disable_unprepare(dpaux->clk);
637 	return err;
638 }
639 #endif
640 
641 static const struct dev_pm_ops tegra_dpaux_pm_ops = {
642 	SET_RUNTIME_PM_OPS(tegra_dpaux_suspend, tegra_dpaux_resume, NULL)
643 };
644 
645 static const struct of_device_id tegra_dpaux_of_match[] = {
646 	{ .compatible = "nvidia,tegra194-dpaux", },
647 	{ .compatible = "nvidia,tegra186-dpaux", },
648 	{ .compatible = "nvidia,tegra210-dpaux", },
649 	{ .compatible = "nvidia,tegra124-dpaux", },
650 	{ },
651 };
652 MODULE_DEVICE_TABLE(of, tegra_dpaux_of_match);
653 
654 struct platform_driver tegra_dpaux_driver = {
655 	.driver = {
656 		.name = "tegra-dpaux",
657 		.of_match_table = tegra_dpaux_of_match,
658 		.pm = &tegra_dpaux_pm_ops,
659 	},
660 	.probe = tegra_dpaux_probe,
661 	.remove = tegra_dpaux_remove,
662 };
663 
664 struct drm_dp_aux *drm_dp_aux_find_by_of_node(struct device_node *np)
665 {
666 	struct tegra_dpaux *dpaux;
667 
668 	mutex_lock(&dpaux_lock);
669 
670 	list_for_each_entry(dpaux, &dpaux_list, list)
671 		if (np == dpaux->dev->of_node) {
672 			mutex_unlock(&dpaux_lock);
673 			return &dpaux->aux;
674 		}
675 
676 	mutex_unlock(&dpaux_lock);
677 
678 	return NULL;
679 }
680 
681 int drm_dp_aux_attach(struct drm_dp_aux *aux, struct tegra_output *output)
682 {
683 	struct tegra_dpaux *dpaux = to_dpaux(aux);
684 	unsigned long timeout;
685 	int err;
686 
687 	output->connector.polled = DRM_CONNECTOR_POLL_HPD;
688 	dpaux->output = output;
689 
690 	err = regulator_enable(dpaux->vdd);
691 	if (err < 0)
692 		return err;
693 
694 	timeout = jiffies + msecs_to_jiffies(250);
695 
696 	while (time_before(jiffies, timeout)) {
697 		enum drm_connector_status status;
698 
699 		status = drm_dp_aux_detect(aux);
700 		if (status == connector_status_connected) {
701 			enable_irq(dpaux->irq);
702 			return 0;
703 		}
704 
705 		usleep_range(1000, 2000);
706 	}
707 
708 	return -ETIMEDOUT;
709 }
710 
711 int drm_dp_aux_detach(struct drm_dp_aux *aux)
712 {
713 	struct tegra_dpaux *dpaux = to_dpaux(aux);
714 	unsigned long timeout;
715 	int err;
716 
717 	disable_irq(dpaux->irq);
718 
719 	err = regulator_disable(dpaux->vdd);
720 	if (err < 0)
721 		return err;
722 
723 	timeout = jiffies + msecs_to_jiffies(250);
724 
725 	while (time_before(jiffies, timeout)) {
726 		enum drm_connector_status status;
727 
728 		status = drm_dp_aux_detect(aux);
729 		if (status == connector_status_disconnected) {
730 			dpaux->output = NULL;
731 			return 0;
732 		}
733 
734 		usleep_range(1000, 2000);
735 	}
736 
737 	return -ETIMEDOUT;
738 }
739 
740 enum drm_connector_status drm_dp_aux_detect(struct drm_dp_aux *aux)
741 {
742 	struct tegra_dpaux *dpaux = to_dpaux(aux);
743 	u32 value;
744 
745 	value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
746 
747 	if (value & DPAUX_DP_AUXSTAT_HPD_STATUS)
748 		return connector_status_connected;
749 
750 	return connector_status_disconnected;
751 }
752 
753 int drm_dp_aux_enable(struct drm_dp_aux *aux)
754 {
755 	struct tegra_dpaux *dpaux = to_dpaux(aux);
756 
757 	return tegra_dpaux_pad_config(dpaux, DPAUX_PADCTL_FUNC_AUX);
758 }
759 
760 int drm_dp_aux_disable(struct drm_dp_aux *aux)
761 {
762 	struct tegra_dpaux *dpaux = to_dpaux(aux);
763 
764 	tegra_dpaux_pad_power_down(dpaux);
765 
766 	return 0;
767 }
768 
769 int drm_dp_aux_prepare(struct drm_dp_aux *aux, u8 encoding)
770 {
771 	int err;
772 
773 	err = drm_dp_dpcd_writeb(aux, DP_MAIN_LINK_CHANNEL_CODING_SET,
774 				 encoding);
775 	if (err < 0)
776 		return err;
777 
778 	return 0;
779 }
780 
781 int drm_dp_aux_train(struct drm_dp_aux *aux, struct drm_dp_link *link,
782 		     u8 pattern)
783 {
784 	u8 tp = pattern & DP_TRAINING_PATTERN_MASK;
785 	u8 status[DP_LINK_STATUS_SIZE], values[4];
786 	unsigned int i;
787 	int err;
788 
789 	err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, pattern);
790 	if (err < 0)
791 		return err;
792 
793 	if (tp == DP_TRAINING_PATTERN_DISABLE)
794 		return 0;
795 
796 	for (i = 0; i < link->num_lanes; i++)
797 		values[i] = DP_TRAIN_MAX_PRE_EMPHASIS_REACHED |
798 			    DP_TRAIN_PRE_EMPH_LEVEL_0 |
799 			    DP_TRAIN_MAX_SWING_REACHED |
800 			    DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
801 
802 	err = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, values,
803 				link->num_lanes);
804 	if (err < 0)
805 		return err;
806 
807 	usleep_range(500, 1000);
808 
809 	err = drm_dp_dpcd_read_link_status(aux, status);
810 	if (err < 0)
811 		return err;
812 
813 	switch (tp) {
814 	case DP_TRAINING_PATTERN_1:
815 		if (!drm_dp_clock_recovery_ok(status, link->num_lanes))
816 			return -EAGAIN;
817 
818 		break;
819 
820 	case DP_TRAINING_PATTERN_2:
821 		if (!drm_dp_channel_eq_ok(status, link->num_lanes))
822 			return -EAGAIN;
823 
824 		break;
825 
826 	default:
827 		dev_err(aux->dev, "unsupported training pattern %u\n", tp);
828 		return -EINVAL;
829 	}
830 
831 	err = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, 0);
832 	if (err < 0)
833 		return err;
834 
835 	return 0;
836 }
837